mirror of
https://github.com/AsahiLinux/u-boot
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mmc: Tegra2: SD/MMC driver for Seaboard - eMMC on SDMMC4, SDIO on SDMMC3
Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Tom Warren
Andy Fleming
parent
68d4230c3c
commit
21ef6a109c
7 changed files with 751 additions and 0 deletions
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@ -191,4 +191,9 @@ struct clk_rst_ctlr {
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#define CPCON (1 << 8)
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#define SWR_SDMMC4_RST (1 << 15)
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#define CLK_ENB_SDMMC4 (1 << 15)
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#define SWR_SDMMC3_RST (1 << 5)
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#define CLK_ENB_SDMMC3 (1 << 5)
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#endif /* CLK_RST_H */
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@ -51,5 +51,11 @@ struct pmux_tri_ctlr {
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#define Z_GMC (1 << 29)
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#define Z_IRRX (1 << 20)
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#define Z_IRTX (1 << 19)
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#define Z_GMA (1 << 28)
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#define Z_GME (1 << 0)
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#define Z_ATB (1 << 1)
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#define Z_SDB (1 << 15)
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#define Z_SDC (1 << 1)
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#define Z_SDD (1 << 2)
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#endif /* PINMUX_H */
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@ -32,6 +32,10 @@
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#include <asm/arch/uart.h>
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#include "board.h"
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#ifdef CONFIG_TEGRA2_MMC
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#include <mmc.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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const struct tegra2_sysinfo sysinfo = {
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@ -170,6 +174,116 @@ static void pin_mux_uart(void)
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#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
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}
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/*
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* Routine: clock_init_mmc
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* Description: init the PLL and clocks for the SDMMC controllers
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*/
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static void clock_init_mmc(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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/* Do the SDMMC resets/clock enables */
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/* Assert Reset to SDMMC4 */
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reg = readl(&clkrst->crc_rst_dev_l);
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reg |= SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 1 */
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writel(reg, &clkrst->crc_rst_dev_l);
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/* Enable clk to SDMMC4 */
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reg = readl(&clkrst->crc_clk_out_enb_l);
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reg |= CLK_ENB_SDMMC4; /* CLK_ENB_SDMMC4 = 1 */
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writel(reg, &clkrst->crc_clk_out_enb_l);
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/* Enable pllp_out0 to SDMMC4 */
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reg = readl(&clkrst->crc_clk_src_sdmmc4);
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reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */
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reg |= (10 << 1); /* n-1, 11-1 shl 1 */
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writel(reg, &clkrst->crc_clk_src_sdmmc4);
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/*
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* As per the Tegra2 TRM, section 5.3.4:
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* 'Wait 2 us for the clock to flush through the pipe/logic'
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*/
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udelay(2);
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/* De-assert reset to SDMMC4 */
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reg = readl(&clkrst->crc_rst_dev_l);
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reg &= ~SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 0 */
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writel(reg, &clkrst->crc_rst_dev_l);
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/* Assert Reset to SDMMC3 */
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reg = readl(&clkrst->crc_rst_dev_u);
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reg |= SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 1 */
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writel(reg, &clkrst->crc_rst_dev_u);
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/* Enable clk to SDMMC3 */
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reg = readl(&clkrst->crc_clk_out_enb_u);
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reg |= CLK_ENB_SDMMC3; /* CLK_ENB_SDMMC3 = 1 */
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writel(reg, &clkrst->crc_clk_out_enb_u);
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/* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
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reg = readl(&clkrst->crc_clk_src_sdmmc3);
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reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */
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reg |= (10 << 1); /* n-1, 11-1 shl 1 */
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writel(reg, &clkrst->crc_clk_src_sdmmc3);
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/* wait for 2us */
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udelay(2);
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/* De-assert reset to SDMMC3 */
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reg = readl(&clkrst->crc_rst_dev_u);
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reg &= ~SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 0 */
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writel(reg, &clkrst->crc_rst_dev_u);
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}
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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static void pin_mux_mmc(void)
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{
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 reg;
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/* SDMMC4 */
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/* config 2, x8 on 2nd set of pins */
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reg = readl(&pmt->pmt_ctl_a);
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reg |= (3 << 16); /* ATB_SEL [17:16] = 11 SDIO4 */
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writel(reg, &pmt->pmt_ctl_a);
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reg = readl(&pmt->pmt_ctl_b);
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reg |= (3 << 0); /* GMA_SEL [1:0] = 11 SDIO4 */
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writel(reg, &pmt->pmt_ctl_b);
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reg = readl(&pmt->pmt_ctl_d);
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reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */
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writel(reg, &pmt->pmt_ctl_d);
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reg = readl(&pmt->pmt_tri_a);
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reg &= ~Z_ATB; /* Z_ATB = normal (0) */
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reg &= ~Z_GMA; /* Z_GMA = normal (0) */
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writel(reg, &pmt->pmt_tri_a);
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reg = readl(&pmt->pmt_tri_b);
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reg &= ~Z_GME; /* Z_GME = normal (0) */
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writel(reg, &pmt->pmt_tri_b);
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/* SDMMC3 */
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/* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
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reg = readl(&pmt->pmt_ctl_d);
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reg &= 0xFFFF03FF;
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reg |= (2 << 10); /* SDB_SEL [11:10] = 01 SDIO3 */
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reg |= (2 << 12); /* SDC_SEL [13:12] = 01 SDIO3 */
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reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */
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writel(reg, &pmt->pmt_ctl_d);
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reg = readl(&pmt->pmt_tri_b);
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reg &= ~Z_SDC; /* Z_SDC = normal (0) */
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reg &= ~Z_SDD; /* Z_SDD = normal (0) */
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writel(reg, &pmt->pmt_tri_b);
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reg = readl(&pmt->pmt_tri_d);
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reg &= ~Z_SDB; /* Z_SDB = normal (0) */
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writel(reg, &pmt->pmt_tri_d);
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}
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/*
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* Routine: clock_init
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* Description: Do individual peripheral clock reset/enables
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@ -210,3 +324,36 @@ int board_init(void)
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return 0;
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}
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#ifdef CONFIG_TEGRA2_MMC
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/* this is a weak define that we are overriding */
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int board_mmc_init(bd_t *bd)
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{
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debug("board_mmc_init called\n");
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/* Enable clocks, muxes, etc. for SDMMC controllers */
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clock_init_mmc();
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pin_mux_mmc();
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debug("board_mmc_init: init eMMC\n");
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/* init dev 0, eMMC chip, with 4-bit bus */
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tegra2_mmc_init(0, 4);
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debug("board_mmc_init: init SD slot\n");
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/* init dev 1, SD slot, with 4-bit bus */
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tegra2_mmc_init(1, 4);
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return 0;
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}
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/* this is a weak define that we are overriding */
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int board_mmc_getcd(u8 *cd, struct mmc *mmc)
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{
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debug("board_mmc_getcd called\n");
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/*
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* Hard-code CD presence for now. Need to add GPIO inputs
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* for Seaboard & Harmony (& Kaen/Aebl/Wario?)
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*/
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*cd = 1;
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return 0;
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}
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#endif
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@ -29,5 +29,6 @@ void clock_init(void);
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void pinmux_init(void);
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void gpio_init(void);
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void gpio_config_uart(void);
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int tegra2_mmc_init(int dev_index, int bus_width);
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#endif /* BOARD_H */
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@ -38,6 +38,7 @@ COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
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COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
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COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
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COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o
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COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o
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COBJS := $(COBJS-y)
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SRCS := $(COBJS:.o=.c)
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510
drivers/mmc/tegra2_mmc.c
Normal file
510
drivers/mmc/tegra2_mmc.c
Normal file
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@ -0,0 +1,510 @@
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/*
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* (C) Copyright 2009 SAMSUNG Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Jaehoon Chung <jh80.chung@samsung.com>
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* Portions Copyright 2011 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/arch/clk_rst.h>
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#include "tegra2_mmc.h"
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/* support 4 mmc hosts */
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struct mmc mmc_dev[4];
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struct mmc_host mmc_host[4];
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static inline struct tegra2_mmc *tegra2_get_base_mmc(int dev_index)
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{
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unsigned long offset;
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debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
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switch (dev_index) {
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case 0:
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offset = TEGRA2_SDMMC4_BASE;
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break;
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case 1:
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offset = TEGRA2_SDMMC3_BASE;
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break;
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case 2:
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offset = TEGRA2_SDMMC2_BASE;
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break;
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case 3:
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offset = TEGRA2_SDMMC1_BASE;
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break;
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default:
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offset = TEGRA2_SDMMC4_BASE;
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break;
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}
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return (struct tegra2_mmc *)(offset);
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}
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static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
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{
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unsigned char ctrl;
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debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
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(u32)data->dest, data->blocks, data->blocksize);
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writel((u32)data->dest, &host->reg->sysad);
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/*
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* DMASEL[4:3]
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* 00 = Selects SDMA
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* 01 = Reserved
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* 10 = Selects 32-bit Address ADMA2
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* 11 = Selects 64-bit Address ADMA2
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*/
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ctrl = readb(&host->reg->hostctl);
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ctrl &= ~(3 << 3); /* SDMA */
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writeb(ctrl, &host->reg->hostctl);
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/* We do not handle DMA boundaries, so set it to max (512 KiB) */
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writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
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writew(data->blocks, &host->reg->blkcnt);
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}
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static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
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{
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unsigned short mode;
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debug(" mmc_set_transfer_mode called\n");
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/*
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* TRNMOD
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* MUL1SIN0[5] : Multi/Single Block Select
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* RD1WT0[4] : Data Transfer Direction Select
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* 1 = read
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* 0 = write
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* ENACMD12[2] : Auto CMD12 Enable
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* ENBLKCNT[1] : Block Count Enable
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* ENDMA[0] : DMA Enable
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*/
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mode = (1 << 1) | (1 << 0);
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if (data->blocks > 1)
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mode |= (1 << 5);
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if (data->flags & MMC_DATA_READ)
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mode |= (1 << 4);
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writew(mode, &host->reg->trnmod);
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}
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static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct mmc_host *host = (struct mmc_host *)mmc->priv;
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int flags, i;
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unsigned int timeout;
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unsigned int mask;
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unsigned int retry = 0x100000;
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debug(" mmc_send_cmd called\n");
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/* Wait max 10 ms */
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timeout = 10;
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/*
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* PRNSTS
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* CMDINHDAT[1] : Command Inhibit (DAT)
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* CMDINHCMD[0] : Command Inhibit (CMD)
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*/
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mask = (1 << 0);
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if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
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mask |= (1 << 1);
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/*
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* We shouldn't wait for data inhibit for stop commands, even
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* though they might use busy signaling
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*/
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if (data)
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mask &= ~(1 << 1);
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while (readl(&host->reg->prnsts) & mask) {
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if (timeout == 0) {
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printf("%s: timeout error\n", __func__);
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return -1;
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}
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timeout--;
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udelay(1000);
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}
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if (data)
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mmc_prepare_data(host, data);
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debug("cmd->arg: %08x\n", cmd->cmdarg);
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writel(cmd->cmdarg, &host->reg->argument);
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if (data)
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mmc_set_transfer_mode(host, data);
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if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
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return -1;
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/*
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* CMDREG
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* CMDIDX[13:8] : Command index
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* DATAPRNT[5] : Data Present Select
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* ENCMDIDX[4] : Command Index Check Enable
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* ENCMDCRC[3] : Command CRC Check Enable
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* RSPTYP[1:0]
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* 00 = No Response
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* 01 = Length 136
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* 10 = Length 48
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* 11 = Length 48 Check busy after response
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*/
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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flags = 0;
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else if (cmd->resp_type & MMC_RSP_136)
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flags = (1 << 0);
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else if (cmd->resp_type & MMC_RSP_BUSY)
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flags = (3 << 0);
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else
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flags = (2 << 0);
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= (1 << 3);
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if (cmd->resp_type & MMC_RSP_OPCODE)
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flags |= (1 << 4);
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if (data)
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flags |= (1 << 5);
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debug("cmd: %d\n", cmd->cmdidx);
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writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
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for (i = 0; i < retry; i++) {
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mask = readl(&host->reg->norintsts);
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/* Command Complete */
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if (mask & (1 << 0)) {
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if (!data)
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writel(mask, &host->reg->norintsts);
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break;
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}
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}
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if (i == retry) {
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printf("%s: waiting for status update\n", __func__);
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return TIMEOUT;
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}
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if (mask & (1 << 16)) {
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/* Timeout Error */
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debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
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return TIMEOUT;
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} else if (mask & (1 << 15)) {
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/* Error Interrupt */
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debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
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return -1;
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}
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136) {
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/* CRC is stripped so we need to do some shifting. */
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for (i = 0; i < 4; i++) {
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unsigned int offset =
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(unsigned int)(&host->reg->rspreg3 - i);
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cmd->response[i] = readl(offset) << 8;
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if (i != 3) {
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cmd->response[i] |=
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readb(offset - 1);
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}
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debug("cmd->resp[%d]: %08x\n",
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i, cmd->response[i]);
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}
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} else if (cmd->resp_type & MMC_RSP_BUSY) {
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for (i = 0; i < retry; i++) {
|
||||
/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
|
||||
if (readl(&host->reg->prnsts)
|
||||
& (1 << 20)) /* DAT[0] */
|
||||
break;
|
||||
}
|
||||
|
||||
if (i == retry) {
|
||||
printf("%s: card is still busy\n", __func__);
|
||||
return TIMEOUT;
|
||||
}
|
||||
|
||||
cmd->response[0] = readl(&host->reg->rspreg0);
|
||||
debug("cmd->resp[0]: %08x\n", cmd->response[0]);
|
||||
} else {
|
||||
cmd->response[0] = readl(&host->reg->rspreg0);
|
||||
debug("cmd->resp[0]: %08x\n", cmd->response[0]);
|
||||
}
|
||||
}
|
||||
|
||||
if (data) {
|
||||
while (1) {
|
||||
mask = readl(&host->reg->norintsts);
|
||||
|
||||
if (mask & (1 << 15)) {
|
||||
/* Error Interrupt */
|
||||
writel(mask, &host->reg->norintsts);
|
||||
printf("%s: error during transfer: 0x%08x\n",
|
||||
__func__, mask);
|
||||
return -1;
|
||||
} else if (mask & (1 << 3)) {
|
||||
/* DMA Interrupt */
|
||||
debug("DMA end\n");
|
||||
break;
|
||||
} else if (mask & (1 << 1)) {
|
||||
/* Transfer Complete */
|
||||
debug("r/w is done\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
writel(mask, &host->reg->norintsts);
|
||||
}
|
||||
|
||||
udelay(1000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mmc_change_clock(struct mmc_host *host, uint clock)
|
||||
{
|
||||
int div, hw_div;
|
||||
unsigned short clk;
|
||||
unsigned long timeout;
|
||||
unsigned int reg, hostbase;
|
||||
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
debug(" mmc_change_clock called\n");
|
||||
|
||||
/* Change Tegra2 SDMMCx clock divisor here */
|
||||
/* Source is 216MHz, PLLP_OUT0 */
|
||||
if (clock == 0)
|
||||
goto out;
|
||||
|
||||
div = 1;
|
||||
if (clock <= 400000) {
|
||||
hw_div = ((9-1)<<1); /* Best match is 375KHz */
|
||||
div = 64;
|
||||
} else if (clock <= 20000000)
|
||||
hw_div = ((11-1)<<1); /* Best match is 19.6MHz */
|
||||
else if (clock <= 26000000)
|
||||
hw_div = ((9-1)<<1); /* Use 24MHz */
|
||||
else
|
||||
hw_div = ((4-1)<<1) + 1; /* 4.5 divisor for 48MHz */
|
||||
|
||||
debug("mmc_change_clock: hw_div = %d, card clock div = %d\n",
|
||||
hw_div, div);
|
||||
|
||||
/* Change SDMMCx divisor */
|
||||
|
||||
hostbase = readl(&host->base);
|
||||
debug("mmc_change_clock: hostbase = %08X\n", hostbase);
|
||||
|
||||
if (hostbase == TEGRA2_SDMMC1_BASE) {
|
||||
reg = readl(&clkrst->crc_clk_src_sdmmc1);
|
||||
reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
|
||||
reg |= hw_div; /* n-1 */
|
||||
writel(reg, &clkrst->crc_clk_src_sdmmc1);
|
||||
} else if (hostbase == TEGRA2_SDMMC2_BASE) {
|
||||
reg = readl(&clkrst->crc_clk_src_sdmmc2);
|
||||
reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
|
||||
reg |= hw_div; /* n-1 */
|
||||
writel(reg, &clkrst->crc_clk_src_sdmmc2);
|
||||
} else if (hostbase == TEGRA2_SDMMC3_BASE) {
|
||||
reg = readl(&clkrst->crc_clk_src_sdmmc3);
|
||||
reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
|
||||
reg |= hw_div; /* n-1 */
|
||||
writel(reg, &clkrst->crc_clk_src_sdmmc3);
|
||||
} else {
|
||||
reg = readl(&clkrst->crc_clk_src_sdmmc4);
|
||||
reg &= 0xFFFFFF00; /* divisor (7.1) = 00 */
|
||||
reg |= hw_div; /* n-1 */
|
||||
writel(reg, &clkrst->crc_clk_src_sdmmc4);
|
||||
}
|
||||
|
||||
writew(0, &host->reg->clkcon);
|
||||
|
||||
div >>= 1;
|
||||
/*
|
||||
* CLKCON
|
||||
* SELFREQ[15:8] : base clock divided by value
|
||||
* ENSDCLK[2] : SD Clock Enable
|
||||
* STBLINTCLK[1] : Internal Clock Stable
|
||||
* ENINTCLK[0] : Internal Clock Enable
|
||||
*/
|
||||
clk = (div << 8) | (1 << 0);
|
||||
writew(clk, &host->reg->clkcon);
|
||||
|
||||
/* Wait max 10 ms */
|
||||
timeout = 10;
|
||||
while (!(readw(&host->reg->clkcon) & (1 << 1))) {
|
||||
if (timeout == 0) {
|
||||
printf("%s: timeout error\n", __func__);
|
||||
return;
|
||||
}
|
||||
timeout--;
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
clk |= (1 << 2);
|
||||
writew(clk, &host->reg->clkcon);
|
||||
|
||||
debug("mmc_change_clock: clkcon = %08X\n", clk);
|
||||
debug("mmc_change_clock: CLK_SOURCE_SDMMCx = %08X\n", reg);
|
||||
|
||||
out:
|
||||
host->clock = clock;
|
||||
}
|
||||
|
||||
static void mmc_set_ios(struct mmc *mmc)
|
||||
{
|
||||
struct mmc_host *host = mmc->priv;
|
||||
unsigned char ctrl;
|
||||
debug(" mmc_set_ios called\n");
|
||||
|
||||
debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
|
||||
|
||||
/* Change clock first */
|
||||
|
||||
mmc_change_clock(host, mmc->clock);
|
||||
|
||||
ctrl = readb(&host->reg->hostctl);
|
||||
|
||||
/*
|
||||
* WIDE8[5]
|
||||
* 0 = Depend on WIDE4
|
||||
* 1 = 8-bit mode
|
||||
* WIDE4[1]
|
||||
* 1 = 4-bit mode
|
||||
* 0 = 1-bit mode
|
||||
*/
|
||||
if (mmc->bus_width == 8)
|
||||
ctrl |= (1 << 5);
|
||||
else if (mmc->bus_width == 4)
|
||||
ctrl |= (1 << 1);
|
||||
else
|
||||
ctrl &= ~(1 << 1);
|
||||
|
||||
writeb(ctrl, &host->reg->hostctl);
|
||||
debug("mmc_set_ios: hostctl = %08X\n", ctrl);
|
||||
}
|
||||
|
||||
static void mmc_reset(struct mmc_host *host)
|
||||
{
|
||||
unsigned int timeout;
|
||||
debug(" mmc_reset called\n");
|
||||
|
||||
/*
|
||||
* RSTALL[0] : Software reset for all
|
||||
* 1 = reset
|
||||
* 0 = work
|
||||
*/
|
||||
writeb((1 << 0), &host->reg->swrst);
|
||||
|
||||
host->clock = 0;
|
||||
|
||||
/* Wait max 100 ms */
|
||||
timeout = 100;
|
||||
|
||||
/* hw clears the bit when it's done */
|
||||
while (readb(&host->reg->swrst) & (1 << 0)) {
|
||||
if (timeout == 0) {
|
||||
printf("%s: timeout error\n", __func__);
|
||||
return;
|
||||
}
|
||||
timeout--;
|
||||
udelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
static int mmc_core_init(struct mmc *mmc)
|
||||
{
|
||||
struct mmc_host *host = (struct mmc_host *)mmc->priv;
|
||||
unsigned int mask;
|
||||
debug(" mmc_core_init called\n");
|
||||
|
||||
mmc_reset(host);
|
||||
|
||||
host->version = readw(&host->reg->hcver);
|
||||
debug("host version = %x\n", host->version);
|
||||
|
||||
/* mask all */
|
||||
writel(0xffffffff, &host->reg->norintstsen);
|
||||
writel(0xffffffff, &host->reg->norintsigen);
|
||||
|
||||
writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
|
||||
/*
|
||||
* NORMAL Interrupt Status Enable Register init
|
||||
* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
|
||||
* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
|
||||
* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
|
||||
* [0] ENSTACMDCMPLT : Command Complete Status Enable
|
||||
*/
|
||||
mask = readl(&host->reg->norintstsen);
|
||||
mask &= ~(0xffff);
|
||||
mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
|
||||
writel(mask, &host->reg->norintstsen);
|
||||
|
||||
/*
|
||||
* NORMAL Interrupt Signal Enable Register init
|
||||
* [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
|
||||
*/
|
||||
mask = readl(&host->reg->norintsigen);
|
||||
mask &= ~(0xffff);
|
||||
mask |= (1 << 1);
|
||||
writel(mask, &host->reg->norintsigen);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra2_mmc_initialize(int dev_index, int bus_width)
|
||||
{
|
||||
struct mmc *mmc;
|
||||
|
||||
debug(" mmc_initialize called\n");
|
||||
|
||||
mmc = &mmc_dev[dev_index];
|
||||
|
||||
sprintf(mmc->name, "Tegra2 SD/MMC");
|
||||
mmc->priv = &mmc_host[dev_index];
|
||||
mmc->send_cmd = mmc_send_cmd;
|
||||
mmc->set_ios = mmc_set_ios;
|
||||
mmc->init = mmc_core_init;
|
||||
|
||||
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
|
||||
if (bus_width == 8)
|
||||
mmc->host_caps = MMC_MODE_8BIT;
|
||||
else
|
||||
mmc->host_caps = MMC_MODE_4BIT;
|
||||
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
||||
|
||||
/*
|
||||
* min freq is for card identification, and is the highest
|
||||
* low-speed SDIO card frequency (actually 400KHz)
|
||||
* max freq is highest HS eMMC clock as per the SD/MMC spec
|
||||
* (actually 52MHz)
|
||||
* Both of these are the closest equivalents w/216MHz source
|
||||
* clock and Tegra2 SDMMC divisors.
|
||||
*/
|
||||
mmc->f_min = 375000;
|
||||
mmc->f_max = 48000000;
|
||||
|
||||
mmc_host[dev_index].clock = 0;
|
||||
mmc_host[dev_index].reg = tegra2_get_base_mmc(dev_index);
|
||||
mmc_host[dev_index].base = (unsigned int)mmc_host[dev_index].reg;
|
||||
mmc_register(mmc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra2_mmc_init(int dev_index, int bus_width)
|
||||
{
|
||||
debug(" tegra2_mmc_init: index %d, bus width %d\n",
|
||||
dev_index, bus_width);
|
||||
return tegra2_mmc_initialize(dev_index, bus_width);
|
||||
}
|
||||
81
drivers/mmc/tegra2_mmc.h
Normal file
81
drivers/mmc/tegra2_mmc.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* (C) Copyright 2009 SAMSUNG Electronics
|
||||
* Minkyu Kang <mk7.kang@samsung.com>
|
||||
* Portions Copyright (C) 2011 NVIDIA Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __TEGRA2_MMC_H_
|
||||
#define __TEGRA2_MMC_H_
|
||||
|
||||
#define TEGRA2_SDMMC1_BASE 0xC8000000
|
||||
#define TEGRA2_SDMMC2_BASE 0xC8000200
|
||||
#define TEGRA2_SDMMC3_BASE 0xC8000400
|
||||
#define TEGRA2_SDMMC4_BASE 0xC8000600
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct tegra2_mmc {
|
||||
unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
|
||||
unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
|
||||
unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
|
||||
unsigned int argument; /* _ARGUMENT_0 */
|
||||
unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */
|
||||
unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */
|
||||
unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
|
||||
unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
|
||||
unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
|
||||
unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
|
||||
unsigned int bdata; /* _BUFFER_DATA_PORT_0 */
|
||||
unsigned int prnsts; /* _PRESENT_STATE_0 */
|
||||
unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */
|
||||
unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */
|
||||
unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */
|
||||
unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */
|
||||
unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */
|
||||
unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */
|
||||
unsigned char swrst; /* _SW_RESET_ 31:24 */
|
||||
unsigned int norintsts; /* _INTERRUPT_STATUS_0 */
|
||||
unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */
|
||||
unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */
|
||||
unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
|
||||
unsigned char res1[2]; /* _RESERVED 31:16 */
|
||||
unsigned int capareg; /* _CAPABILITIES_0 */
|
||||
unsigned char res2[4]; /* RESERVED, offset 44h-47h */
|
||||
unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */
|
||||
unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */
|
||||
unsigned short setacmd12err; /* offset 50h */
|
||||
unsigned short setinterr; /* offset 52h */
|
||||
unsigned char admaerr; /* offset 54h */
|
||||
unsigned char res4[3]; /* RESERVED, offset 55h-57h */
|
||||
unsigned long admaaddr; /* offset 58h-5Fh */
|
||||
unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
|
||||
unsigned short slotintstatus; /* offset FCh */
|
||||
unsigned short hcver; /* HOST Version */
|
||||
unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
|
||||
};
|
||||
|
||||
struct mmc_host {
|
||||
struct tegra2_mmc *reg;
|
||||
unsigned int version; /* SDHCI spec. version */
|
||||
unsigned int clock; /* Current clock (MHz) */
|
||||
unsigned int base; /* Base address, SDMMC1/2/3/4 */
|
||||
};
|
||||
|
||||
int tegra2_mmc_init(int dev_index, int bus_width);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __TEGRA2_MMC_H_ */
|
||||
Loading…
Reference in a new issue