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https://github.com/AsahiLinux/u-boot
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ARM: display5: Remove common.c file (after DM/DTS U-Boot proper conversion)
The common.c file content can be safely moved to spl.c file after performing the DM/DTS conversion for the U-Boot proper. It contains the non DM/DTS setup code, which now is only used by SPL. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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d5354f59d0
commit
21c7d34279
4 changed files with 76 additions and 90 deletions
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@ -5,7 +5,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-y = common.o spl.o
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obj-y = spl.o
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else
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obj-y := common.o display5.o
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obj-y := display5.o
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endif
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@ -1,83 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/arch/mx6-pins.h>
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#include "common.h"
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iomux_v3_cfg_t const uart_console_pads[] = {
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/* UART5 */
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MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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void displ5_set_iomux_uart_spl(void)
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{
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SETUP_IOMUX_PADS(uart_console_pads);
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}
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iomux_v3_cfg_t const misc_pads_spl[] = {
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/* Emergency recovery pin */
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MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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void displ5_set_iomux_misc_spl(void)
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{
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SETUP_IOMUX_PADS(misc_pads_spl);
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}
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#ifdef CONFIG_MXC_SPI
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iomux_v3_cfg_t const ecspi2_pads[] = {
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/* SPI2, NOR Flash nWP, CS0 */
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MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
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{
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if (bus != 1 || cs != 0)
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return -EINVAL;
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return IMX_GPIO_NR(5, 29);
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}
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void displ5_set_iomux_ecspi_spl(void)
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{
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SETUP_IOMUX_PADS(ecspi2_pads);
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}
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#else
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void displ5_set_iomux_ecspi_spl(void) {}
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#endif
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#ifdef CONFIG_FSL_ESDHC_IMX
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iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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void displ5_set_iomux_usdhc_spl(void)
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{
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SETUP_IOMUX_PADS(usdhc4_pads);
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}
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#else
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void displ5_set_iomux_usdhc_spl(void) {}
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#endif
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@ -31,9 +31,4 @@
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#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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void displ5_set_iomux_uart_spl(void);
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void displ5_set_iomux_ecspi_spl(void);
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void displ5_set_iomux_usdhc_spl(void);
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void displ5_set_iomux_misc_spl(void);
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#endif /* __DISPL5_COMMON_H_ */
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@ -104,6 +104,80 @@ static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
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.trasmin = 3500,
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};
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iomux_v3_cfg_t const uart_console_pads[] = {
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/* UART5 */
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MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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void displ5_set_iomux_uart_spl(void)
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{
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SETUP_IOMUX_PADS(uart_console_pads);
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}
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iomux_v3_cfg_t const misc_pads_spl[] = {
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/* Emergency recovery pin */
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MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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void displ5_set_iomux_misc_spl(void)
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{
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SETUP_IOMUX_PADS(misc_pads_spl);
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}
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#ifdef CONFIG_MXC_SPI
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iomux_v3_cfg_t const ecspi2_pads[] = {
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/* SPI2, NOR Flash nWP, CS0 */
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MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
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{
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if (bus != 1 || cs != 0)
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return -EINVAL;
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return IMX_GPIO_NR(5, 29);
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}
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void displ5_set_iomux_ecspi_spl(void)
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{
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SETUP_IOMUX_PADS(ecspi2_pads);
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}
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#else
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void displ5_set_iomux_ecspi_spl(void) {}
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#endif
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#ifdef CONFIG_FSL_ESDHC_IMX
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iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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void displ5_set_iomux_usdhc_spl(void)
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{
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SETUP_IOMUX_PADS(usdhc4_pads);
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}
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#else
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void displ5_set_iomux_usdhc_spl(void) {}
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#endif
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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