sh: Remove r7780mp board

This board has not been converted to CONFIG_DM by the deadline of v2020.01
and is missing other conversions which depend on this as well.  Remove it.

Patch-cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Patch-cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-02-10 12:51:22 -05:00
parent 5617351532
commit 215386e48c
13 changed files with 0 additions and 870 deletions

View file

@ -25,10 +25,6 @@ config TARGET_R2DPLUS
bool "Renesas R2D-PLUS"
select CPU_SH4
config TARGET_R7780MP
bool "R7780MP board"
select CPU_SH4A
config TARGET_SH7752EVB
bool "SH7752EVB"
select CPU_SH4A
@ -56,7 +52,6 @@ config SYS_CPU
source "arch/sh/lib/Kconfig"
source "board/renesas/r2dplus/Kconfig"
source "board/renesas/r7780mp/Kconfig"
source "board/renesas/sh7752evb/Kconfig"
source "board/renesas/sh7753evb/Kconfig"
source "board/renesas/sh7757lcr/Kconfig"

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@ -1,12 +0,0 @@
if TARGET_R7780MP
config SYS_BOARD
default "r7780mp"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "r7780mp"
endif

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@ -1,7 +0,0 @@
R7780MP BOARD
M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
S: Maintained
F: board/renesas/r7780mp/
F: include/configs/r7780mp.h
F: configs/r7780mp_defconfig

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@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
#
# board/r7780mp/Makefile
#
obj-y := r7780mp.o
extra-y += lowlevel_init.o

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@ -1,356 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu
*
* u-boot/board/r7780mp/lowlevel_init.S
*/
#include <config.h>
#include <asm/processor.h>
#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
.text
.align 2
lowlevel_init:
write32 CCR_A, CCR_D /* Address of Cache Control Register */
/* Instruction Cache Invalidate */
write32 FRQCR_A, FRQCR_D /* Frequency control register */
/* pin_multi_setting */
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
write32 BBG_PMSR1_A, BBG_PMSR1_D
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
write32 BBG_PMSR2_A, BBG_PMSR2_D
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
write32 BBG_PMSR3_A, BBG_PMSR3_D
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
write32 BBG_PMSR4_A, BBG_PMSR4_D
write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
write32 BBG_PMSRG_A, BBG_PMSRG_D
/* cpg_setting */
write32 FRQCR_A, FRQCR_D
write32 DLLCSR_A, DLLCSR_D
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
/* wait 200us */
mov.l REPEAT0_R3, r3
mov #0, r2
repeat0:
add #1, r2
cmp/hs r3, r2
bf repeat0
nop
/* bsc_setting */
write32 MMSELR_A, MMSELR_D
write32 BCR_A, BCR_D
write32 CS0BCR_A, CS0BCR_D
write32 CS1BCR_A, CS1BCR_D
write32 CS2BCR_A, CS2BCR_D
write32 CS4BCR_A, CS4BCR_D
write32 CS5BCR_A, CS5BCR_D
write32 CS6BCR_A, CS6BCR_D
write32 CS0WCR_A, CS0WCR_D
write32 CS1WCR_A, CS1WCR_D
write32 CS2WCR_A, CS2WCR_D
write32 CS4WCR_A, CS4WCR_D
write32 CS5WCR_A, CS5WCR_D
write32 CS6WCR_A, CS6WCR_D
write32 CS5PCR_A, CS5PCR_D
write32 CS6PCR_A, CS6PCR_D
/* ddr_setting */
/* wait 200us */
mov.l REPEAT0_R3, r3
mov #0, r2
repeat1:
add #1, r2
cmp/hs r3, r2
bf repeat1
nop
mov.l MIM_U_A, r0
mov.l MIM_U_D, r1
synco
mov.l r1, @r0
synco
mov.l MIM_L_A, r0
mov.l MIM_L_D0, r1
synco
mov.l r1, @r0
synco
mov.l STR_L_A, r0
mov.l STR_L_D, r1
synco
mov.l r1, @r0
synco
mov.l SDR_L_A, r0
mov.l SDR_L_D, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
nop
mov.l SCR_L_A, r0
mov.l SCR_L_D0, r1
synco
mov.l r1, @r0
synco
mov.l SCR_L_A, r0
mov.l SCR_L_D1, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l EMRS_A, r0
mov.l EMRS_D, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l MRS1_A, r0
mov.l MRS1_D, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A, r0
mov.l SCR_L_D2, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A, r0
mov.l SCR_L_D3, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A, r0
mov.l SCR_L_D4, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l MRS2_A, r0
mov.l MRS2_D, r1
synco
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A, r0
mov.l SCR_L_D5, r1
synco
mov.l r1, @r0
synco
/* wait 200us */
mov.l REPEAT0_R1, r3
mov #0, r2
repeat2:
add #1, r2
cmp/hs r3, r2
bf repeat2
synco
mov.l MIM_L_A, r0
mov.l MIM_L_D1, r1
synco
mov.l r1, @r0
synco
rts
nop
.align 4
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA507
RWTCNT_D: .word 0x5A00
.align 2
BBG_PMMR_A: .long 0xFF800010
BBG_PMSR1_A: .long 0xFF800014
BBG_PMSR2_A: .long 0xFF800018
BBG_PMSR3_A: .long 0xFF80001C
BBG_PMSR4_A: .long 0xFF800020
BBG_PMSRG_A: .long 0xFF800024
BBG_PMMR_D_PMSR1: .long 0xffffbffd
BBG_PMSR1_D: .long 0x00004002
BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
BBG_PMSR2_D: .long 0x03de5800
BBG_PMMR_D_PMSR3: .long 0xfffffff8
BBG_PMSR3_D: .long 0x00000007
BBG_PMMR_D_PMSR4: .long 0xdffdfff9
BBG_PMSR4_D: .long 0x20020006
BBG_PMMR_D_PMSRG: .long 0xffffffff
BBG_PMSRG_D: .long 0x00000000
FRQCR_A: .long FRQCR
DLLCSR_A: .long 0xffc40010
FRQCR_D: .long 0x40233035
DLLCSR_D: .long 0x00000000
/* for DDR-SDRAM */
MIM_U_A: .long MIM_1
MIM_L_A: .long MIM_2
SCR_U_A: .long SCR_1
SCR_L_A: .long SCR_2
STR_U_A: .long STR_1
STR_L_A: .long STR_2
SDR_U_A: .long SDR_1
SDR_L_A: .long SDR_2
EMRS_A: .long 0xFEC02000
MRS1_A: .long 0xFEC00B08
MRS2_A: .long 0xFEC00308
MIM_U_D: .long 0x00004000
MIM_L_D0: .long 0x03e80009
MIM_L_D1: .long 0x03e80209
SCR_L_D0: .long 0x3
SCR_L_D1: .long 0x2
SCR_L_D2: .long 0x2
SCR_L_D3: .long 0x4
SCR_L_D4: .long 0x4
SCR_L_D5: .long 0x0
STR_L_D: .long 0x000f0000
SDR_L_D: .long 0x00000400
EMRS_D: .long 0x0
MRS1_D: .long 0x0
MRS2_D: .long 0x0
/* Cache Controller */
CCR_A: .long CCR
MMUCR_A: .long MMUCR
RWTCNT_A: .long WTCNT
CCR_D: .long 0x0000090b
CCR_D_2: .long 0x00000103
MMUCR_D: .long 0x00000004
MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
/* local Bus State Controller */
MMSELR_A: .long MMSELR
BCR_A: .long BCR
CS0BCR_A: .long CS0BCR
CS1BCR_A: .long CS1BCR
CS2BCR_A: .long CS2BCR
CS4BCR_A: .long CS4BCR
CS5BCR_A: .long CS5BCR
CS6BCR_A: .long CS6BCR
CS0WCR_A: .long CS0WCR
CS1WCR_A: .long CS1WCR
CS2WCR_A: .long CS2WCR
CS4WCR_A: .long CS4WCR
CS5WCR_A: .long CS5WCR
CS6WCR_A: .long CS6WCR
CS5PCR_A: .long CS5PCR
CS6PCR_A: .long CS6PCR
MMSELR_D: .long 0xA5A50003
BCR_D: .long 0x00000000
CS0BCR_D: .long 0x77777770
CS1BCR_D: .long 0x77777670
CS2BCR_D: .long 0x77777770
CS4BCR_D: .long 0x77777770
CS5BCR_D: .long 0x77777670
CS6BCR_D: .long 0x77777770
CS0WCR_D: .long 0x00020006
CS1WCR_D: .long 0x00232304
CS2WCR_D: .long 0x7777770F
CS4WCR_D: .long 0x7777770F
CS5WCR_D: .long 0x00101006
CS6WCR_D: .long 0x77777703
CS5PCR_D: .long 0x77000000
CS6PCR_D: .long 0x77000000
REPEAT0_R3: .long 0x00002000
REPEAT0_R1: .long 0x0000200

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@ -1,64 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*/
#include <common.h>
#include <ide.h>
#include <init.h>
#include <net.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <netdev.h>
#include "r7780mp.h"
int checkboard(void)
{
#if defined(CONFIG_R7780MP)
puts("BOARD: Renesas Solutions R7780MP\n");
#else
puts("BOARD: Renesas Solutions R7780RP\n");
#endif
return 0;
}
int board_init(void)
{
/* SCIF Enable */
writew(0x0, PHCR);
return 0;
}
void led_set_state(unsigned short value)
{
}
void ide_set_reset(int idereset)
{
/* if reset = 1 IDE reset will be asserted */
if (idereset) {
writew(0x432, FPGA_CFCTL);
#if defined(CONFIG_R7780MP)
writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
#else
writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
#endif
writew(0x01, FPGA_CFCDINTCLR);
}
}
static struct pci_controller hose;
void pci_init_board(void)
{
pci_sh7780_init(&hose);
}
int board_eth_init(struct bd_info *bis)
{
/* return >= 0 if a chip is found, the board's AX88796L is n2k-based */
return ne2k_register() + pci_eth_init(bis);
}

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@ -1,40 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007 Nobuhiro Iwamatsu
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* u-boot/board/r7780mp/r7780mp.h
*/
#ifndef _BOARD_R7780MP_R7780MP_H_
#define _BOARD_R7780MP_R7780MP_H_
/* R7780MP's FPGA register map */
#define FPGA_BASE 0xa4000000
#define FPGA_IRLMSK (FPGA_BASE + 0x00)
#define FPGA_IRLMON (FPGA_BASE + 0x02)
#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
#define FPGA_PCIBD (FPGA_BASE + 0x0E)
#define FPGA_PCICD (FPGA_BASE + 0x10)
#define FPGA_EXTGIO (FPGA_BASE + 0x16)
#define FPGA_IVDRMON (FPGA_BASE + 0x18)
#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
#define FPGA_OBLED (FPGA_BASE + 0x1C)
#define FPGA_OBSW (FPGA_BASE + 0x1E)
#define FPGA_TPCTL (FPGA_BASE + 0x100)
#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
#define FPGA_TPCLR (FPGA_BASE + 0x104)
#define FPGA_TPXPOS (FPGA_BASE + 0x106)
#define FPGA_TPYPOS (FPGA_BASE + 0x108)
#define FPGA_DBSW (FPGA_BASE + 0x200)
#define FPGA_VERSION (FPGA_BASE + 0x700)
#define FPGA_CFCTL (FPGA_BASE + 0x300)
#define FPGA_CFPOW (FPGA_BASE + 0x302)
#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
#define FPGA_PMR (FPGA_BASE + 0x900)
#endif /* _BOARD_R7780RP_R7780RP_H_ */

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@ -1,40 +0,0 @@
CONFIG_SH=y
CONFIG_SYS_TEXT_BASE=0x0FFC0000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_TARGET_R7780MP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200"
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xA0040000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PCI=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y

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@ -26,10 +26,6 @@ Renesas SH7722
^^^^^^^^^^^^^^
This CPU has the SH4AL-DSP core.
Renesas SH7780
^^^^^^^^^^^^^^
This CPU has the SH4A core.
Supported Boards
----------------
@ -67,20 +63,6 @@ Support devices are:
- NOR Flash
- Marubun PCMCIA
Renesas R7780MP
^^^^^^^^^^^^^^^
Board specific code is in board/r7780mp
To use this board, type "make r7780mp_config".
Support devices are:
- SCIF
- DDR-SDRAM
- NOR Flash
- Compact Flash
- ASIX ethernet
- SH7780 PCI bridge
- RTL8110 ethernet
In SuperH, S-record and binary of made u-boot work on the memory.
When u-boot is written in the flash, it is necessary to change the
address by using 'objcopy'::

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@ -53,7 +53,6 @@ obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NATSEMI) += natsemi.o
obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
obj-$(CONFIG_NETCONSOLE) += netconsole.o
obj-$(CONFIG_NS8382X) += ns8382x.o
obj-$(CONFIG_PCH_GBE) += pch_gbe.o

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@ -1,144 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
#include <common.h>
#include <linux/delay.h>
#include "ax88796.h"
/*
* Set 1 bit data
*/
static void ax88796_bitset(u32 bit)
{
/* DATA1 */
if( bit )
EEDI_HIGH;
else
EEDI_LOW;
EECLK_LOW;
udelay(1000);
EECLK_HIGH;
udelay(1000);
EEDI_LOW;
}
/*
* Get 1 bit data
*/
static u8 ax88796_bitget(void)
{
u8 bit;
EECLK_LOW;
udelay(1000);
/* DATA */
bit = EEDO;
EECLK_HIGH;
udelay(1000);
return bit;
}
/*
* Send COMMAND to EEPROM
*/
static void ax88796_eep_cmd(u8 cmd)
{
ax88796_bitset(BIT_DUMMY);
switch(cmd){
case MAC_EEP_READ:
ax88796_bitset(1);
ax88796_bitset(1);
ax88796_bitset(0);
break;
case MAC_EEP_WRITE:
ax88796_bitset(1);
ax88796_bitset(0);
ax88796_bitset(1);
break;
case MAC_EEP_ERACE:
ax88796_bitset(1);
ax88796_bitset(1);
ax88796_bitset(1);
break;
case MAC_EEP_EWEN:
ax88796_bitset(1);
ax88796_bitset(0);
ax88796_bitset(0);
break;
case MAC_EEP_EWDS:
ax88796_bitset(1);
ax88796_bitset(0);
ax88796_bitset(0);
break;
default:
break;
}
}
static void ax88796_eep_setaddr(u16 addr)
{
int i ;
for( i = 7 ; i >= 0 ; i-- )
ax88796_bitset(addr & (1 << i));
}
/*
* Get data from EEPROM
*/
static u16 ax88796_eep_getdata(void)
{
ushort data = 0;
int i;
ax88796_bitget(); /* DUMMY */
for( i = 0 ; i < 16 ; i++ ){
data <<= 1;
data |= ax88796_bitget();
}
return data;
}
static void ax88796_mac_read(u8 *buff)
{
int i ;
u16 data;
u16 addr = 0;
for( i = 0 ; i < 3; i++ )
{
EECS_HIGH;
EEDI_LOW;
udelay(1000);
/* READ COMMAND */
ax88796_eep_cmd(MAC_EEP_READ);
/* ADDRESS */
ax88796_eep_setaddr(addr++);
/* GET DATA */
data = ax88796_eep_getdata();
*buff++ = (uchar)(data & 0xff);
*buff++ = (uchar)((data >> 8) & 0xff);
EECLK_LOW;
EEDI_LOW;
EECS_LOW;
}
}
int get_prom(u8* mac_addr, u8* base_addr)
{
u8 prom[32];
int i;
ax88796_mac_read(prom);
for (i = 0; i < 6; i++){
mac_addr[i] = prom[i];
}
return 1;
}

View file

@ -1,66 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* AX88796L(NE2000) support
*
* (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
#ifndef __DRIVERS_AX88796L_H__
#define __DRIVERS_AX88796L_H__
#define DP_DATA (0x10 << 1)
#define START_PG 0x40 /* First page of TX buffer */
#define START_PG2 0x48
#define STOP_PG 0x80 /* Last page +1 of RX ring */
#define TX_PAGES 12
#define RX_START (START_PG+TX_PAGES)
#define RX_END STOP_PG
#define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE
#define AX88796L_BYTE_ACCESS 0x00001000
#define AX88796L_OFFSET 0x00000400
#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \
AX88796L_BYTE_ACCESS + AX88796L_OFFSET
#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1)
#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1)
#define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR))
#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR))
#define EECS_HIGH (AX88796L_MEMR |= 0x10)
#define EECS_LOW (AX88796L_MEMR &= 0xef)
#define EECLK_HIGH (AX88796L_MEMR |= 0x80)
#define EECLK_LOW (AX88796L_MEMR &= 0x7f)
#define EEDI_HIGH (AX88796L_MEMR |= 0x20)
#define EEDI_LOW (AX88796L_MEMR &= 0xdf)
#define EEDO ((AX88796L_MEMR & 0x40)>>6)
#define PAGE0_SET (AX88796L_CR &= 0x3f)
#define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40)
#define BIT_DUMMY 0
#define MAC_EEP_READ 1
#define MAC_EEP_WRITE 2
#define MAC_EEP_ERACE 3
#define MAC_EEP_EWEN 4
#define MAC_EEP_EWDS 5
/* R7780MP Specific code */
#if defined(CONFIG_R7780MP)
#define ISA_OFFSET 0x1400
#define DP_IN(_b_, _o_, _d_) (_d_) = \
*( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET))
#define DP_OUT(_b_, _o_, _d_) \
*((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_)
#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET))
#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
#else
/* Please change for your target boards */
#define ISA_OFFSET 0x0000
#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET))
#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_)
#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET))
#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
#endif
#endif /* __DRIVERS_AX88796L_H__ */

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@ -1,108 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Renesas R7780MP board
*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*/
#ifndef __R7780RP_H
#define __R7780RP_H
#define CONFIG_CPU_SH7780 1
#define CONFIG_R7780MP 1
#define CONFIG_SYS_R7780MP_OLD_FLASH 1
#define __LITTLE_ENDIAN__ 1
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CONS_SCIF0 1
#define CONFIG_SYS_SDRAM_BASE (0x08000000)
#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
#define CONFIG_SYS_PBSIZE 256
/* Flash board support */
#define CONFIG_SYS_FLASH_BASE (0xA0000000)
#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
/* NOR Flash (S29PL127J60TFI130) */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
# define CONFIG_SYS_MAX_FLASH_BANKS (2)
# define CONFIG_SYS_MAX_FLASH_SECT 270
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
CONFIG_SYS_FLASH_BASE + 0x100000,\
CONFIG_SYS_FLASH_BASE + 0x400000,\
CONFIG_SYS_FLASH_BASE + 0x700000, }
#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
/* NOR Flash (Spantion S29GL256P) */
# define CONFIG_SYS_MAX_FLASH_BANKS (1)
# define CONFIG_SYS_MAX_FLASH_SECT 256
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_SYS_RX_ETH_BUFFER (8)
#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
#undef CONFIG_SYS_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
/* PCI Controller */
#if defined(CONFIG_CMD_PCI)
#define CONFIG_SH4_PCI
#define CONFIG_SH7780_PCI
#define CONFIG_SH7780_PCI_LSR 0x07f00001
#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
#define CONFIG_PCI_SCAN_SHOW 1
#define __mem_pci
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
#endif /* CONFIG_CMD_PCI */
#if defined(CONFIG_CMD_NET)
/* AX88796L Support(NE2000 base chip) */
#define CONFIG_DRIVER_AX88796L
#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
#endif
/* Compact flash Support */
#if defined(CONFIG_IDE)
#define CONFIG_IDE_RESET 1
#define CONFIG_SYS_PIO_MODE 1
#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 1
#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
#define CONFIG_IDE_SWAP_IO
#endif /* CONFIG_IDE */
#endif /* __R7780RP_H */