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https://github.com/AsahiLinux/u-boot
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STiH410: Add STi serial driver
This patch adds support to ASC (asynchronous serial controller) driver, which is basically a standard serial driver. This IP is common across other STMicroelectronics SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Patrice Chotard
Tom Rini
parent
413788cef5
commit
214a17e61d
4 changed files with 222 additions and 0 deletions
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@ -1096,6 +1096,8 @@ config STM32
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config ARCH_STI
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bool "Support STMicrolectronics SoCs"
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select CPU_V7
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select DM
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select DM_SERIAL
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help
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Support for STMicroelectronics STiH407/10 SoC family.
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This SoC is used on Linaro 96Board STiH410-B2260
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@ -413,4 +413,12 @@ config PXA_SERIAL
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If you have a machine based on a Marvell XScale PXA2xx CPU you
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can enable its onboard serial ports by enabling this option.
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config STI_ASC_SERIAL
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bool "STMicroelectronics on-chip UART"
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depends on DM_SERIAL && ARCH_STI
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help
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Select this to enable Asynchronous Serial Controller available
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on STiH410 SoC. This is a basic implementation, it supports
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following baudrate 9600, 19200, 38400, 57600 and 115200.
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endmenu
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@ -41,6 +41,7 @@ obj-$(CONFIG_FSL_LINFLEXUART) += serial_linflexuart.o
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obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
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obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
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obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
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obj-$(CONFIG_STI_ASC_SERIAL) += serial_sti_asc.o
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obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
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obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
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obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
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211
drivers/serial/serial_sti_asc.c
Normal file
211
drivers/serial/serial_sti_asc.c
Normal file
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@ -0,0 +1,211 @@
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/*
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* Support for Serial I/O using STMicroelectronics' on-chip ASC.
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*
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* Copyright (c) 2017
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* Patrice Chotard <patrice.chotard@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <serial.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define BAUDMODE 0x00001000
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#define RXENABLE 0x00000100
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#define RUN 0x00000080
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#define MODE 0x00000001
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#define MODE_8BIT 0x0001
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#define STOP_1BIT 0x0008
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#define PARITYODD 0x0020
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#define STA_TF BIT(9)
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#define STA_RBF BIT(0)
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struct sti_asc_uart {
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u32 baudrate;
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u32 txbuf;
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u32 rxbuf;
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u32 control;
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u32 inten;
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u32 status;
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u32 guardtime;
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u32 timeout;
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u32 txreset;
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u32 rxreset;
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};
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struct sti_asc_serial {
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/* address of registers in physical memory */
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struct sti_asc_uart *regs;
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};
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/* Values for the BAUDRATE Register */
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#define PCLK (200ul * 1000000ul)
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#define BAUDRATE_VAL_M0(bps) (PCLK / (16 * (bps)))
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#define BAUDRATE_VAL_M1(bps) ((bps * (1 << 14)) + (1<<13)) / (PCLK/(1 << 6))
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/*
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* MODE 0
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* ICCLK
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* ASCBaudRate = ----------------
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* baudrate * 16
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*
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* MODE 1
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* baudrate * 16 * 2^16
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* ASCBaudRate = ------------------------
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* ICCLK
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*
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* NOTE:
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* Mode 1 should be used for baudrates of 19200, and above, as it
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* has a lower deviation error than Mode 0 for higher frequencies.
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* Mode 0 should be used for all baudrates below 19200.
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*/
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static int sti_asc_pending(struct udevice *dev, bool input)
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{
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struct sti_asc_serial *priv = dev_get_priv(dev);
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struct sti_asc_uart *const uart = priv->regs;
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unsigned long status;
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status = readl(&uart->status);
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if (input)
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return status & STA_RBF;
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else
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return status & STA_TF;
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}
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static int _sti_asc_serial_setbrg(struct sti_asc_uart *uart, int baudrate)
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{
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unsigned long val;
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int t, mode = 1;
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switch (baudrate) {
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case 9600:
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t = BAUDRATE_VAL_M0(9600);
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mode = 0;
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break;
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case 19200:
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t = BAUDRATE_VAL_M1(19200);
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break;
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case 38400:
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t = BAUDRATE_VAL_M1(38400);
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break;
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case 57600:
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t = BAUDRATE_VAL_M1(57600);
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break;
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default:
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debug("ASC: unsupported baud rate: %d, using 115200 instead.\n",
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baudrate);
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case 115200:
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t = BAUDRATE_VAL_M1(115200);
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break;
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}
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/* disable the baudrate generator */
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val = readl(&uart->control);
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writel(val & ~RUN, &uart->control);
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/* set baud generator reload value */
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writel(t, &uart->baudrate);
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/* reset the RX & TX buffers */
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writel(1, &uart->txreset);
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writel(1, &uart->rxreset);
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/* set baud generator mode */
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if (mode)
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val |= BAUDMODE;
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/* finally, write value and enable ASC */
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writel(val, &uart->control);
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return 0;
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}
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/* called to adjust baud-rate */
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static int sti_asc_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct sti_asc_serial *priv = dev_get_priv(dev);
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struct sti_asc_uart *const uart = priv->regs;
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return _sti_asc_serial_setbrg(uart, baudrate);
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}
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/* blocking function, that returns next char */
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static int sti_asc_serial_getc(struct udevice *dev)
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{
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struct sti_asc_serial *priv = dev_get_priv(dev);
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struct sti_asc_uart *const uart = priv->regs;
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/* polling wait: for a char to be read */
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if (!sti_asc_pending(dev, true))
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return -EAGAIN;
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return readl(&uart->rxbuf);
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}
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/* write write out a single char */
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static int sti_asc_serial_putc(struct udevice *dev, const char c)
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{
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struct sti_asc_serial *priv = dev_get_priv(dev);
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struct sti_asc_uart *const uart = priv->regs;
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/* wait till safe to write next char */
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if (sti_asc_pending(dev, false))
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return -EAGAIN;
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/* finally, write next char */
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writel(c, &uart->txbuf);
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return 0;
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}
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/* initialize the ASC */
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static int sti_asc_serial_probe(struct udevice *dev)
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{
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struct sti_asc_serial *priv = dev_get_priv(dev);
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unsigned long val;
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fdt_addr_t base;
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base = dev_get_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = (struct sti_asc_uart *)base;
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sti_asc_serial_setbrg(dev, gd->baudrate);
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/*
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* build up the value to be written to CONTROL
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* set character length, bit stop number, odd parity
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*/
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val = RXENABLE | RUN | MODE_8BIT | STOP_1BIT | PARITYODD;
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writel(val, &priv->regs->control);
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return 0;
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}
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static const struct dm_serial_ops sti_asc_serial_ops = {
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.putc = sti_asc_serial_putc,
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.pending = sti_asc_pending,
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.getc = sti_asc_serial_getc,
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.setbrg = sti_asc_serial_setbrg,
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};
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static const struct udevice_id sti_serial_of_match[] = {
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{ .compatible = "st,asc" },
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{ }
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};
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U_BOOT_DRIVER(serial_sti_asc) = {
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.name = "serial_sti_asc",
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.id = UCLASS_SERIAL,
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.of_match = sti_serial_of_match,
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.ops = &sti_asc_serial_ops,
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.probe = sti_asc_serial_probe,
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.priv_auto_alloc_size = sizeof(struct sti_asc_serial),
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.flags = DM_FLAG_PRE_RELOC,
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};
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