mirror of
https://github.com/AsahiLinux/u-boot
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ppc4xx: Beautify configuration files for Sequoia and Korat boards
Signed-off-by: Larry Johnson <lrj@acm.org>
This commit is contained in:
Larry Johnson
Stefan Roese
parent
5db6138565
commit
214398d9cb
2 changed files with 237 additions and 235 deletions
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@ -25,73 +25,73 @@
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* MA 02111-1307 USA
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*/
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/************************************************************************
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/*
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* korat.h - configuration for Korat board
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***********************************************************************/
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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/*
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_440EPX 1 /* Specific PPC440EPx */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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*/
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#define CONFIG_440EPX 1 /* Specific PPC440EPx */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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/*-----------------------------------------------------------------------
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/*
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* Manufacturer's information serial EEPROM parameters
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*----------------------------------------------------------------------*/
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#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
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*/
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#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
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#define MAN_SERIAL_NO_FIELD 2
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#define MAN_SERIAL_NO_LENGTH 13
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#define MAN_MAC_ADDR_FIELD 3
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#define MAN_MAC_ADDR_LENGTH 17
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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/*
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* Base addresses -- Note these are effective addresses where the actual
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* resources get mapped (not physical addresses).
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*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
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#define CFG_BOOT_BASE_ADDR 0xf0000000
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_OCM_BASE 0xe0010000 /* ocm */
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#define CFG_OCM_BASE 0xe0010000 /* ocm */
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#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
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#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
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#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
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#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
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/* Don't change either of these */
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#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
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#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
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#define CFG_USB2D0_BASE 0xe0000100
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#define CFG_USB_DEVICE 0xe0000000
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#define CFG_USB_HOST 0xe0000400
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#define CFG_CPLD_BASE 0xc0000000
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/*-----------------------------------------------------------------------
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/*
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* Initial RAM & stack pointer
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*----------------------------------------------------------------------*/
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*/
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/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
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#undef CFG_INIT_RAM_DCACHE
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#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
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#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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/*-----------------------------------------------------------------------
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/*
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
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*/
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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/* define this if you want console on UART1 */
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@ -100,57 +100,57 @@
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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/*
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* Environment
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*----------------------------------------------------------------------*/
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
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*/
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
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/*-----------------------------------------------------------------------
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/*
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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/*
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
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#define CONFIG_DDR_ECC /* Use ECC when available */
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*/
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#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
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#define CONFIG_DDR_ECC /* Use ECC when available */
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#define SPD_EEPROM_ADDRESS {0x50}
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#define CONFIG_PROG_SDRAM_TLB
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#define CFG_DRAM_TEST
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/*-----------------------------------------------------------------------
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/*
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_MULTI_EEPROMS
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@ -164,8 +164,8 @@
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#define CFG_I2C_RTC_ADDR 0x68
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/* I2C SYSMON (LM73) */
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#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
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#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
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#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
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#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
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#define CFG_DTT_MAX_TEMP 70
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#define CFG_DTT_MIN_TEMP -30
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@ -206,24 +206,24 @@
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
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#define CONFIG_PHY_DYNAMIC_ANEG 1
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_HAS_ETH0
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
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/* buffers & descriptors */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 3
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/* USB */
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@ -273,80 +273,81 @@
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#define CONFIG_CMD_USB
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/* POST support */
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#define CONFIG_POST (CFG_POST_CACHE | \
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#define CONFIG_POST (CFG_POST_CACHE | \
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CFG_POST_CPU | \
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CFG_POST_ECC | \
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CFG_POST_ECC | \
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CFG_POST_ETHER | \
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CFG_POST_FPU | \
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CFG_POST_I2C | \
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CFG_POST_MEMORY | \
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CFG_POST_RTC | \
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CFG_POST_SPR | \
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CFG_POST_RTC | \
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CFG_POST_SPR | \
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CFG_POST_UART)
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CONFIG_LOGBUFFER
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#define CFG_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
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#define CFG_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
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#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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#define CONFIG_SUPPORT_VFAT
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/*-----------------------------------------------------------------------
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/*
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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/* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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/*
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* PCI stuff
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*----------------------------------------------------------------------*/
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
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/* CFG_PCI_MEMBASE */
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT
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#define CFG_PCI_MASTER_INIT
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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* For booting Linux, the board info and command line data have to be in the
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* first 8 MB of memory, since this is the maximum mapped by the Linux kernel
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* during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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/*
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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*/
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x04017300
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@ -360,7 +361,7 @@
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#define CFG_EBC_PB2AP 0x04017300
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#define CFG_EBC_PB2CR (CFG_CPLD_BASE | 0x00038000)
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/*-----------------------------------------------------------------------
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/*
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* GPIO Setup
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*
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* Korat GPIO usage:
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@ -423,7 +424,7 @@
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* . . . . .
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* . . . . .
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* GPIO63 xxxx x x (reserved for trace port)
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*----------------------------------------------------------------------*/
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*/
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#define CFG_GPIO_ATMEGA_SS_ 13
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#define CFG_GPIO_PHY0_FIBER_SEL 27
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@ -435,7 +436,7 @@
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#define CFG_GPIO_PHY0_EN 45
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#define CFG_GPIO_PHY1_EN 46
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/*-----------------------------------------------------------------------
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/*
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* PPC440 GPIO Configuration
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*/
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#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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@ -516,11 +517,12 @@
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -22,23 +22,23 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
/*
|
||||
* sequoia.h - configuration for Sequoia & Rainier boards
|
||||
***********************************************************************/
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
|
||||
#ifndef CONFIG_RAINIER
|
||||
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
|
||||
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
|
||||
#else
|
||||
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
|
||||
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
|
||||
#endif
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
/* Detect Sequoia PLL input clock automatically via CPLD bit */
|
||||
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
|
||||
33333333 : 33000000)
|
||||
|
|
@ -48,28 +48,28 @@
|
|||
* 44x dcache supported is working now on sequoia, but we don't enable
|
||||
* it yet since it needs further testing
|
||||
*/
|
||||
#define CONFIG_4xx_DCACHE /* enable dcache */
|
||||
#define CONFIG_4xx_DCACHE /* enable dcache */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the actual
|
||||
* resources get mapped (not physical addresses).
|
||||
*/
|
||||
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
|
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
|
||||
|
||||
#define CFG_TLB_FOR_BOOT_FLASH 0x0003
|
||||
#define CFG_BOOT_BASE_ADDR 0xf0000000
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
|
||||
#define CFG_OCM_BASE 0xe0010000 /* ocm */
|
||||
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
|
||||
#define CFG_OCM_BASE 0xe0010000 /* ocm */
|
||||
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
|
||||
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
|
||||
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
|
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
|
||||
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
|
||||
|
|
@ -83,62 +83,62 @@
|
|||
#define CFG_USB_HOST 0xe0000400
|
||||
#define CFG_BCSR_BASE 0xc0000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Initial RAM & stack pointer
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
|
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
|
||||
#define CFG_INIT_RAM_END (4 << 10)
|
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
/* define this if you want console on UART1 */
|
||||
#undef CONFIG_UART1_CONSOLE
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
|
||||
#else
|
||||
#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
|
||||
#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
|
||||
#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environ vars */
|
||||
#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
*/
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
|
|
@ -163,27 +163,28 @@
|
|||
* set up. While still running from cache, I experienced problems accessing
|
||||
* the NAND controller. sr - 2006-08-25
|
||||
*/
|
||||
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
|
||||
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
|
||||
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
|
||||
#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
|
||||
#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
|
||||
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
|
||||
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
|
||||
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
|
||||
#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
|
||||
#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */
|
||||
/* this addr */
|
||||
#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
|
||||
|
||||
/*
|
||||
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
|
||||
*/
|
||||
#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
|
||||
#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
|
||||
#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
|
||||
#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
|
||||
|
||||
/*
|
||||
* Now the NAND chip has to be defined (no autodetection used!)
|
||||
*/
|
||||
#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
|
||||
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
|
||||
#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
|
||||
#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
|
||||
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
|
||||
#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
|
||||
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
|
||||
#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
|
||||
#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
|
||||
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
|
||||
|
||||
#define CFG_NAND_ECCSIZE 256
|
||||
#define CFG_NAND_ECCBYTES 3
|
||||
|
|
@ -202,20 +203,20 @@
|
|||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MBYTES_SDRAM (256) /* 256MB */
|
||||
*/
|
||||
#define CFG_MBYTES_SDRAM (256) /* 256MB */
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
|
||||
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
#define CFG_I2C_MULTI_EEPROMS
|
||||
|
|
@ -226,9 +227,9 @@
|
|||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CFG_DTT_MAX_TEMP 70
|
||||
#define CFG_DTT_LOW_TEMP -30
|
||||
#define CFG_DTT_HYSTERESIS 3
|
||||
|
|
@ -290,12 +291,12 @@
|
|||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
|
||||
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
|
||||
|
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
|
||||
/* buffers & descriptors */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
|
||||
#define CONFIG_PHY1_ADDR 1
|
||||
|
|
@ -322,7 +323,6 @@
|
|||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
|
|
@ -332,7 +332,6 @@
|
|||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
|
|
@ -367,26 +366,26 @@
|
|||
#endif
|
||||
|
||||
/* POST support */
|
||||
#define CONFIG_POST (CFG_POST_MEMORY | \
|
||||
#define CONFIG_POST (CFG_POST_CACHE | \
|
||||
CFG_POST_CPU | \
|
||||
CFG_POST_UART | \
|
||||
CFG_POST_I2C | \
|
||||
CFG_POST_CACHE | \
|
||||
CFG_POST_FPU_ON | \
|
||||
CFG_POST_ETHER | \
|
||||
CFG_POST_SPR)
|
||||
CFG_POST_FPU_ON | \
|
||||
CFG_POST_I2C | \
|
||||
CFG_POST_MEMORY | \
|
||||
CFG_POST_SPR | \
|
||||
CFG_POST_UART)
|
||||
|
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
|
||||
#define CONFIG_LOGBUFFER
|
||||
#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
|
||||
#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
|
||||
|
||||
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
|
||||
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
|
||||
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
|
|
@ -394,7 +393,8 @@
|
|||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
|
|
@ -402,26 +402,26 @@
|
|||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* PCI stuff
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
|
||||
/* CFG_PCI_MEMBASE */
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_TARGET_INIT
|
||||
#define CFG_PCI_MASTER_INIT
|
||||
|
|
@ -430,54 +430,54 @@
|
|||
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
* For booting Linux, the board info and command line data have to be in the
|
||||
* first 8 MB of memory, since this is the maximum mapped by the Linux kernel
|
||||
* during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
|
||||
/*
|
||||
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
|
||||
*/
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
|
||||
/* Memory Bank 0 (NOR-FLASH) initialization */
|
||||
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
|
||||
/* Memory Bank 0 (NOR-FLASH) initialization */
|
||||
#define CFG_EBC_PB0AP 0x03017200
|
||||
#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
|
||||
|
||||
/* Memory Bank 3 (NAND-FLASH) initialization */
|
||||
/* Memory Bank 3 (NAND-FLASH) initialization */
|
||||
#define CFG_EBC_PB3AP 0x018003c0
|
||||
#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
|
||||
#else
|
||||
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
|
||||
/* Memory Bank 3 (NOR-FLASH) initialization */
|
||||
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
|
||||
/* Memory Bank 3 (NOR-FLASH) initialization */
|
||||
#define CFG_EBC_PB3AP 0x03017200
|
||||
#define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000)
|
||||
|
||||
/* Memory Bank 0 (NAND-FLASH) initialization */
|
||||
/* Memory Bank 0 (NAND-FLASH) initialization */
|
||||
#define CFG_EBC_PB0AP 0x018003c0
|
||||
#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
|
||||
#endif
|
||||
|
||||
/* Memory Bank 2 (CPLD) initialization */
|
||||
/* Memory Bank 2 (CPLD) initialization */
|
||||
#define CFG_EBC_PB2AP 0x24814580
|
||||
#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000)
|
||||
|
||||
#define CFG_BCSR5_PCI66EN 0x80
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* NAND FLASH
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CFG_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
|
||||
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
|
||||
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* PPC440 GPIO Configuration
|
||||
*/
|
||||
/* test-only: take GPIO init from pcs440ep ???? in config file */
|
||||
|
|
@ -559,16 +559,16 @@
|
|||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue