Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-26 22:52:18 +00:00
Code Issues Projects Releases Packages Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot

Browse source
This commit is contained in:
Stefano Babic 2015-06-15 12:08:11 +02:00
commit 212b660161
120 changed files with 550 additions and 2389 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/Kconfig
View file

@ -668,6 +668,7 @@ config TEGRA
select SUPPORT_SPL
select SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
select CPU_V7
select DM
select DM_SPI_FLASH
@ -794,6 +795,7 @@ config ARCH_UNIPHIER
select DM
select DM_SERIAL
select DM_I2C
select SPL_DISABLE_OF_CONTROL
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)

47
arch/arm/cpu/armv7/cpu.c
View file

@ -24,7 +24,7 @@
void __weak cpu_cache_initialization(void){}
int cleanup_before_linux(void)
int cleanup_before_linux_select(int flags)
{
/*
* this function is called just before we call linux
@ -42,24 +42,30 @@ int cleanup_before_linux(void)
icache_disable();
invalidate_icache_all();
/*
* turn off D-cache
* dcache_disable() in turn flushes the d-cache and disables MMU
*/
dcache_disable();
v7_outer_cache_disable();
if (flags & CBL_DISABLE_CACHES) {
/*
* turn off D-cache
* dcache_disable() in turn flushes the d-cache and disables MMU
*/
dcache_disable();
v7_outer_cache_disable();
/*
* After D-cache is flushed and before it is disabled there may
* be some new valid entries brought into the cache. We are sure
* that these lines are not dirty and will not affect our execution.
* (because unwinding the call-stack and setting a bit in CP15 SCTLR
* is all we did during this. We have not pushed anything on to the
* stack. Neither have we affected any static data)
* So just invalidate the entire d-cache again to avoid coherency
* problems for kernel
*/
invalidate_dcache_all();
/*
* After D-cache is flushed and before it is disabled there may
* be some new valid entries brought into the cache. We are
* sure that these lines are not dirty and will not affect our
* execution. (because unwinding the call-stack and setting a
* bit in CP15 SCTRL is all we did during this. We have not
* pushed anything on to the stack. Neither have we affected
* any static data) So just invalidate the entire d-cache again
* to avoid coherency problems for kernel
*/
invalidate_dcache_all();
} else {
flush_dcache_all();
invalidate_icache_all();
icache_enable();
}
/*
* Some CPU need more cache attention before starting the kernel.
@ -68,3 +74,8 @@ int cleanup_before_linux(void)
return 0;
}
int cleanup_before_linux(void)
{
return cleanup_before_linux_select(CBL_ALL);
}

8
arch/arm/cpu/armv7/exynos/Kconfig
View file

@ -8,6 +8,7 @@ config TARGET_SMDKV310
select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
config TARGET_TRATS
bool "Exynos4210 Trats board"
@ -28,6 +29,7 @@ config TARGET_ODROID
config TARGET_ODROID_XU3
bool "Exynos5422 Odroid board"
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
@ -35,31 +37,37 @@ config TARGET_ARNDALE
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
config TARGET_SMDK5250
bool "SMDK5250 board"
select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
config TARGET_SNOW
bool "Snow board"
select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
config TARGET_SMDK5420
bool "SMDK5420 board"
select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
config TARGET_PEACH_PI
bool "Peach Pi board"
select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
config TARGET_PEACH_PIT
bool "Peach Pit board"
select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
endchoice

2
arch/arm/cpu/armv7/s5pc1xx/Kconfig
View file

@ -7,10 +7,12 @@ choice
config TARGET_S5P_GONI
bool "S5P Goni board"
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
config TARGET_SMDKC100
bool "Support smdkc100 board"
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
endchoice

1
arch/arm/cpu/armv7/sunxi/board.c
View file

@ -223,6 +223,7 @@ int cpu_eth_init(bd_t *bis)
__maybe_unused int rc;
#ifdef CONFIG_MACPWR
gpio_request(CONFIG_MACPWR, "macpwr");
gpio_direction_output(CONFIG_MACPWR, 1);
mdelay(200);
#endif

3
arch/arm/dts/Makefile
View file

@ -138,7 +138,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
# Add any required device tree compiler flags here
DTC_FLAGS +=
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))

80
arch/arm/dts/exynos4412-odroid.dts
View file

@ -43,140 +43,102 @@
voltage-regulators {
ldo1_reg: ldo1 {
regulator-compatible = "LDO1";
regulator-name = "VDD_ALIVE_1.0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
ldo2_reg: ldo2 {
regulator-compatible = "LDO2";
regulator-name = "VDDQ_VM1M2_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo3_reg: ldo3 {
regulator-compatible = "LDO3";
regulator-name = "VCC_1.8V_AP";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo4_reg: ldo4 {
regulator-compatible = "LDO4";
regulator-name = "VDDQ_MMC2_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo5_reg: ldo5 {
regulator-compatible = "LDO5";
regulator-name = "VDDQ_MMC0/1/3_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo6_reg: ldo6 {
regulator-compatible = "LDO6";
regulator-name = "VMPLL_1.0V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
ldo7_reg: ldo7 {
regulator-compatible = "LDO7";
regulator-name = "VPLL_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
ldo8_reg: ldo8 {
regulator-compatible = "LDO8";
regulator-name = "VDD_MIPI/HDMI_1.0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
ldo9_reg: ldo9 {
regulator-compatible = "LDO9";
regulator-name = "nc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo10_reg: ldo10 {
regulator-compatible = "LDO10";
regulator-name = "VDD_MIPI/HDMI_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo11_reg: ldo11 {
regulator-compatible = "LDO11";
regulator-name = "VDD_ABB1_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo12_reg: ldo12 {
regulator-compatible = "LDO12";
regulator-name = "VDD_UOTG_3.0V";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
ldo13_reg: ldo13 {
regulator-compatible = "LDO13";
regulator-name = "VDD_C2C_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo14_reg: ldo14 {
regulator-compatible = "LDO14";
regulator-name = "VDD_ABB02_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo15_reg: ldo15 {
regulator-compatible = "LDO15";
regulator-name = "VDD_HSIC/OTG_1.0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
ldo16_reg: ldo16 {
regulator-compatible = "LDO16";
regulator-name = "VDD_HSIC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo17_reg: ldo17 {
regulator-compatible = "LDO17";
regulator-name = "VDDQ_CAM_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo18_reg: ldo18 {
regulator-compatible = "LDO18";
regulator-name = "nc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo19_reg: ldo19 {
regulator-compatible = "LDO19";
regulator-name = "nc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo20_reg: ldo20 {
regulator-compatible = "LDO20";
regulator-name = "VDDQ_EMMC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -185,7 +147,6 @@
};
ldo21_reg: ldo21 {
regulator-compatible = "LDO21";
regulator-name = "TFLASH_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -194,7 +155,6 @@
};
ldo22_reg: ldo22 {
regulator-compatible = "LDO22";
regulator-name = "VDDQ_EMMC_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -202,20 +162,6 @@
regulator-boot-on;
};
ldo23_reg: ldo23 {
regulator-compatible = "LDO23";
regulator-name = "nc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo24_reg: ldo24 {
regulator-compatible = "LDO24";
regulator-name = "nc";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
ldo25_reg: ldo25 {
regulator-compatible = "LDO25";
regulator-name = "VDDQ_LCD_3.0V";
@ -223,75 +169,53 @@
regulator-max-microvolt = <3000000>;
};
ldo26_reg: ldo26 {
regulator-compatible = "LDO26";
regulator-name = "nc";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
buck1_reg: buck@1 {
regulator-compatible = "BUCK1";
buck1_reg: buck1 {
regulator-name = "VDD_MIF_1.0V";
regulator-min-microvolt = <8500000>;
regulator-max-microvolt = <1100000>;
};
buck2_reg: buck@2 {
regulator-compatible = "BUCK2";
buck2_reg: buck2 {
regulator-name = "VDD_ARM_1.0V";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1500000>;
};
buck3_reg: buck3 {
regulator-compatible = "BUCK3";
regulator-name = "VDD_INT_1.1V";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1150000>;
};
buck4_reg: buck4 {
regulator-compatible = "BUCK4";
regulator-name = "VDD_G3D_1.0V";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1150000>;
};
buck5_reg: buck5 {
regulator-compatible = "BUCK5";
regulator-name = "VDDQ_AP_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
buck6_reg: buck6 {
regulator-compatible = "BUCK6";
regulator-name = "VCC_INL1/7_1.35V";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
};
buck7_reg: buck7 {
regulator-compatible = "BUCK7";
regulator-name = "VCC_INL2/3/5_2.0V";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
};
buck8_reg: buck8 {
regulator-compatible = "BUCK8";
regulator-name = "VCC_P3V3_2.85V";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
};
buck9_reg: buck9 {
regulator-compatible = "BUCK9";
regulator-name = "nc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
};
};
};

3
arch/arm/dts/tegra124-nyan-big.dts
View file

@ -163,12 +163,15 @@
spi@7000d400 {
status = "okay";
spi-deactivate-delay = <200>;
spi-max-frequency = <3000000>;
cros_ec: cros-ec@0 {
compatible = "google,cros-ec-spi";
spi-max-frequency = <3000000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
reg = <0>;
google,cros-ec-spi-msg-delay = <2000>;

8
arch/arm/include/asm/arch-tegra/clock.h
View file

@ -336,4 +336,12 @@ void arch_timer_init(void);
void tegra30_set_up_pllp(void);
/**
* Enable output clock for external peripherals
*
* @param clk_id Clock ID to output (1, 2 or 3)
* @return 0 if OK. -ve on error
*/
int clock_external_output(int clk_id);
#endif /* _TEGRA_CLOCK_H_ */

7
arch/arm/include/asm/arch-tegra/sys_proto.h
View file

@ -25,4 +25,11 @@ int tegra_board_id(void);
*/
int tegra_lcd_pmic_init(int board_id);
/**
* nvidia_board_init() - perform any board-specific init
*
* @return 0 if OK, -ve on error
*/
int nvidia_board_init(void);
#endif

12
arch/arm/include/asm/arch-tegra124/clock-tables.h
View file

@ -285,12 +285,12 @@ enum periph_id {
/* 184 */
PERIPH_ID_GPU,
PERIPH_ID_AMX1,
PERIPH_ID_X_RESERVED26,
PERIPH_ID_X_RESERVED27,
PERIPH_ID_X_RESERVED28,
PERIPH_ID_X_RESERVED29,
PERIPH_ID_X_RESERVED30,
PERIPH_ID_X_RESERVED31,
PERIPH_ID_AFC5,
PERIPH_ID_AFC4,
PERIPH_ID_AFC3,
PERIPH_ID_AFC2,
PERIPH_ID_AFC1,
PERIPH_ID_AFC0,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,

12
arch/arm/include/asm/arch-tegra124/flow.h
View file

@ -26,6 +26,12 @@ struct flow_ctlr {
u32 cpu_pwr_csr; /* offset 0x38 */
u32 mpid; /* offset 0x3c */
u32 ram_repair; /* offset 0x40 */
u32 flow_dbg_sel; /* offset 0x44 */
u32 flow_dbg_cnt0; /* offset 0x48 */
u32 flow_dbg_cnt1; /* offset 0x4c */
u32 flow_dbg_qual; /* offset 0x50 */
u32 flow_ctlr_spare; /* offset 0x54 */
u32 ram_repair_cluster1;/* offset 0x58 */
};
/* HALT_COP_EVENTS_0, 0x04 */
@ -43,4 +49,10 @@ struct flow_ctlr {
#define CSR_WAIT_WFI_SHIFT 8
#define CSR_PWR_OFF_STS (1 << 16)
/* RAM_REPAIR, 0x40, 0x58 */
enum {
RAM_REPAIR_REQ = 0x1 << 0,
RAM_REPAIR_STS = 0x1 << 1,
};
#endif /* _TEGRA124_FLOW_H_ */

6
arch/arm/mach-tegra/Kconfig
View file

@ -24,9 +24,15 @@ config SYS_MALLOC_F_LEN
config USE_PRIVATE_LIBGCC
default y
config DM_USB
default y
config SPL_DM
default y
config SPL_DISABLE_OF_CONTROL
default y
source "arch/arm/mach-tegra/tegra20/Kconfig"
source "arch/arm/mach-tegra/tegra30/Kconfig"
source "arch/arm/mach-tegra/tegra114/Kconfig"

9
arch/arm/mach-tegra/board2.c
View file

@ -107,6 +107,11 @@ __weak int tegra_lcd_pmic_init(int board_it)
return 0;
}
__weak int nvidia_board_init(void)
{
return 0;
}
/*
* Routine: board_init
* Description: Early hardware init.
@ -156,7 +161,6 @@ int board_init(void)
#ifdef CONFIG_USB_EHCI_TEGRA
pin_mux_usb();
usb_process_devicetree(gd->fdt_blob);
#endif
#ifdef CONFIG_LCD
@ -180,8 +184,7 @@ int board_init(void)
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
return 0;
return nvidia_board_init();
}
#ifdef CONFIG_BOARD_EARLY_INIT_F

24
arch/arm/mach-tegra/clock.c
View file

@ -17,11 +17,13 @@
/* Tegra SoC common clock control functions */
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/timer.h>
#include <div64.h>
#include <fdtdec.h>
@ -82,7 +84,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
assert(clock_id_is_pll(clkid));
if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
debug("%s: Invalid PLL\n", __func__);
debug("%s: Invalid PLL %d\n", __func__, clkid);
return NULL;
}
return &clkrst->crc_pll[clkid];
@ -118,9 +120,12 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon)
{
struct clk_pll *pll = get_pll(clkid);
struct clk_pll *pll = NULL;
u32 misc_data, data;
if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
pll = get_pll(clkid);
/*
* We cheat by treating all PLL (except PLLU) in the same fashion.
* This works only because:
@ -702,3 +707,18 @@ void tegra30_set_up_pllp(void)
set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
}
int clock_external_output(int clk_id)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
if (clk_id >= 1 && clk_id <= 3) {
setbits_le32(&pmc->pmc_clk_out_cntrl,
1 << (2 + (clk_id - 1) * 8));
} else {
printf("%s: Unknown output clock id %d\n", __func__, clk_id);
return -EINVAL;
}
return 0;
}

20
arch/arm/mach-tegra/powergate.c
View file

@ -9,7 +9,7 @@
#include <asm/io.h>
#include <asm/types.h>
#include <asm/arch/flow.h>
#include <asm/arch/powergate.h>
#include <asm/arch/tegra.h>
@ -75,11 +75,29 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id)
return 0;
}
static void tegra_powergate_ram_repair(void)
{
#ifdef CONFIG_TEGRA124
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
/* Request RAM repair for cluster 0 and wait until complete */
setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
;
/* Same for cluster 1 */
setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
;
#endif
}
int tegra_powergate_sequence_power_up(enum tegra_powergate id,
enum periph_id periph)
{
int err;
tegra_powergate_ram_repair();
reset_set_enable(periph, 1);
err = tegra_powergate_power_on(id);

2
arch/arm/mach-tegra/tegra124/Kconfig
View file

@ -10,7 +10,7 @@ config TARGET_JETSON_TK1
select CPU_V7_HAS_VIRT if !SPL_BUILD
config TARGET_NYAN_BIG
bool "Google/NVIDIA Nyan-big Chrombook"
bool "Google/NVIDIA Nyan-big Chromebook"
help
Nyan Big is a Tegra124 clamshell board that is very similar
to venice2, but it has a different panel, the sdcard CD and WP

2
arch/arm/mach-tegra/tegra124/clock.c
View file

@ -475,7 +475,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
PERIPHC_ACTMON,
/* 120 */
NONE(EXTPERIPH1),
PERIPHC_EXTPERIPH1,
NONE(EXTPERIPH2),
NONE(EXTPERIPH3),
NONE(OOB),

21
arch/avr32/Kconfig
View file

@ -17,35 +17,14 @@ config TARGET_ATNGW100MKII
config TARGET_ATSTK1002
bool "Support atstk1002"
config TARGET_ATSTK1003
bool "Support atstk1003"
config TARGET_ATSTK1004
bool "Support atstk1004"
config TARGET_ATSTK1006
bool "Support atstk1006"
config TARGET_FAVR_32_EZKIT
bool "Support favr-32-ezkit"
config TARGET_GRASSHOPPER
bool "Support grasshopper"
config TARGET_MIMC200
bool "Support mimc200"
config TARGET_HAMMERHEAD
bool "Support hammerhead"
endchoice
source "board/atmel/atngw100/Kconfig"
source "board/atmel/atngw100mkii/Kconfig"
source "board/atmel/atstk1000/Kconfig"
source "board/earthlcd/favr-32-ezkit/Kconfig"
source "board/in-circuit/grasshopper/Kconfig"
source "board/mimc/mimc200/Kconfig"
source "board/miromico/hammerhead/Kconfig"
endmenu

3
arch/avr32/lib/Makefile
View file

@ -8,9 +8,6 @@
#
obj-y += memset.o
ifndef CONFIG_SYS_GENERIC_BOARD
obj-y += board.o
endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += interrupts.o
obj-y += dram_init.o

256
arch/avr32/lib/board.c
View file

@ -1,256 +0,0 @@
/*
* Copyright (C) 2004-2006 Atmel Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
#include <version.h>
#include <net.h>
#ifdef CONFIG_BITBANGMII
#include <miiphy.h>
#endif
#include <asm/sections.h>
#include <asm/arch/mmu.h>
#include <asm/arch/hardware.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
#include <mmc.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
unsigned long monitor_flash_len;
__weak void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
}
/* Weak aliases for optional board functions */
static int __do_nothing(void)
{
return 0;
}
int board_postclk_init(void) __attribute__((weak, alias("__do_nothing")));
int board_early_init_r(void) __attribute__((weak, alias("__do_nothing")));
static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
return 0;
}
static int display_banner (void)
{
printf ("\n\n%s\n\n", version_string);
printf ("U-Boot code: %08lx -> %08lx data: %08lx -> %08lx\n",
(unsigned long)_text, (unsigned long)_etext,
(unsigned long)_data, (unsigned long)(&__bss_end));
return 0;
}
static int display_dram_config (void)
{
int i;
puts ("DRAM Configuration:\n");
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
print_size (gd->bd->bi_dram[i].size, "\n");
}
return 0;
}
static void display_flash_config (void)
{
puts ("Flash: ");
print_size(gd->bd->bi_flashsize, " ");
printf("at address 0x%08lx\n", gd->bd->bi_flashstart);
}
void board_init_f(ulong board_type)
{
gd_t gd_data;
gd_t *new_gd;
bd_t *bd;
unsigned long *new_sp;
unsigned long monitor_len;
unsigned long monitor_addr;
unsigned long addr;
/* Initialize the global data pointer */
memset(&gd_data, 0, sizeof(gd_data));
gd = &gd_data;
/* Perform initialization sequence */
board_early_init_f();
arch_cpu_init();
board_postclk_init();
env_init();
init_baudrate();
serial_init();
console_init_f();
display_banner();
dram_init();
/* If we have no SDRAM, we can't go on */
if (gd->ram_size <= 0)
panic("No working SDRAM available\n");
/*
* Now that we have DRAM mapped and working, we can
* relocate the code and continue running from DRAM.
*
* Reserve memory at end of RAM for (top down in that order):
* - u-boot image
* - heap for malloc()
* - board info struct
* - global data struct
* - stack
*/
addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
monitor_len = (char *)(&__bss_end) - _text;
/*
* Reserve memory for u-boot code, data and bss.
* Round down to next 4 kB limit.
*/
addr -= monitor_len;
addr &= ~(4096UL - 1);
monitor_addr = addr;
/* Reserve memory for malloc() */
addr -= CONFIG_SYS_MALLOC_LEN;
#ifdef CONFIG_LCD
#ifdef CONFIG_FB_ADDR
printf("LCD: Frame buffer allocated at preset 0x%08x\n",
CONFIG_FB_ADDR);
gd->fb_base = CONFIG_FB_ADDR;
#else
addr = lcd_setmem(addr);
printf("LCD: Frame buffer allocated at 0x%08lx\n", addr);
gd->fb_base = addr;
#endif /* CONFIG_FB_ADDR */
#endif /* CONFIG_LCD */
/* Allocate a Board Info struct on a word boundary */
addr -= sizeof(bd_t);
addr &= ~3UL;
gd->bd = bd = (bd_t *)addr;
/* Allocate a new global data copy on a 8-byte boundary. */
addr -= sizeof(gd_t);
addr &= ~7UL;
new_gd = (gd_t *)addr;
/* And finally, a new, bigger stack. */
new_sp = (unsigned long *)addr;
gd->start_addr_sp = addr;
*(--new_sp) = 0;
*(--new_sp) = 0;
dram_init_banksize();
memcpy(new_gd, gd, sizeof(gd_t));
relocate_code((unsigned long)new_sp, new_gd, monitor_addr);
}
void board_init_r(gd_t *new_gd, ulong dest_addr)
{
#ifndef CONFIG_ENV_IS_NOWHERE
extern char * env_name_spec;
#endif
bd_t *bd;
gd = new_gd;
bd = gd->bd;
gd->flags |= GD_FLG_RELOC;
gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
/* Enable the MMU so that we can keep u-boot simple */
mmu_init_r(dest_addr);
board_early_init_r();
monitor_flash_len = _edata - _text;
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
#ifndef CONFIG_ENV_IS_NOWHERE
env_name_spec += gd->reloc_off;
#endif
timer_init();
/* The malloc area is right below the monitor image in RAM */
mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
enable_interrupts();
bd->bi_flashstart = 0;
bd->bi_flashsize = 0;
bd->bi_flashoffset = 0;
#ifndef CONFIG_SYS_NO_FLASH
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
bd->bi_flashsize = flash_init();
bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text;
if (bd->bi_flashsize)
display_flash_config();
#endif
if (bd->bi_dram[0].size)
display_dram_config();
gd->bd->bi_boot_params = malloc(CONFIG_SYS_BOOTPARAMS_LEN);
if (!gd->bd->bi_boot_params)
puts("WARNING: Cannot allocate space for boot parameters\n");
/* initialize environment */
env_relocate();
stdio_init();
jumptable_init();
console_init_r();
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
puts("Net: ");
eth_initialize();
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
mmc_initialize(gd->bd);
#endif
for (;;) {
main_loop();
}
}

5
arch/sandbox/cpu/cpu.c
View file

@ -52,6 +52,11 @@ int cleanup_before_linux(void)
return 0;
}
int cleanup_before_linux_select(int flags)
{
return 0;
}
void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
#ifdef CONFIG_PCI

48
board/atmel/atstk1000/Kconfig
View file

@ -13,51 +13,3 @@ config SYS_CONFIG_NAME
default "atstk1002"
endif
if TARGET_ATSTK1003
config SYS_BOARD
default "atstk1000"
config SYS_VENDOR
default "atmel"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "atstk1003"
endif
if TARGET_ATSTK1004
config SYS_BOARD
default "atstk1000"
config SYS_VENDOR
default "atmel"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "atstk1004"
endif
if TARGET_ATSTK1006
config SYS_BOARD
default "atstk1000"
config SYS_VENDOR
default "atmel"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "atstk1006"
endif

10
board/atmel/atstk1000/MAINTAINERS
View file

@ -1,12 +1,6 @@
ATSTK1000 BOARD
#M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
S: Orphan (since 2014-06)
M: Andreas Bießmann <andreas.biessmann@corscience.de>
S: Maintained
F: board/atmel/atstk1000/
F: include/configs/atstk1002.h
F: configs/atstk1002_defconfig
F: include/configs/atstk1003.h
F: configs/atstk1003_defconfig
F: include/configs/atstk1004.h
F: configs/atstk1004_defconfig
F: include/configs/atstk1006.h
F: configs/atstk1006_defconfig

23
board/atmel/atstk1000/atstk1000.c
View file

@ -30,32 +30,12 @@ struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
};
static const struct sdram_config sdram_config = {
#if defined(CONFIG_ATSTK1006)
/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
.cas = 2,
.twr = 2,
.trc = 7,
.trp = 2,
.trcd = 2,
.tras = 4,
.txsr = 7,
/* 7.81 us */
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
#else
/* MT48LC2M32B2P-5 (8 MB) on motherboard */
#ifdef CONFIG_ATSTK1004
.data_bits = SDRAM_DATA_16BIT,
#else
.data_bits = SDRAM_DATA_32BIT,
#endif
#ifdef CONFIG_ATSTK1000_16MB_SDRAM
/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
.row_bits = 12,
#else
/* MT48LC2M32B2P-5 (8 MB) on motherboard */
.row_bits = 11,
#endif
.col_bits = 8,
@ -69,7 +49,6 @@ static const struct sdram_config sdram_config = {
.txsr = 5,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
#endif
};
int board_early_init_f(void)

15
board/earthlcd/favr-32-ezkit/Kconfig
View file

@ -1,15 +0,0 @@
if TARGET_FAVR_32_EZKIT
config SYS_BOARD
default "favr-32-ezkit"
config SYS_VENDOR
default "earthlcd"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "favr-32-ezkit"
endif

6
board/earthlcd/favr-32-ezkit/MAINTAINERS
View file

@ -1,6 +0,0 @@
FAVR-32-EZKIT BOARD
#M: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
S: Orphan (since 2014-06)
F: board/earthlcd/favr-32-ezkit/
F: include/configs/favr-32-ezkit.h
F: configs/favr-32-ezkit_defconfig

9
board/earthlcd/favr-32-ezkit/Makefile
View file

@ -1,9 +0,0 @@
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2008 Atmel Corporation
#
# SPDX-License-Identifier: GPL-2.0+
obj-y := favr-32-ezkit.o flash.o

81
board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
View file

@ -1,81 +0,0 @@
/*
* Copyright (C) 2008 Atmel Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
static const struct sdram_config sdram_config = {
/* MT48LC4M32B2P-6 (16 MB) */
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 12,
.col_bits = 8,
.bank_bits = 2,
.cas = 3,
.twr = 2,
.trc = 7,
.trp = 2,
.trcd = 2,
.tras = 5,
.txsr = 5,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
};
int board_early_init_f(void)
{
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart3(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
return 0;
}
#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bi)
{
return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
bi->bi_phy_id[0]);
}
#endif

216
board/earthlcd/favr-32-ezkit/flash.c
View file

@ -1,216 +0,0 @@
/*
* Copyright (C) 2008 Atmel Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
#include <asm/arch/cacheflush.h>
#include <asm/io.h>
#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
flash_info_t flash_info[1];
static void flash_identify(uint16_t *flash, flash_info_t *info)
{
unsigned long flags;
flags = disable_interrupts();
dcache_flush_unlocked();
writew(0xaa, flash + 0x555);
writew(0x55, flash + 0xaaa);
writew(0x90, flash + 0x555);
info->flash_id = readl(flash);
writew(0xff, flash);
readw(flash);
if (flags)
enable_interrupts();
}
unsigned long flash_init(void)
{
unsigned long addr;
unsigned int i;
flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
flash_info[0].sector_count = 135;
flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
flash_info[0].start[i] = addr;
for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
flash_info[0].start[i] = addr;
return CONFIG_SYS_FLASH_SIZE;
}
void flash_print_info(flash_info_t *info)
{
printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
info->flash_id >> 16, info->flash_id & 0xffff);
printf("Size: %ld MB in %d sectors\n",
info->size >> 10, info->sector_count);
}
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
unsigned long flags;
unsigned long start_time;
uint16_t *fb, *sb;
unsigned int i;
int ret;
uint16_t status;
if ((s_first < 0) || (s_first > s_last)
|| (s_last >= info->sector_count)) {
puts("Error: first and/or last sector out of range\n");
return ERR_INVAL;
}
for (i = s_first; i < s_last; i++)
if (info->protect[i]) {
printf("Error: sector %d is protected\n", i);
return ERR_PROTECTED;
}
fb = (uint16_t *)uncached(info->start[0]);
dcache_flush_unlocked();
for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
printf("Erasing sector %3d...", i);
sb = (uint16_t *)uncached(info->start[i]);
flags = disable_interrupts();
start_time = get_timer(0);
/* Unlock sector */
writew(0xaa, fb + 0x555);
writew(0x70, sb);
/* Erase sector */
writew(0xaa, fb + 0x555);
writew(0x55, fb + 0xaaa);
writew(0x80, fb + 0x555);
writew(0xaa, fb + 0x555);
writew(0x55, fb + 0xaaa);
writew(0x30, sb);
/* Wait for completion */
ret = ERR_OK;
do {
/* TODO: Timeout */
status = readw(sb);
} while ((status != 0xffff) && !(status & 0x28));
writew(0xf0, fb);
/*
* Make sure the command actually makes it to the bus
* before we re-enable interrupts.
*/
readw(fb);
if (flags)
enable_interrupts();
if (status != 0xffff) {
printf("Flash erase error at address 0x%p: 0x%02x\n",
sb, status);
ret = ERR_PROG_ERROR;
break;
}
}
if (ctrlc())
printf("User interrupt!\n");
return ERR_OK;
}
int write_buff(flash_info_t *info, uchar *src,
ulong addr, ulong count)
{
unsigned long flags;
uint16_t *base, *p, *s, *end;
uint16_t word, status, status1;
int ret = ERR_OK;
if (addr < info->start[0]
|| (addr + count) > (info->start[0] + info->size)
|| (addr + count) < addr) {
puts("Error: invalid address range\n");
return ERR_INVAL;
}
if (addr & 1 || count & 1 || (unsigned int)src & 1) {
puts("Error: misaligned source, destination or count\n");
return ERR_ALIGN;
}
base = (uint16_t *)uncached(info->start[0]);
end = (uint16_t *)uncached(addr + count);
flags = disable_interrupts();
dcache_flush_unlocked();
sync_write_buffer();
for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
p < end && !ctrlc(); p++, s++) {
word = *s;
writew(0xaa, base + 0x555);
writew(0x55, base + 0xaaa);
writew(0xa0, base + 0x555);
writew(word, p);
sync_write_buffer();
/* Wait for completion */
status1 = readw(p);
do {
/* TODO: Timeout */
status = status1;
status1 = readw(p);
} while (((status ^ status1) & 0x40) /* toggled */
&& !(status1 & 0x28)); /* error bits */
/*
* We'll need to check once again for toggle bit
* because the toggle bit may stop toggling as I/O5
* changes to "1" (ref at49bv642.pdf p9)
*/
status1 = readw(p);
status = readw(p);
if ((status ^ status1) & 0x40) {
printf("Flash write error at address 0x%p: "
"0x%02x != 0x%02x\n",
p, status,word);
ret = ERR_PROG_ERROR;
writew(0xf0, base);
readw(base);
break;
}
writew(0xf0, base);
readw(base);
}
if (flags)
enable_interrupts();
return ret;
}
#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */

15
board/mimc/mimc200/Kconfig
View file

@ -1,15 +0,0 @@
if TARGET_MIMC200
config SYS_BOARD
default "mimc200"
config SYS_VENDOR
default "mimc"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "mimc200"
endif

6
board/mimc/mimc200/MAINTAINERS
View file

@ -1,6 +0,0 @@
MIMC200 BOARD
M: Mark Jackson <mpfj@mimc.co.uk>
S: Maintained
F: board/mimc/mimc200/
F: include/configs/mimc200.h
F: configs/mimc200_defconfig

6
board/mimc/mimc200/Makefile
View file

@ -1,6 +0,0 @@
#
# Copyright (C) 2005-2006 Atmel Corporation
#
# SPDX-License-Identifier: GPL-2.0+
obj-y := mimc200.o

197
board/mimc/mimc200/mimc200.c
View file

@ -1,197 +0,0 @@
/*
* Copyright (C) 2006 Atmel Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
#include <atmel_lcdc.h>
#include <lcd.h>
#include "../../../arch/avr32/cpu/hsmc3.h"
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT,
.phys = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
#if defined(CONFIG_LCD)
/* 480x272x16 @ 72 Hz */
vidinfo_t panel_info = {
.vl_col = 480, /* Number of columns */
.vl_row = 272, /* Number of rows */
.vl_clk = 5000000, /* pixel clock in ps */
.vl_sync = ATMEL_LCDC_INVCLK_INVERTED |
ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
.vl_bpix = LCD_COLOR16, /* Bits per pixel, BPP = 2^n */
.vl_tft = 1, /* 0 = passive, 1 = TFT */
.vl_hsync_len = 42, /* Length of horizontal sync */
.vl_left_margin = 1, /* Time from sync to picture */
.vl_right_margin = 1, /* Time from picture to sync */
.vl_vsync_len = 1, /* Length of vertical sync */
.vl_upper_margin = 12, /* Time from sync to picture */
.vl_lower_margin = 1, /* Time from picture to sync */
.mmio = LCDC_BASE, /* Memory mapped registers */
};
void lcd_enable(void)
{
}
void lcd_disable(void)
{
}
#endif
DECLARE_GLOBAL_DATA_PTR;
static const struct sdram_config sdram_config = {
.data_bits = SDRAM_DATA_16BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
.cas = 3,
.twr = 2,
.trc = 6,
.trp = 2,
.trcd = 2,
.tras = 6,
.txsr = 6,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
};
int board_early_init_f(void)
{
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
/* Enable 26 address bits and NCS2 */
portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
/* de-assert "force sys reset" pin */
portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
/* init custom i/o */
/* cpu type inputs */
portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
PORTMUX_DIR_INPUT);
/* main board type inputs */
portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
PORTMUX_DIR_INPUT);
/* DEBUG input (use weak pullup) */
portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
/* are we suppressing the console ? */
if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
/* reset phys */
portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
udelay(5000);
/* release phys reset */
gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */
/* setup Data Flash chip select (NCS2) */
hsmc3_writel(MODE2, 0x20121003);
hsmc3_writel(CYCLE2, 0x000a0009);
hsmc3_writel(PULSE2, 0x0a060806);
hsmc3_writel(SETUP2, 0x00030102);
/* setup FRAM chip select (NCS3) */
hsmc3_writel(MODE3, 0x10120001);
hsmc3_writel(CYCLE3, 0x001e001d);
hsmc3_writel(PULSE3, 0x08040704);
hsmc3_writel(SETUP3, 0x02050204);
#if defined(CONFIG_MACB)
/* init macb0 pins */
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
#if defined(CONFIG_LCD)
portmux_enable_lcdc(1);
#endif
return 0;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
gd->bd->bi_phy_id[1] = 0x03;
return 0;
}
int board_postclk_init(void)
{
/* Use GCLK0 as 10MHz output */
gclk_enable_output(0, PORTMUX_DRIVE_LOW);
gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
return 0;
}
/* SPI chip select control */
#ifdef CONFIG_ATMEL_SPI
#include <spi.h>
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return (bus == 0) && (cs == 0);
}
void spi_cs_activate(struct spi_slave *slave)
{
}
void spi_cs_deactivate(struct spi_slave *slave)
{
}
#endif /* CONFIG_ATMEL_SPI */
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bi)
{
macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
return 0;
}
#endif

15
board/miromico/hammerhead/Kconfig
View file

@ -1,15 +0,0 @@
if TARGET_HAMMERHEAD
config SYS_BOARD
default "hammerhead"
config SYS_VENDOR
default "miromico"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "hammerhead"
endif

6
board/miromico/hammerhead/MAINTAINERS
View file

@ -1,6 +0,0 @@
HAMMERHEAD BOARD
M: Alex Raimondi <alex.raimondi@miromico.ch>
S: Maintained
F: board/miromico/hammerhead/
F: include/configs/hammerhead.h
F: configs/hammerhead_defconfig

6
board/miromico/hammerhead/Makefile
View file

@ -1,6 +0,0 @@
#
# Copyright (C) 2008 Miromico AG
#
# SPDX-License-Identifier: GPL-2.0+
obj-y := hammerhead.o

91
board/miromico/hammerhead/hammerhead.c
View file

@ -1,91 +0,0 @@
/*
* Copyright (C) 2008 Miromico AG
*
* Mostly copied form atmel ATNGW100 sources
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
static const struct sdram_config sdram_config = {
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
.cas = 3,
.twr = 2,
.trc = 7,
.trp = 2,
.trcd = 2,
.tras = 5,
.txsr = 5,
/* 7.81 us */
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
};
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
bis->bi_phy_id[0]);
}
#endif
int board_early_init_f(void)
{
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
return 0;
}
int board_postclk_init(void)
{
/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
gclk_enable_output(3, PORTMUX_DRIVE_LOW);
gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
return 0;
}

4
board/nokia/rx51/lowlevel_init.S
View file

@ -105,10 +105,6 @@ fix_start:
/* r6 - maximal u-boot size */
ldr r6, imagesize
/* fix return address */
subhi lr, lr, r5
addlo lr, lr, r5
/* r1 - start of u-boot after */
ldr r1, startaddr

2
board/nvidia/nyan-big/MAINTAINERS
View file

@ -1,4 +1,4 @@
NORRIN BOARD
NYAN-BIG BOARD
M: Allen Martin <amartin@nvidia.com>
S: Maintained
F: board/nvidia/nyan-big/

69
board/nvidia/nyan-big/nyan-big.c
View file

@ -8,7 +8,12 @@
#include <common.h>
#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
#include <asm/arch/mc.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <power/as3722.h>
#include <power/pmic.h>
#include "pinmux-config-nyan-big.h"
@ -57,3 +62,67 @@ int tegra_lcd_pmic_init(int board_id)
return 0;
}
/* Setup required information for Linux kernel */
static void setup_kernel_info(void)
{
struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
/* The kernel graphics driver needs this region locked down */
writel(0, &mc->mc_video_protect_bom);
writel(0, &mc->mc_video_protect_size_mb);
writel(1, &mc->mc_video_protect_reg_ctrl);
}
/*
* We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
* I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
* Otherwise reading AHUB devices will hang when the kernel boots.
*/
static void enable_required_clocks(void)
{
static enum periph_id ids[] = {
PERIPH_ID_I2S0,
PERIPH_ID_I2S1,
PERIPH_ID_I2S2,
PERIPH_ID_I2S3,
PERIPH_ID_I2S4,
PERIPH_ID_AUDIO,
PERIPH_ID_APBIF,
PERIPH_ID_DAM0,
PERIPH_ID_DAM1,
PERIPH_ID_DAM2,
PERIPH_ID_AMX0,
PERIPH_ID_AMX1,
PERIPH_ID_ADX0,
PERIPH_ID_ADX1,
PERIPH_ID_SPDIF,
PERIPH_ID_AFC0,
PERIPH_ID_AFC1,
PERIPH_ID_AFC2,
PERIPH_ID_AFC3,
PERIPH_ID_AFC4,
PERIPH_ID_AFC5,
PERIPH_ID_EXTPERIPH1
};
int i;
for (i = 0; i < ARRAY_SIZE(ids); i++)
clock_enable(ids[i]);
udelay(2);
for (i = 0; i < ARRAY_SIZE(ids); i++)
reset_set_enable(ids[i], 0);
}
int nvidia_board_init(void)
{
clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000);
/* For external MAX98090 audio codec */
clock_external_output(1);
setup_kernel_info();
enable_required_clocks();
return 0;
}

3
common/cmd_bdinfo.c
View file

@ -399,6 +399,9 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
printf("ARM frequency = %ld MHz\n", gd->bd->bi_arm_freq);
printf("DSP frequency = %ld MHz\n", gd->bd->bi_dsp_freq);
printf("DDR frequency = %ld MHz\n", gd->bd->bi_ddr_freq);
#endif
#ifdef CONFIG_BOARD_TYPES
printf("Board Type = %ld\n", gd->board_type);
#endif
return 0;
}

16
common/cmd_bmp.c
View file

@ -34,12 +34,12 @@ static int bmp_info (ulong addr);
* didn't contain a valid BMP signature.
*/
#ifdef CONFIG_VIDEO_BMP_GZIP
bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp,
void **alloc_addr)
struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
void **alloc_addr)
{
void *dst;
unsigned long len;
bmp_image_t *bmp;
struct bmp_image *bmp;
/*
* Decompress bmp image
@ -55,7 +55,7 @@ bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp,
bmp = dst;
/* align to 32-bit-aligned-address + 2 */
bmp = (bmp_image_t *)((((unsigned int)dst + 1) & ~3) + 2);
bmp = (struct bmp_image *)((((unsigned int)dst + 1) & ~3) + 2);
if (gunzip(bmp, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) {
free(dst);
@ -80,8 +80,8 @@ bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp,
return bmp;
}
#else
bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp,
void **alloc_addr)
struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
void **alloc_addr)
{
return NULL;
}
@ -187,7 +187,7 @@ U_BOOT_CMD(
*/
static int bmp_info(ulong addr)
{
bmp_image_t *bmp=(bmp_image_t *)addr;
struct bmp_image *bmp = (struct bmp_image *)addr;
void *bmp_alloc_addr = NULL;
unsigned long len;
@ -224,7 +224,7 @@ static int bmp_info(ulong addr)
int bmp_display(ulong addr, int x, int y)
{
int ret;
bmp_image_t *bmp = (bmp_image_t *)addr;
struct bmp_image *bmp = (struct bmp_image *)addr;
void *bmp_alloc_addr = NULL;
unsigned long len;

33
common/lcd.c
View file

@ -448,8 +448,8 @@ static void draw_encoded_bitmap(ushort **fbp, ushort c, int cnt)
/*
* Do not call this function directly, must be called from lcd_display_bitmap.
*/
static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb,
int x_off, int y_off)
static void lcd_display_rle8_bitmap(struct bmp_image *bmp, ushort *cmap,
uchar *fb, int x_off, int y_off)
{
uchar *bmap;
ulong width, height;
@ -548,10 +548,10 @@ __weak void fb_put_word(uchar **fb, uchar **from)
}
#endif /* CONFIG_BMP_16BPP */
__weak void lcd_set_cmap(bmp_image_t *bmp, unsigned colors)
__weak void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
{
int i;
bmp_color_table_entry_t cte;
struct bmp_color_table_entry cte;
ushort *cmap = configuration_get_cmap();
for (i = 0; i < colors; ++i) {
@ -572,12 +572,14 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
ushort *cmap_base = NULL;
ushort i, j;
uchar *fb;
bmp_image_t *bmp = (bmp_image_t *)map_sysmem(bmp_image, 0);
struct bmp_image *bmp = (struct bmp_image *)map_sysmem(bmp_image, 0);
uchar *bmap;
ushort padded_width;
unsigned long width, height, byte_width;
unsigned long pwidth = panel_info.vl_col;
unsigned colors, bpix, bmp_bpix;
int hdr_size;
struct bmp_color_table_entry *palette = bmp->color_table;
if (!bmp || !(bmp->header.signature[0] == 'B' &&
bmp->header.signature[1] == 'M')) {
@ -589,6 +591,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
width = get_unaligned_le32(&bmp->header.width);
height = get_unaligned_le32(&bmp->header.height);
bmp_bpix = get_unaligned_le16(&bmp->header.bit_count);
hdr_size = get_unaligned_le16(&bmp->header.size);
debug("hdr_size=%d, bmp_bpix=%d\n", hdr_size, bmp_bpix);
colors = 1 << bmp_bpix;
@ -613,8 +617,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
return 1;
}
debug("Display-bmp: %d x %d with %d colors\n",
(int)width, (int)height, (int)colors);
debug("Display-bmp: %d x %d with %d colors, display %d\n",
(int)width, (int)height, (int)colors, 1 << bpix);
if (bmp_bpix == 8)
lcd_set_cmap(bmp, colors);
@ -641,6 +645,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
cmap_base = configuration_get_cmap();
#ifdef CONFIG_LCD_BMP_RLE8
u32 compression = get_unaligned_le32(&bmp->header.compression);
debug("compressed %d %d\n", compression, BMP_BI_RLE8);
if (compression == BMP_BI_RLE8) {
if (bpix != 16) {
/* TODO implement render code for bpix != 16 */
@ -663,7 +668,19 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
if (bpix != 16) {
fb_put_byte(&fb, &bmap);
} else {
*(uint16_t *)fb = cmap_base[*(bmap++)];
struct bmp_color_table_entry *entry;
uint val;
if (cmap_base) {
val = cmap_base[*bmap];
} else {
entry = &palette[*bmap];
val = entry->blue >> 3 |
entry->green >> 2 << 5 |
entry->red >> 3 << 11;
}
*(uint16_t *)fb = val;
bmap++;
fb += sizeof(uint16_t) / sizeof(*fb);
}
}

14
common/malloc_simple.c
View file

@ -26,6 +26,20 @@ void *malloc_simple(size_t bytes)
return ptr;
}
void *memalign_simple(size_t align, size_t bytes)
{
ulong addr, new_ptr;
void *ptr;
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, bytes);
new_ptr = addr + bytes;
if (new_ptr > gd->malloc_limit)
return NULL;
ptr = map_sysmem(addr, bytes);
gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
return ptr;
}
#ifdef CONFIG_SYS_MALLOC_SIMPLE
void *calloc(size_t nmemb, size_t elem_size)
{

1
configs/am335x_boneblack_vboot_defconfig
View file

@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y

1
configs/arches_defconfig
View file

@ -6,3 +6,4 @@ CONFIG_DEFAULT_DEVICE_TREE="arches"
CONFIG_CMD_SETEXPR=y
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y

6
configs/atstk1003_defconfig
View file

@ -1,6 +0,0 @@
CONFIG_AVR32=y
CONFIG_TARGET_ATSTK1003=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "

6
configs/atstk1004_defconfig
View file

@ -1,6 +0,0 @@
CONFIG_AVR32=y
CONFIG_TARGET_ATSTK1004=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "

7
configs/atstk1006_defconfig
View file

@ -1,7 +0,0 @@
CONFIG_AVR32=y
CONFIG_CMD_NET=y
CONFIG_TARGET_ATSTK1006=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "

1
configs/bf527-ezkit-v2_defconfig
View file

@ -3,3 +3,4 @@ CONFIG_TARGET_BF527_EZKIT=y
CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1"
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/bf533-ezkit_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_BF533_EZKIT=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/bf533-stamp_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_BF533_STAMP=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/bf538f-ezkit_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_BF538F_EZKIT=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/bf548-ezkit_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_BF548_EZKIT=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/bf561-acvilon_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_BF561_ACVILON=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/bf561-ezkit_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_BF561_EZKIT=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/bf609-ezkit_defconfig
View file

@ -3,3 +3,4 @@ CONFIG_NETDEVICES=y
CONFIG_TARGET_BF609_EZKIT=y
CONFIG_CMD_NET=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_LIB_RAND=y

1
configs/br4_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_BR4=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/canyonlands_defconfig
View file

@ -6,4 +6,5 @@ CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
CONFIG_CMD_SETEXPR=y
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_OF_EMBED=y

1
configs/cm-bf533_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF533=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/cm-bf548_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF548=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/cm-bf561_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_CM_BF561=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

7
configs/favr-32-ezkit_defconfig
View file

@ -1,7 +0,0 @@
CONFIG_AVR32=y
CONFIG_CMD_NET=y
CONFIG_TARGET_FAVR_32_EZKIT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "

1
configs/galileo_defconfig
View file

@ -5,5 +5,6 @@ CONFIG_DEFAULT_DEVICE_TREE="galileo"
CONFIG_TARGET_GALILEO=y
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GENERATE_PIRQ_TABLE=y

7
configs/hammerhead_defconfig
View file

@ -1,7 +0,0 @@
CONFIG_AVR32=y
CONFIG_CMD_NET=y
CONFIG_TARGET_HAMMERHEAD=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "

1
configs/ibf-dsp561_defconfig
View file

@ -1,3 +1,4 @@
CONFIG_BLACKFIN=y
CONFIG_TARGET_IBF_DSP561=y
CONFIG_CMD_NET=y
CONFIG_LIB_RAND=y

1
configs/microblaze-generic_defconfig
View file

@ -4,4 +4,5 @@ CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SPL=y
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_OF_EMBED=y

3
configs/mimc200_defconfig
View file

@ -1,3 +0,0 @@
CONFIG_AVR32=y
CONFIG_TARGET_MIMC200=y
CONFIG_CMD_NET=y

5
configs/nyan-big_defconfig
View file

@ -6,3 +6,8 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
CONFIG_CMD_NET=y
CONFIG_DISPLAY_PORT=y
CONFIG_VIDEO_TEGRA124=y
CONFIG_DM_CROS_EC=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CMD_CROS_EC=y

1
configs/odroid_defconfig
View file

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ODROID=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
CONFIG_CMD_SETEXPR=y
CONFIG_CMD_NET=y

1
configs/origen_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_ORIGEN=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
CONFIG_SPL=y
CONFIG_CMD_SETEXPR=y

1
configs/pr1_defconfig
View file

@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y
CONFIG_TARGET_PR1=y
CONFIG_CMD_NET=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y

1
configs/s5pc210_universal_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_S5PC210_UNIVERSAL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
CONFIG_CMD_SETEXPR=y
CONFIG_OF_CONTROL=y

1
configs/sandbox_defconfig
View file

@ -41,3 +41,4 @@ CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
CONFIG_SANDBOX_SERIAL=y

1
configs/socfpga_socrates_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TARGET_SOCFPGA_CYCLONE5=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_NETDEVICES=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL=y

1
configs/trats2_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_TRATS2=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
CONFIG_CMD_SETEXPR=y

1
configs/trats_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TARGET_TRATS=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
CONFIG_CMD_SETEXPR=y
CONFIG_OF_CONTROL=y

1
configs/zynq_microzed_defconfig
View file

@ -4,6 +4,7 @@ CONFIG_TARGET_ZYNQ_MICROZED=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y

1
configs/zynq_zc70x_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZC70X=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y

1
configs/zynq_zc770_xm010_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y

1
configs/zynq_zc770_xm012_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y

1
configs/zynq_zc770_xm013_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y

1
configs/zynq_zed_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZED=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y

1
configs/zynq_zybo_defconfig
View file

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZYBO=y
CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y

6
doc/README.scrapyard
View file

@ -12,6 +12,12 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
atstk1003 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
atstk1004 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
atstk1006 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
mimc200 avr32 - c62d2f8f 2015-06-10 Mark Jackson <mpfj@mimc.co.uk>
hammerhead avr32 - e3693076 2015-06-10 Alex Raimondi <alex.raimondi@miromico.ch>
favr-32-ezkit avr32 - 9eb45aab 2015-06-10 Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
afeb9260 arm arm926ejs f6b42c14 2015-05-13 Sergey Lapin <slapin@ossfans.org>
tny_a9260 arm arm926ejs f6b42c14 2015-05-13 Albin Tonnerre <albin.tonnerre@free-electrons.com>
sbc35_a9g20 arm arm926ejs f6b42c14 2015-05-13 Albin Tonnerre <albin.tonnerre@free-electrons.com>

2
drivers/core/Makefile
View file

@ -5,5 +5,7 @@
#
obj-$(CONFIG_DM) += device.o lists.o root.o uclass.o util.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_OF_CONTROL) += simple-bus.o
endif
obj-$(CONFIG_DM_DEVICE_REMOVE) += device-remove.o

21
drivers/i2c/i2c-uclass-compat.c
View file

@ -106,3 +106,24 @@ void board_i2c_init(const void *blob)
{
/* Nothing to do here - the init happens through driver model */
}
uint8_t i2c_reg_read(uint8_t chip_addr, uint8_t offset)
{
struct udevice *dev;
int ret;
ret = i2c_compat_get_device(chip_addr, 1, &dev);
if (ret)
return 0xff;
return dm_i2c_reg_read(dev, offset);
}
void i2c_reg_write(uint8_t chip_addr, uint8_t offset, uint8_t val)
{
struct udevice *dev;
int ret;
ret = i2c_compat_get_device(chip_addr, 1, &dev);
if (!ret)
dm_i2c_reg_write(dev, offset, val);
}

20
drivers/serial/Kconfig
View file

@ -76,6 +76,26 @@ config DEBUG_UART_SHIFT
value. Use this value to specify the shift to use, where 0=byte
registers, 2=32-bit word registers, etc.
config SANDBOX_SERIAL
bool "Sandbox UART support"
depends on SANDBOX && DM
help
Select this to enable a seral UART for sandbox. This is required to
operate correctly, otherwise you will see no serial output from
sandbox. The emulated UART will display to the console and console
input will be fed into the UART. This allows you to interact with
U-Boot.
The operation of the console is controlled by the -t command-line
flag. In raw mode, U-Boot sees all characters from the terminal
before they are processed, including Ctrl-C. In cooked mode, Ctrl-C
is processed by the terminal, and terminates U-Boot. Valid options
are:
-t raw-with-sigs Raw mode, Ctrl-C will terminate U-Boot
-t raw Raw mode, Ctrl-C is processed by U-Boot
-t cooked Cooked mode, Ctrl-C terminates
config UNIPHIER_SERIAL
bool "Support for UniPhier on-chip UART"
depends on ARCH_UNIPHIER && DM_SERIAL

4
drivers/serial/ns16550.c
View file

@ -65,6 +65,8 @@ static inline void serial_out_shift(void *addr, int shift, int value)
out_le32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
out_be32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32)
writel(value, addr);
#elif defined(CONFIG_SYS_BIG_ENDIAN)
writeb(value, addr + (1 << shift) - 1);
#else
@ -80,6 +82,8 @@ static inline int serial_in_shift(void *addr, int shift)
return in_le32(addr);
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
return in_be32(addr);
#elif defined(CONFIG_SYS_NS16550_MEM32)
return readl(addr);
#elif defined(CONFIG_SYS_BIG_ENDIAN)
return readb(addr + (1 << shift) - 1);
#else

68
drivers/serial/serial-uclass.c
View file

@ -30,49 +30,55 @@ static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
static void serial_find_console_or_panic(void)
{
struct udevice *dev;
#ifdef CONFIG_OF_CONTROL
int node;
/* Check for a chosen console */
node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
if (node < 0)
node = fdt_path_offset(gd->fdt_blob, "console");
if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) {
gd->cur_serial_dev = dev;
return;
}
/*
* If the console is not marked to be bound before relocation, bind
* it anyway.
*/
if (node > 0 &&
!lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) {
if (!device_probe(dev)) {
if (OF_CONTROL && gd->fdt_blob) {
/* Check for a chosen console */
node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
if (node < 0)
node = fdt_path_offset(gd->fdt_blob, "console");
if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node,
&dev)) {
gd->cur_serial_dev = dev;
return;
}
/*
* If the console is not marked to be bound before relocation,
* bind it anyway.
*/
if (node > 0 &&
!lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) {
if (!device_probe(dev)) {
gd->cur_serial_dev = dev;
return;
}
}
}
#endif
/*
* Try to use CONFIG_CONS_INDEX if available (it is numbered from 1!).
*
* Failing that, get the device with sequence number 0, or in extremis
* just the first serial device we can find. But we insist on having
* a console (even if it is silent).
*/
if (!SPL_BUILD || !OF_CONTROL || !gd->fdt_blob) {
/*
* Try to use CONFIG_CONS_INDEX if available (it is numbered
* from 1!).
*
* Failing that, get the device with sequence number 0, or in
* extremis just the first serial device we can find. But we
* insist on having a console (even if it is silent).
*/
#ifdef CONFIG_CONS_INDEX
#define INDEX (CONFIG_CONS_INDEX - 1)
#else
#define INDEX 0
#endif
if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) &&
uclass_get_device(UCLASS_SERIAL, INDEX, &dev) &&
(uclass_first_device(UCLASS_SERIAL, &dev) || !dev))
panic_str("No serial driver found");
if (!uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) ||
!uclass_get_device(UCLASS_SERIAL, INDEX, &dev) ||
(!uclass_first_device(UCLASS_SERIAL, &dev) || dev)) {
gd->cur_serial_dev = dev;
return;
}
#undef INDEX
gd->cur_serial_dev = dev;
}
panic_str("No serial driver found");
}
/* Called prior to relocation */

40
drivers/spi/tegra114_spi.c
View file

@ -143,24 +143,30 @@ static int tegra114_spi_probe(struct udevice *bus)
{
struct tegra_spi_platdata *plat = dev_get_platdata(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
struct spi_regs *regs;
ulong rate;
priv->regs = (struct spi_regs *)plat->base;
regs = priv->regs;
priv->last_transaction_us = timer_get_us();
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
return 0;
}
static int tegra114_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
struct tegra114_spi_priv *priv = dev_get_priv(bus);
struct spi_regs *regs = priv->regs;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
/*
* Change SPI clock to correct frequency, PLLP_OUT0 source, falling
* back to the oscillator if that is too fast.
*/
rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
priv->freq);
if (rate > priv->freq + 100000) {
rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
priv->freq);
if (rate != priv->freq) {
printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
bus->name, priv->freq, rate);
}
}
/* Clear stale status here */
setbits_le32(&regs->fifo_status,
@ -175,9 +181,8 @@ static int tegra114_spi_claim_bus(struct udevice *dev)
SPI_FIFO_STS_RX_FIFO_EMPTY);
debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
/* Set master mode and sw controlled CS */
setbits_le32(&regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
(priv->mode << SPI_CMD1_MODE_SHIFT));
setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
(priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL);
debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
return 0;
@ -249,6 +254,9 @@ static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
ret = 0;
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev);
/* clear all error status bits */
reg = readl(&regs->fifo_status);
writel(reg, &regs->fifo_status);
@ -260,9 +268,6 @@ static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
/* set xfer size to 1 block (32 bits) */
writel(0, &regs->dma_blk);
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(dev);
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
int bytes;
@ -385,7 +390,6 @@ static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
}
static const struct dm_spi_ops tegra114_spi_ops = {
.claim_bus = tegra114_spi_claim_bus,
.xfer = tegra114_spi_xfer,
.set_speed = tegra114_spi_set_speed,
.set_mode = tegra114_spi_set_mode,

150
drivers/usb/host/ehci-tegra.c
View file

@ -35,12 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#endif
#ifndef CONFIG_DM_USB
enum {
USB_PORTS_MAX = 3, /* Maximum ports we allow */
};
#endif
/* Parameters we need for USB */
enum {
PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
@ -82,9 +76,6 @@ struct fdt_usb {
unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
unsigned enabled:1; /* 1 to enable, 0 to disable */
unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
#ifndef CONFIG_DM_USB
unsigned initialized:1; /* has this port already been initialized? */
#endif
enum usb_ctlr_type type;
enum usb_init_type init_type;
enum dr_mode dr_mode; /* dual role mode */
@ -93,11 +84,6 @@ struct fdt_usb {
struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */
};
#ifndef CONFIG_DM_USB
static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
static unsigned port_count; /* Number of available ports */
#endif
/*
* This table has USB timing parameters for each Oscillator frequency we
* support. There are four sets of values:
@ -173,8 +159,6 @@ static const u8 utmip_elastic_limit = 16;
static const u8 utmip_hs_sync_start_delay = 9;
struct fdt_usb_controller {
/* TODO(sjg@chromium.org): Remove when we only use driver model */
int compat;
/* flag to determine whether controller supports hostpc register */
u32 has_hostpc:1;
const unsigned *pll_parameter;
@ -182,17 +166,14 @@ struct fdt_usb_controller {
static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = {
{
.compat = COMPAT_NVIDIA_TEGRA20_USB,
.has_hostpc = 0,
.pll_parameter = (const unsigned *)T20_usb_pll,
},
{
.compat = COMPAT_NVIDIA_TEGRA30_USB,
.has_hostpc = 1,
.pll_parameter = (const unsigned *)T30_usb_pll,
},
{
.compat = COMPAT_NVIDIA_TEGRA114_USB,
.has_hostpc = 1,
.pll_parameter = (const unsigned *)T114_usb_pll,
},
@ -754,12 +735,6 @@ int usb_common_init(struct fdt_usb *config, enum usb_init_type init)
return -1;
}
#ifndef CONFIG_DM_USB
/* skip init, if the port is already initialized */
if (config->initialized && config->init_type == init)
return 0;
#endif
debug("%d, %d\n", config->utmi, config->ulpi);
if (config->utmi)
ret = init_utmi_usb_controller(config, init);
@ -796,130 +771,6 @@ static const struct ehci_ops tegra_ehci_ops = {
.powerup_fixup = tegra_ehci_powerup_fixup,
};
#ifndef CONFIG_DM_USB
/*
* process_usb_nodes() - Process a list of USB nodes, adding them to our list
* of USB ports.
* @blob: fdt blob
* @node_list: list of nodes to process (any <=0 are ignored)
* @count: number of nodes to process
* @id: controller type (enum usb_ctlr_type)
*
* Return: 0 - ok, -1 - error
*/
static int process_usb_nodes(const void *blob, int node_list[], int count,
enum usb_ctlr_type id)
{
struct fdt_usb config;
int node, i;
int clk_done = 0;
port_count = 0;
for (i = 0; i < count; i++) {
if (port_count == USB_PORTS_MAX) {
printf("tegrausb: Cannot register more than %d ports\n",
USB_PORTS_MAX);
return -1;
}
debug("USB %d: ", i);
node = node_list[i];
if (!node)
continue;
if (fdt_decode_usb(blob, node, &config)) {
debug("Cannot decode USB node %s\n",
fdt_get_name(blob, node, NULL));
return -1;
}
if (!clk_done) {
config_clock(get_pll_timing(
&fdt_usb_controllers[id]));
clk_done = 1;
}
config.type = id;
config.initialized = 0;
/* add new USB port to the list of available ports */
port[port_count++] = config;
}
return 0;
}
int usb_process_devicetree(const void *blob)
{
int node_list[USB_PORTS_MAX];
int count, err = 0;
int i;
for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) {
count = fdtdec_find_aliases_for_id(blob, "usb",
fdt_usb_controllers[i].compat, node_list,
USB_PORTS_MAX);
if (count) {
err = process_usb_nodes(blob, node_list, count, i);
if (err)
printf("%s: Error processing USB node!\n",
__func__);
return err;
}
}
return err;
}
/**
* Start up the given port number (ports are numbered from 0 on each board).
* This returns values for the appropriate hccr and hcor addresses to use for
* USB EHCI operations.
*
* @param index port number to start
* @param hccr returns start address of EHCI HCCR registers
* @param hcor returns start address of EHCI HCOR registers
* @return 0 if ok, -1 on error (generally invalid port number)
*/
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct fdt_usb *config;
struct usb_ctlr *usbctlr;
int ret;
if (index >= port_count)
return -1;
config = &port[index];
ehci_set_controller_priv(index, config, &tegra_ehci_ops);
ret = usb_common_init(config, init);
if (ret) {
printf("tegrausb: Cannot init port %d\n", index);
return ret;
}
config->initialized = 1;
usbctlr = config->reg;
*hccr = (struct ehci_hccr *)&usbctlr->cap_length;
*hcor = (struct ehci_hcor *)&usbctlr->usb_cmd;
return 0;
}
/*
* Bring down the specified USB controller
*/
int ehci_hcd_stop(int index)
{
usb_common_uninit(&port[index]);
port[index].initialized = 0;
return 0;
}
#endif /* !CONFIG_DM_USB */
#ifdef CONFIG_DM_USB
static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
{
struct fdt_usb *priv = dev_get_priv(dev);
@ -987,4 +838,3 @@ U_BOOT_DRIVER(usb_ehci) = {
.priv_auto_alloc_size = sizeof(struct fdt_usb),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif

43
drivers/usb/host/usb-uclass.c
View file

@ -628,6 +628,49 @@ int usb_scan_device(struct udevice *parent, int port,
return 0;
}
/*
* Detect if a USB device has been plugged or unplugged.
*/
int usb_detect_change(void)
{
struct udevice *hub;
struct uclass *uc;
int change = 0;
int ret;
ret = uclass_get(UCLASS_USB_HUB, &uc);
if (ret)
return ret;
uclass_foreach_dev(hub, uc) {
struct usb_device *udev;
struct udevice *dev;
if (!device_active(hub))
continue;
for (device_find_first_child(hub, &dev);
dev;
device_find_next_child(&dev)) {
struct usb_port_status status;
if (!device_active(dev))
continue;
udev = dev_get_parentdata(dev);
if (usb_get_port_status(udev, udev->portnr, &status)
< 0)
/* USB request failed */
continue;
if (le16_to_cpu(status.wPortChange) &
USB_PORT_STAT_C_CONNECTION)
change++;
}
}
return change;
}
int usb_child_post_bind(struct udevice *dev)
{
struct usb_dev_platdata *plat = dev_get_parent_platdata(dev);

4
drivers/video/atmel_lcdfb.c
View file

@ -81,12 +81,12 @@ void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
#endif
}
void lcd_set_cmap(bmp_image_t *bmp, unsigned colors)
void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
{
int i;
for (i = 0; i < colors; ++i) {
bmp_color_table_entry_t cte = bmp->color_table[i];
struct bmp_color_table_entry cte = bmp->color_table[i];
lcd_setcolreg(i, cte.red, cte.green, cte.blue);
}
}

4
drivers/video/bus_vcxk.c
View file

@ -358,7 +358,7 @@ void vcxk_draw_mono(unsigned char *dataptr, unsigned long linewidth,
int vcxk_display_bitmap(ulong addr, int x, int y)
{
bmp_image_t *bmp;
struct bmp_image *bmp;
unsigned long width;
unsigned long height;
unsigned long bpp;
@ -369,7 +369,7 @@ int vcxk_display_bitmap(ulong addr, int x, int y)
unsigned long c_height;
unsigned char *dataptr;
bmp = (bmp_image_t *) addr;
bmp = (struct bmp_image *)addr;
if ((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M')) {
width = le32_to_cpu(bmp->header.width);

10
drivers/video/cfb_console.c
View file

@ -1295,7 +1295,7 @@ static void draw_bitmap(uchar **fb, uchar *bm, struct palette *p,
*fb = (uchar *) addr; /* return modified address */
}
static int display_rle8_bitmap(bmp_image_t *img, int xoff, int yoff,
static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff,
int width, int height)
{
unsigned char *bm;
@ -1304,7 +1304,7 @@ static int display_rle8_bitmap(bmp_image_t *img, int xoff, int yoff,
int decode = 1;
int x, y, bpp, i, ncolors;
struct palette p[256];
bmp_color_table_entry_t cte;
struct bmp_color_table_entry cte;
int green_shift, red_off;
int limit = VIDEO_COLS * VIDEO_ROWS;
int pixels = 0;
@ -1447,13 +1447,13 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
{
ushort xcount, ycount;
uchar *fb;
bmp_image_t *bmp = (bmp_image_t *) bmp_image;
struct bmp_image *bmp = (struct bmp_image *)bmp_image;
uchar *bmap;
ushort padded_line;
unsigned long width, height, bpp;
unsigned colors;
unsigned long compression;
bmp_color_table_entry_t cte;
struct bmp_color_table_entry cte;
#ifdef CONFIG_VIDEO_BMP_GZIP
unsigned char *dst = NULL;
@ -1495,7 +1495,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
/*
* Set addr to decompressed image
*/
bmp = (bmp_image_t *)(dst+2);
bmp = (struct bmp_image *)(dst+2);
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {

4
drivers/video/tegra124/tegra124-lcd.c
View file

@ -51,15 +51,13 @@ static int tegra124_lcd_init(void *lcdbase)
int ret;
clock_set_up_plldp();
clock_adjust_periph_pll_div(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
408000000, NULL);
clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
clock_enable(PERIPH_ID_HOST1X);
clock_enable(PERIPH_ID_DISP1);
clock_enable(PERIPH_ID_PWM);
clock_enable(PERIPH_ID_DPAUX);
clock_enable(PERIPH_ID_SOR0);
udelay(2);
reset_set_enable(PERIPH_ID_HOST1X, 0);

17
include/bmp_layout.h
View file

@ -11,17 +11,17 @@
#ifndef _BMP_H_
#define _BMP_H_
typedef struct bmp_color_table_entry {
struct __packed bmp_color_table_entry {
__u8 blue;
__u8 green;
__u8 red;
__u8 reserved;
} __attribute__ ((packed)) bmp_color_table_entry_t;
};
/* When accessing these fields, remember that they are stored in little
endian format, so use linux macros, e.g. le32_to_cpu(width) */
typedef struct bmp_header {
struct __packed bmp_header {
/* Header */
char signature[2];
__u32 file_size;
@ -40,15 +40,14 @@ typedef struct bmp_header {
__u32 colors_used;
__u32 colors_important;
/* ColorTable */
};
} __attribute__ ((packed)) bmp_header_t;
typedef struct bmp_image {
bmp_header_t header;
struct bmp_image {
struct bmp_header header;
/* We use a zero sized array just as a placeholder for variable
sized array */
bmp_color_table_entry_t color_table[0];
} bmp_image_t;
struct bmp_color_table_entry color_table[0];
};
/* Data in the bmp_image is aligned to this length */
#define BMP_DATA_ALIGN 4

15
include/common.h
View file

@ -714,6 +714,21 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_all(void);
void invalidate_icache_all(void);
enum {
/* Disable caches (else flush caches but leave them active) */
CBL_DISABLE_CACHES = 1 << 0,
CBL_SHOW_BOOTSTAGE_REPORT = 1 << 1,
CBL_ALL = 3,
};
/**
* Clean up ready for linux
*
* @param flags Flags to control what is done
*/
int cleanup_before_linux_select(int flags);
/* arch/$(ARCH)/lib/ticks.S */
uint64_t get_ticks(void);
void wait_ticks (unsigned long);

Some files were not shown because too many files have changed in this diff Show more