Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-11 15:37:23 +00:00
Code Issues Projects Releases Packages Wiki Activity

mmc: sunxi: add support for automatic delay calibration

Browse source 
A64 and H6 support automatic delay calibration and Linux driver uses it
instead of hardcoded delays. Add support for it to u-boot driver.

Fixes eMMC instability on Pinebook

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Vasily Khoruzhick 2018-11-05 20:24:28 -08:00 committed by Jagan Teki
parent 4f9d34e633
commit 20940ef2a3
2 changed files with 25 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
arch/arm/include/asm/arch-sunxi/mmc.h
View file

@ -46,7 +46,9 @@ struct sunxi_mmc {
u32 cbda; /* 0x94 */ u32 cbda; /* 0x94 */
u32 res2[26]; u32 res2[26];
#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
u32 res3[64]; u32 res3[17];
u32 samp_dl;
u32 res4[46];
#endif #endif
u32 fifo; /* 0x100 / 0x200 FIFO access address */ u32 fifo; /* 0x100 / 0x200 FIFO access address */
}; };
@ -130,5 +132,7 @@ struct sunxi_mmc {
#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
#define SUNXI_MMC_COMMON_RESET (1 << 18) #define SUNXI_MMC_COMMON_RESET (1 << 18)
#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
struct mmc *sunxi_mmc_init(int sdc_no); struct mmc *sunxi_mmc_init(int sdc_no);
#endif /* _SUNXI_MMC_H */ #endif /* _SUNXI_MMC_H */

21
drivers/mmc/sunxi_mmc.c
View file

@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
{ {
unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
bool new_mode = false; bool new_mode = false;
bool calibrate = false;
u32 val = 0; u32 val = 0;
if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2)) if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
new_mode = true; new_mode = true;
#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
calibrate = true;
#endif
/* /*
* The MMC clock has an extra /2 post-divider when operating in the new * The MMC clock has an extra /2 post-divider when operating in the new
* mode. * mode.
@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
val = CCM_MMC_CTRL_MODE_SEL_NEW; val = CCM_MMC_CTRL_MODE_SEL_NEW;
setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
#endif #endif
} else { } else if (!calibrate) {
/*
* Use hardcoded delay values if controller doesn't support
* calibration
*/
val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
CCM_MMC_CTRL_SCLK_DLY(sclk_dly); CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
} }
@ -228,6 +237,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
writel(rval, &priv->reg->clkcr); writel(rval, &priv->reg->clkcr);
#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
/* A64 supports calibration of delays on MMC controller and we
* have to set delay of zero before starting calibration.
* Allwinner BSP driver sets a delay only in the case of
* using HS400 which is not supported by mainline U-Boot or
* Linux at the moment
*/
writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
#endif
/* Re-enable Clock */ /* Re-enable Clock */
rval |= SUNXI_MMC_CLK_ENABLE; rval |= SUNXI_MMC_CLK_ENABLE;
writel(rval, &priv->reg->clkcr); writel(rval, &priv->reg->clkcr);