mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 16:39:35 +00:00
Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
commit
207f83f102
19 changed files with 394 additions and 2780 deletions
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|
@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2007
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* (C) Copyright 2007-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@ -246,6 +246,18 @@ int checkboard (void)
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return 0;
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}
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/*
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* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
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* board specific values.
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*/
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u32 ddr_wrdtr(u32 default_val) {
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return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
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}
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u32 ddr_clktr(u32 default_val) {
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return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
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}
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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@ -33,343 +33,11 @@
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#include <asm/io.h>
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#include <ppc440.h>
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#include "sdram.h"
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
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defined(CONFIG_DDR_DATA_EYE)
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/*-----------------------------------------------------------------------------+
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* wait_for_dlllock.
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+----------------------------------------------------------------------------*/
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static int wait_for_dlllock(void)
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{
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unsigned long val;
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int wait = 0;
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/* -----------------------------------------------------------+
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* Wait for the DCC master delay line to finish calibration
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_17);
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val = DDR0_17_DLLLOCKREG_UNLOCKED;
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while (wait != 0xffff) {
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val = mfdcr(ddrcfgd);
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if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
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/* dlllockreg bit on */
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return 0;
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else
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wait++;
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}
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debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
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debug("Waiting for dlllockreg bit to raise\n");
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return -1;
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}
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#endif
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#if defined(CONFIG_DDR_DATA_EYE)
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/*-----------------------------------------------------------------------------+
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* wait_for_dram_init_complete.
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+----------------------------------------------------------------------------*/
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int wait_for_dram_init_complete(void)
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{
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unsigned long val;
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int wait = 0;
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/* --------------------------------------------------------------+
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* Wait for 'DRAM initialization complete' bit in status register
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* -------------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_00);
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while (wait != 0xffff) {
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val = mfdcr(ddrcfgd);
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if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
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/* 'DRAM initialization complete' bit */
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return 0;
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else
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wait++;
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}
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debug("DRAM initialization complete bit in status register did not rise\n");
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return -1;
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}
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#define NUM_TRIES 64
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#define NUM_READS 10
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/*-----------------------------------------------------------------------------+
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* denali_core_search_data_eye.
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+----------------------------------------------------------------------------*/
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void denali_core_search_data_eye(unsigned long memory_size)
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{
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int k, j;
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u32 val;
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u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
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u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
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u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
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u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
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volatile u32 *ram_pointer;
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u32 test[NUM_TRIES] = {
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
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ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
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for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
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/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
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/* -----------------------------------------------------------+
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* De-assert 'start' parameter.
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
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mtdcr(ddrcfgd, val);
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/* -----------------------------------------------------------+
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* Set 'wr_dqs_shift'
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_09);
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val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
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| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
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mtdcr(ddrcfgd, val);
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/* -----------------------------------------------------------+
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* Set 'dqs_out_shift' = wr_dqs_shift + 32
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* ----------------------------------------------------------*/
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dqs_out_shift = wr_dqs_shift + 32;
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mtdcr(ddrcfga, DDR0_22);
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val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
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| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
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mtdcr(ddrcfgd, val);
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passing_cases = 0;
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for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
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/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
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/* -----------------------------------------------------------+
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* Set 'dll_dqs_delay_X'.
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* ----------------------------------------------------------*/
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/* dll_dqs_delay_0 */
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mtdcr(ddrcfga, DDR0_17);
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val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
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| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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/* dll_dqs_delay_1 to dll_dqs_delay_4 */
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mtdcr(ddrcfga, DDR0_18);
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val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
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| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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/* dll_dqs_delay_5 to dll_dqs_delay_8 */
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mtdcr(ddrcfga, DDR0_19);
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val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
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| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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ppcMsync();
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ppcMbar();
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/* -----------------------------------------------------------+
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* Assert 'start' parameter.
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
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mtdcr(ddrcfgd, val);
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ppcMsync();
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ppcMbar();
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/* -----------------------------------------------------------+
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* Wait for the DCC master delay line to finish calibration
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* ----------------------------------------------------------*/
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if (wait_for_dlllock() != 0) {
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printf("dlllock did not occur !!!\n");
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printf("denali_core_search_data_eye!!!\n");
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printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
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wr_dqs_shift, dll_dqs_delay_X);
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hang();
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}
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ppcMsync();
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ppcMbar();
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if (wait_for_dram_init_complete() != 0) {
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printf("dram init complete did not occur !!!\n");
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printf("denali_core_search_data_eye!!!\n");
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printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
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wr_dqs_shift, dll_dqs_delay_X);
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hang();
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}
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udelay(100); /* wait 100us to ensure init is really completed !!! */
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/* write values */
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for (j=0; j<NUM_TRIES; j++) {
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ram_pointer[j] = test[j];
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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}
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/* read values back */
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for (j=0; j<NUM_TRIES; j++) {
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for (k=0; k<NUM_READS; k++) {
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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if (ram_pointer[j] != test[j])
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break;
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}
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/* read error */
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if (k != NUM_READS)
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break;
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}
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/* See if the dll_dqs_delay_X value passed.*/
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if (j < NUM_TRIES) {
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/* Failed */
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passing_cases = 0;
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/* break; */
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} else {
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/* Passed */
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if (passing_cases == 0)
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dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
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passing_cases++;
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if (passing_cases >= max_passing_cases) {
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max_passing_cases = passing_cases;
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wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
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dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
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dll_dqs_delay_X_end_window = dll_dqs_delay_X;
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}
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}
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/* -----------------------------------------------------------+
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* De-assert 'start' parameter.
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||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
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||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
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mtdcr(ddrcfgd, val);
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||||
|
||||
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
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|
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} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
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||||
|
||||
/* -----------------------------------------------------------+
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* Largest passing window is now detected.
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||||
* ----------------------------------------------------------*/
|
||||
|
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/* Compute dll_dqs_delay_X value */
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dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
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wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
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|
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debug("DQS calibration - Window detected:\n");
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debug("max_passing_cases = %d\n", max_passing_cases);
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||||
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
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||||
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
|
||||
debug("dll_dqs_delay_X window = %d - %d\n",
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dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* De-assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'wr_dqs_shift'
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_09);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_09=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||
* ----------------------------------------------------------*/
|
||||
dqs_out_shift = wr_dqs_shift + 32;
|
||||
mtdcr(ddrcfga, DDR0_22);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_22=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dll_dqs_delay_X'.
|
||||
* ----------------------------------------------------------*/
|
||||
/* dll_dqs_delay_0 */
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_17=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||
mtdcr(ddrcfga, DDR0_18);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_18=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||
mtdcr(ddrcfga, DDR0_19);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_19=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
* ----------------------------------------------------------*/
|
||||
if (wait_for_dlllock() != 0) {
|
||||
printf("dlllock did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
if (wait_for_dram_init_complete() != 0) {
|
||||
printf("dram init complete did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||
}
|
||||
#endif /* CONFIG_DDR_DATA_EYE */
|
||||
* Prototypes
|
||||
*-----------------------------------------------------------------------------*/
|
||||
extern int denali_wait_for_dlllock(void);
|
||||
extern void denali_core_search_data_eye(void);
|
||||
|
||||
#if defined(CONFIG_NAND_SPL)
|
||||
/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
|
||||
|
|
@ -428,14 +96,14 @@ long int initdram (int board_type)
|
|||
mtsdram(DDR0_44, 0x00000003);
|
||||
mtsdram(DDR0_02, 0x00000001);
|
||||
|
||||
wait_for_dlllock();
|
||||
denali_wait_for_dlllock();
|
||||
#endif /* #ifndef CONFIG_NAND_U_BOOT */
|
||||
|
||||
#ifdef CONFIG_DDR_DATA_EYE
|
||||
/* -----------------------------------------------------------+
|
||||
* Perform data eye search if requested.
|
||||
* ----------------------------------------------------------*/
|
||||
denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
|
||||
denali_core_search_data_eye();
|
||||
#endif
|
||||
|
||||
return (CFG_MBYTES_SDRAM << 20);
|
||||
|
|
|
|||
|
|
@ -1,505 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SPD_SDRAM_DENALI_H_
|
||||
#define _SPD_SDRAM_DENALI_H_
|
||||
|
||||
#define ppcMsync sync
|
||||
#define ppcMbar eieio
|
||||
|
||||
/* General definitions */
|
||||
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
|
||||
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
|
||||
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
|
||||
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
|
||||
#define MAXRANKS 2 /* 2 ranks maximum */
|
||||
|
||||
/* Supported PLB Frequencies */
|
||||
#define PLB_FREQ_133MHZ 133333333
|
||||
#define PLB_FREQ_152MHZ 152000000
|
||||
#define PLB_FREQ_160MHZ 160000000
|
||||
#define PLB_FREQ_166MHZ 166666666
|
||||
|
||||
/* Denali Core Registers */
|
||||
#define SDRAM_DCR_BASE 0x10
|
||||
|
||||
#define DDR_DCR_BASE 0x10
|
||||
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
|
||||
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Values for ddrcfga register - indirect addressing of these regs
|
||||
+-----------------------------------------------------------------------------*/
|
||||
|
||||
#define DDR0_00 0x00
|
||||
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
|
||||
#define DDR0_00_INT_ACK_ALL 0x7F000000
|
||||
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
/* Status */
|
||||
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
|
||||
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT0 0x00010000
|
||||
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT1 0x00020000
|
||||
/* Bit2. Single correctable ECC event detected */
|
||||
#define DDR0_00_INT_STATUS_BIT2 0x00040000
|
||||
/* Bit3. Multiple correctable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT3 0x00080000
|
||||
/* Bit4. Single uncorrectable ECC event detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT4 0x00100000
|
||||
/* Bit5. Multiple uncorrectable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT5 0x00200000
|
||||
/* Bit6. DRAM initialization complete. */
|
||||
#define DDR0_00_INT_STATUS_BIT6 0x00400000
|
||||
/* Bit7. Logical OR of all lower bits. */
|
||||
#define DDR0_00_INT_STATUS_BIT7 0x00800000
|
||||
|
||||
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
|
||||
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
|
||||
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
#define DDR0_01 0x01
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_01_INT_MASK_MASK 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
|
||||
|
||||
#define DDR0_02 0x02
|
||||
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
|
||||
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
|
||||
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
|
||||
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
|
||||
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
|
||||
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_02_START_MASK 0x00000001
|
||||
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
#define DDR0_02_START_OFF 0x00000000
|
||||
#define DDR0_02_START_ON 0x00000001
|
||||
|
||||
#define DDR0_03 0x03
|
||||
#define DDR0_03_BSTLEN_MASK 0x07000000
|
||||
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_03_CASLAT_MASK 0x00070000
|
||||
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
|
||||
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_03_INITAREF_MASK 0x0000000F
|
||||
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_04 0x04
|
||||
#define DDR0_04_TRC_MASK 0x1F000000
|
||||
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_04_TRRD_MASK 0x00070000
|
||||
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_04_TRTP_MASK 0x00000700
|
||||
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
|
||||
#define DDR0_05 0x05
|
||||
#define DDR0_05_TMRD_MASK 0x1F000000
|
||||
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_05_TEMRS_MASK 0x00070000
|
||||
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_05_TRP_MASK 0x00000F00
|
||||
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
|
||||
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#define DDR0_06 0x06
|
||||
#define DDR0_06_WRITEINTERP_MASK 0x01000000
|
||||
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_06_TWTR_MASK 0x00070000
|
||||
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_06_TDLL_MASK 0x0000FF00
|
||||
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_06_TRFC_MASK 0x0000007F
|
||||
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_07 0x07
|
||||
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
|
||||
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_07_TFAW_MASK 0x001F0000
|
||||
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_07_AREFRESH_MASK 0x00000001
|
||||
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_08 0x08
|
||||
#define DDR0_08_WRLAT_MASK 0x07000000
|
||||
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_08_TCPD_MASK 0x00FF0000
|
||||
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_08_DQS_N_EN_MASK 0x00000100
|
||||
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
|
||||
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_09 0x09
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_09_RTT_0_MASK 0x00030000
|
||||
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
|
||||
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_10 0x0A
|
||||
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
|
||||
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_10_CS_MAP_MASK 0x00000300
|
||||
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
|
||||
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
|
||||
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
|
||||
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
|
||||
|
||||
#define DDR0_11 0x0B
|
||||
#define DDR0_11_SREFRESH_MASK 0x01000000
|
||||
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_11_TXSNR_MASK 0x00FF0000
|
||||
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_11_TXSR_MASK 0x0000FF00
|
||||
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
|
||||
#define DDR0_12 0x0C
|
||||
#define DDR0_12_TCKE_MASK 0x0000007
|
||||
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
|
||||
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
|
||||
|
||||
#define DDR0_13 0x0D
|
||||
|
||||
#define DDR0_14 0x0E
|
||||
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
|
||||
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_14_REDUC_MASK 0x00010000
|
||||
#define DDR0_14_REDUC_64BITS 0x00000000
|
||||
#define DDR0_14_REDUC_32BITS 0x00010000
|
||||
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
|
||||
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
|
||||
#define DDR0_15 0x0F
|
||||
|
||||
#define DDR0_16 0x10
|
||||
|
||||
#define DDR0_17 0x11
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
|
||||
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
|
||||
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
|
||||
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
|
||||
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
|
||||
#define DDR0_18 0x12
|
||||
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_19 0x13
|
||||
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_20 0x14
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_21 0x15
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_22 0x16
|
||||
/* ECC */
|
||||
#define DDR0_22_CTRL_RAW_MASK 0x03000000
|
||||
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
|
||||
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
|
||||
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
|
||||
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
|
||||
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
|
||||
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
#define DDR0_23 0x17
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
|
||||
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
|
||||
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
|
||||
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_24 0x18
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
|
||||
|
||||
#define DDR0_25 0x19
|
||||
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
|
||||
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||
|
||||
#define DDR0_26 0x1A
|
||||
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
|
||||
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_26_TREF_MASK 0x00003FFF
|
||||
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||
|
||||
#define DDR0_27 0x1B
|
||||
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_27_TINIT_MASK 0x0000FFFF
|
||||
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_28 0x1C
|
||||
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
|
||||
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||
|
||||
#define DDR0_29 0x1D
|
||||
|
||||
#define DDR0_30 0x1E
|
||||
|
||||
#define DDR0_31 0x1F
|
||||
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
|
||||
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_32 0x20
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_33 0x21
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_34 0x22
|
||||
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_35 0x23
|
||||
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_36 0x24
|
||||
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_37 0x25
|
||||
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_38 0x26
|
||||
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_39 0x27
|
||||
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_40 0x28
|
||||
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_41 0x29
|
||||
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_42 0x2A
|
||||
#define DDR0_42_ADDR_PINS_MASK 0x07000000
|
||||
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
|
||||
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_43 0x2B
|
||||
#define DDR0_43_TWR_MASK 0x07000000
|
||||
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_43_APREBIT_MASK 0x000F0000
|
||||
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
|
||||
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
|
||||
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_44 0x2C
|
||||
#define DDR0_44_TRCD_MASK 0x000000FF
|
||||
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#endif /* _SPD_SDRAM_DENALI_H_ */
|
||||
|
|
@ -26,6 +26,7 @@
|
|||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <ppc440.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
|
|
@ -44,36 +45,6 @@ int board_early_init_f(void)
|
|||
mtdcr(ebccfga, xbcfg);
|
||||
mtdcr(ebccfgd, 0xb8400000);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the GPIO pins
|
||||
*-------------------------------------------------------------------*/
|
||||
/* test-only: take GPIO init from pcs440ep ???? in config file */
|
||||
out_be32((u32 *) GPIO0_OR, 0x00000000);
|
||||
out_be32((u32 *) GPIO0_TCR, 0x0000000f);
|
||||
out_be32((u32 *) GPIO0_OSRL, 0x50015400);
|
||||
out_be32((u32 *) GPIO0_OSRH, 0x550050aa);
|
||||
out_be32((u32 *) GPIO0_TSRL, 0x50015400);
|
||||
out_be32((u32 *) GPIO0_TSRH, 0x55005000);
|
||||
out_be32((u32 *) GPIO0_ISR1L, 0x50000000);
|
||||
out_be32((u32 *) GPIO0_ISR1H, 0x00000000);
|
||||
out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
|
||||
out_be32((u32 *) GPIO0_ISR2H, 0x00000100);
|
||||
out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
|
||||
out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
|
||||
|
||||
out_be32((u32 *) GPIO1_OR, 0x00000000);
|
||||
out_be32((u32 *) GPIO1_TCR, 0xc2000000);
|
||||
out_be32((u32 *) GPIO1_OSRL, 0x5c280000);
|
||||
out_be32((u32 *) GPIO1_OSRH, 0x00000000);
|
||||
out_be32((u32 *) GPIO1_TSRL, 0x0c000000);
|
||||
out_be32((u32 *) GPIO1_TSRH, 0x00000000);
|
||||
out_be32((u32 *) GPIO1_ISR1L, 0x00005550);
|
||||
out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
|
||||
out_be32((u32 *) GPIO1_ISR2L, 0x00050000);
|
||||
out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
|
||||
out_be32((u32 *) GPIO1_ISR3L, 0x01400000);
|
||||
out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -37,41 +37,41 @@ int lcd_depth;
|
|||
unsigned char *glob_lcd_reg;
|
||||
unsigned char *glob_lcd_mem;
|
||||
|
||||
#ifdef CFG_LCD_ENDIAN
|
||||
#if defined(CFG_LCD_ENDIAN)
|
||||
void lcd_setup(int lcd, int config)
|
||||
{
|
||||
if (lcd == 0) {
|
||||
/*
|
||||
* Set endianess and reset lcd controller 0 (small)
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
|
||||
udelay(10); /* wait 10us */
|
||||
if (config == 1)
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
||||
else
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
||||
udelay(10); /* wait 10us */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
|
||||
} else {
|
||||
/*
|
||||
* Set endianess and reset lcd controller 1 (big)
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
|
||||
udelay(10); /* wait 10us */
|
||||
if (config == 1)
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
||||
else
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
||||
udelay(10); /* wait 10us */
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
|
||||
}
|
||||
|
||||
/*
|
||||
* CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
|
||||
*/
|
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
|
||||
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
|
||||
}
|
||||
#endif /* #ifdef CFG_LCD_ENDIAN */
|
||||
#endif /* CFG_LCD_ENDIAN */
|
||||
|
||||
|
||||
void lcd_bmp(uchar *logo_bmp)
|
||||
|
|
@ -93,7 +93,6 @@ void lcd_bmp(uchar *logo_bmp)
|
|||
* Check for bmp mark 'BM'
|
||||
*/
|
||||
if (*(ushort *)logo_bmp != 0x424d) {
|
||||
|
||||
/*
|
||||
* Decompress bmp image
|
||||
*/
|
||||
|
|
@ -202,11 +201,10 @@ void lcd_bmp(uchar *logo_bmp)
|
|||
}
|
||||
}
|
||||
} else {
|
||||
for (x=0; x<line_size; x++) {
|
||||
for (x = 0; x < line_size; x++)
|
||||
*ptr++ = *bmp++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if ((dst != NULL) && (dst != (uchar *)logo_bmp))
|
||||
free(dst);
|
||||
|
|
@ -296,7 +294,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
|||
lcd_bmp(logo_bmp);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_VIDEO_SM501
|
||||
#if defined(CONFIG_VIDEO_SM501)
|
||||
int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong addr;
|
||||
|
|
|
|||
|
|
@ -33,343 +33,9 @@
|
|||
#include <asm/io.h>
|
||||
#include <ppc440.h>
|
||||
|
||||
#include "sdram.h"
|
||||
extern int denali_wait_for_dlllock(void);
|
||||
extern void denali_core_search_data_eye(void);
|
||||
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
|
||||
defined(CONFIG_DDR_DATA_EYE)
|
||||
/*-----------------------------------------------------------------------------+
|
||||
* wait_for_dlllock.
|
||||
+----------------------------------------------------------------------------*/
|
||||
static int wait_for_dlllock(void)
|
||||
{
|
||||
unsigned long val;
|
||||
int wait = 0;
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = DDR0_17_DLLLOCKREG_UNLOCKED;
|
||||
|
||||
while (wait != 0xffff) {
|
||||
val = mfdcr(ddrcfgd);
|
||||
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
|
||||
/* dlllockreg bit on */
|
||||
return 0;
|
||||
else
|
||||
wait++;
|
||||
}
|
||||
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
|
||||
debug("Waiting for dlllockreg bit to raise\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DDR_DATA_EYE)
|
||||
/*-----------------------------------------------------------------------------+
|
||||
* wait_for_dram_init_complete.
|
||||
+----------------------------------------------------------------------------*/
|
||||
int wait_for_dram_init_complete(void)
|
||||
{
|
||||
unsigned long val;
|
||||
int wait = 0;
|
||||
|
||||
/* --------------------------------------------------------------+
|
||||
* Wait for 'DRAM initialization complete' bit in status register
|
||||
* -------------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_00);
|
||||
|
||||
while (wait != 0xffff) {
|
||||
val = mfdcr(ddrcfgd);
|
||||
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
|
||||
/* 'DRAM initialization complete' bit */
|
||||
return 0;
|
||||
else
|
||||
wait++;
|
||||
}
|
||||
|
||||
debug("DRAM initialization complete bit in status register did not rise\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
#define NUM_TRIES 64
|
||||
#define NUM_READS 10
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
* denali_core_search_data_eye.
|
||||
+----------------------------------------------------------------------------*/
|
||||
void denali_core_search_data_eye(unsigned long memory_size)
|
||||
{
|
||||
int k, j;
|
||||
u32 val;
|
||||
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
|
||||
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
|
||||
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
|
||||
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
|
||||
volatile u32 *ram_pointer;
|
||||
u32 test[NUM_TRIES] = {
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
|
||||
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
|
||||
|
||||
ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
|
||||
|
||||
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
|
||||
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* De-assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'wr_dqs_shift'
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_09);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||
* ----------------------------------------------------------*/
|
||||
dqs_out_shift = wr_dqs_shift + 32;
|
||||
mtdcr(ddrcfga, DDR0_22);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
passing_cases = 0;
|
||||
|
||||
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
|
||||
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dll_dqs_delay_X'.
|
||||
* ----------------------------------------------------------*/
|
||||
/* dll_dqs_delay_0 */
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||
mtdcr(ddrcfga, DDR0_18);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||
mtdcr(ddrcfga, DDR0_19);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
* ----------------------------------------------------------*/
|
||||
if (wait_for_dlllock() != 0) {
|
||||
printf("dlllock did not occur !!!\n");
|
||||
printf("denali_core_search_data_eye!!!\n");
|
||||
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
|
||||
wr_dqs_shift, dll_dqs_delay_X);
|
||||
hang();
|
||||
}
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
if (wait_for_dram_init_complete() != 0) {
|
||||
printf("dram init complete did not occur !!!\n");
|
||||
printf("denali_core_search_data_eye!!!\n");
|
||||
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
|
||||
wr_dqs_shift, dll_dqs_delay_X);
|
||||
hang();
|
||||
}
|
||||
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||
|
||||
/* write values */
|
||||
for (j=0; j<NUM_TRIES; j++) {
|
||||
ram_pointer[j] = test[j];
|
||||
|
||||
/* clear any cache at ram location */
|
||||
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
|
||||
}
|
||||
|
||||
/* read values back */
|
||||
for (j=0; j<NUM_TRIES; j++) {
|
||||
for (k=0; k<NUM_READS; k++) {
|
||||
/* clear any cache at ram location */
|
||||
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
|
||||
|
||||
if (ram_pointer[j] != test[j])
|
||||
break;
|
||||
}
|
||||
|
||||
/* read error */
|
||||
if (k != NUM_READS)
|
||||
break;
|
||||
}
|
||||
|
||||
/* See if the dll_dqs_delay_X value passed.*/
|
||||
if (j < NUM_TRIES) {
|
||||
/* Failed */
|
||||
passing_cases = 0;
|
||||
/* break; */
|
||||
} else {
|
||||
/* Passed */
|
||||
if (passing_cases == 0)
|
||||
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
|
||||
passing_cases++;
|
||||
if (passing_cases >= max_passing_cases) {
|
||||
max_passing_cases = passing_cases;
|
||||
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
|
||||
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
|
||||
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
|
||||
}
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* De-assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
|
||||
|
||||
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Largest passing window is now detected.
|
||||
* ----------------------------------------------------------*/
|
||||
|
||||
/* Compute dll_dqs_delay_X value */
|
||||
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
|
||||
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
|
||||
|
||||
debug("DQS calibration - Window detected:\n");
|
||||
debug("max_passing_cases = %d\n", max_passing_cases);
|
||||
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
|
||||
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
|
||||
debug("dll_dqs_delay_X window = %d - %d\n",
|
||||
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* De-assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'wr_dqs_shift'
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_09);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_09=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||
* ----------------------------------------------------------*/
|
||||
dqs_out_shift = wr_dqs_shift + 32;
|
||||
mtdcr(ddrcfga, DDR0_22);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_22=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Set 'dll_dqs_delay_X'.
|
||||
* ----------------------------------------------------------*/
|
||||
/* dll_dqs_delay_0 */
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_17=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||
mtdcr(ddrcfga, DDR0_18);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_18=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||
mtdcr(ddrcfga, DDR0_19);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_19=0x%08lx\n", val);
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Assert 'start' parameter.
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
* ----------------------------------------------------------*/
|
||||
if (wait_for_dlllock() != 0) {
|
||||
printf("dlllock did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
if (wait_for_dram_init_complete() != 0) {
|
||||
printf("dram init complete did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||
}
|
||||
#endif /* CONFIG_DDR_DATA_EYE */
|
||||
|
||||
#if defined(CONFIG_NAND_SPL)
|
||||
/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
|
||||
|
|
@ -428,14 +94,14 @@ long int initdram (int board_type)
|
|||
mtsdram(DDR0_44, 0x00000003);
|
||||
mtsdram(DDR0_02, 0x00000001);
|
||||
|
||||
wait_for_dlllock();
|
||||
denali_wait_for_dlllock();
|
||||
#endif /* #ifndef CONFIG_NAND_U_BOOT */
|
||||
|
||||
#ifdef CONFIG_DDR_DATA_EYE
|
||||
/* -----------------------------------------------------------+
|
||||
* Perform data eye search if requested.
|
||||
* ----------------------------------------------------------*/
|
||||
denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
|
||||
denali_core_search_data_eye();
|
||||
#endif
|
||||
|
||||
return (CFG_MBYTES_SDRAM << 20);
|
||||
|
|
|
|||
|
|
@ -1,505 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SPD_SDRAM_DENALI_H_
|
||||
#define _SPD_SDRAM_DENALI_H_
|
||||
|
||||
#define ppcMsync sync
|
||||
#define ppcMbar eieio
|
||||
|
||||
/* General definitions */
|
||||
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
|
||||
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
|
||||
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
|
||||
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
|
||||
#define MAXRANKS 2 /* 2 ranks maximum */
|
||||
|
||||
/* Supported PLB Frequencies */
|
||||
#define PLB_FREQ_133MHZ 133333333
|
||||
#define PLB_FREQ_152MHZ 152000000
|
||||
#define PLB_FREQ_160MHZ 160000000
|
||||
#define PLB_FREQ_166MHZ 166666666
|
||||
|
||||
/* Denali Core Registers */
|
||||
#define SDRAM_DCR_BASE 0x10
|
||||
|
||||
#define DDR_DCR_BASE 0x10
|
||||
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
|
||||
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Values for ddrcfga register - indirect addressing of these regs
|
||||
+-----------------------------------------------------------------------------*/
|
||||
|
||||
#define DDR0_00 0x00
|
||||
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
|
||||
#define DDR0_00_INT_ACK_ALL 0x7F000000
|
||||
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
/* Status */
|
||||
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
|
||||
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT0 0x00010000
|
||||
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT1 0x00020000
|
||||
/* Bit2. Single correctable ECC event detected */
|
||||
#define DDR0_00_INT_STATUS_BIT2 0x00040000
|
||||
/* Bit3. Multiple correctable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT3 0x00080000
|
||||
/* Bit4. Single uncorrectable ECC event detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT4 0x00100000
|
||||
/* Bit5. Multiple uncorrectable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT5 0x00200000
|
||||
/* Bit6. DRAM initialization complete. */
|
||||
#define DDR0_00_INT_STATUS_BIT6 0x00400000
|
||||
/* Bit7. Logical OR of all lower bits. */
|
||||
#define DDR0_00_INT_STATUS_BIT7 0x00800000
|
||||
|
||||
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
|
||||
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
|
||||
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
#define DDR0_01 0x01
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_01_INT_MASK_MASK 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
|
||||
|
||||
#define DDR0_02 0x02
|
||||
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
|
||||
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
|
||||
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
|
||||
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
|
||||
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
|
||||
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_02_START_MASK 0x00000001
|
||||
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
#define DDR0_02_START_OFF 0x00000000
|
||||
#define DDR0_02_START_ON 0x00000001
|
||||
|
||||
#define DDR0_03 0x03
|
||||
#define DDR0_03_BSTLEN_MASK 0x07000000
|
||||
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_03_CASLAT_MASK 0x00070000
|
||||
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
|
||||
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_03_INITAREF_MASK 0x0000000F
|
||||
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_04 0x04
|
||||
#define DDR0_04_TRC_MASK 0x1F000000
|
||||
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_04_TRRD_MASK 0x00070000
|
||||
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_04_TRTP_MASK 0x00000700
|
||||
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
|
||||
#define DDR0_05 0x05
|
||||
#define DDR0_05_TMRD_MASK 0x1F000000
|
||||
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_05_TEMRS_MASK 0x00070000
|
||||
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_05_TRP_MASK 0x00000F00
|
||||
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
|
||||
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#define DDR0_06 0x06
|
||||
#define DDR0_06_WRITEINTERP_MASK 0x01000000
|
||||
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_06_TWTR_MASK 0x00070000
|
||||
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_06_TDLL_MASK 0x0000FF00
|
||||
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_06_TRFC_MASK 0x0000007F
|
||||
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_07 0x07
|
||||
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
|
||||
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_07_TFAW_MASK 0x001F0000
|
||||
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_07_AREFRESH_MASK 0x00000001
|
||||
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_08 0x08
|
||||
#define DDR0_08_WRLAT_MASK 0x07000000
|
||||
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_08_TCPD_MASK 0x00FF0000
|
||||
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_08_DQS_N_EN_MASK 0x00000100
|
||||
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
|
||||
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_09 0x09
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_09_RTT_0_MASK 0x00030000
|
||||
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
|
||||
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_10 0x0A
|
||||
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
|
||||
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_10_CS_MAP_MASK 0x00000300
|
||||
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
|
||||
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
|
||||
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
|
||||
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
|
||||
|
||||
#define DDR0_11 0x0B
|
||||
#define DDR0_11_SREFRESH_MASK 0x01000000
|
||||
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_11_TXSNR_MASK 0x00FF0000
|
||||
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_11_TXSR_MASK 0x0000FF00
|
||||
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
|
||||
#define DDR0_12 0x0C
|
||||
#define DDR0_12_TCKE_MASK 0x0000007
|
||||
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
|
||||
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
|
||||
|
||||
#define DDR0_13 0x0D
|
||||
|
||||
#define DDR0_14 0x0E
|
||||
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
|
||||
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_14_REDUC_MASK 0x00010000
|
||||
#define DDR0_14_REDUC_64BITS 0x00000000
|
||||
#define DDR0_14_REDUC_32BITS 0x00010000
|
||||
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
|
||||
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
|
||||
#define DDR0_15 0x0F
|
||||
|
||||
#define DDR0_16 0x10
|
||||
|
||||
#define DDR0_17 0x11
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
|
||||
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
|
||||
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
|
||||
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
|
||||
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
|
||||
#define DDR0_18 0x12
|
||||
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_19 0x13
|
||||
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_20 0x14
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_21 0x15
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_22 0x16
|
||||
/* ECC */
|
||||
#define DDR0_22_CTRL_RAW_MASK 0x03000000
|
||||
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
|
||||
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
|
||||
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
|
||||
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
|
||||
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
|
||||
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
#define DDR0_23 0x17
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
|
||||
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
|
||||
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
|
||||
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_24 0x18
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
|
||||
|
||||
#define DDR0_25 0x19
|
||||
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
|
||||
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||
|
||||
#define DDR0_26 0x1A
|
||||
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
|
||||
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_26_TREF_MASK 0x00003FFF
|
||||
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||
|
||||
#define DDR0_27 0x1B
|
||||
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_27_TINIT_MASK 0x0000FFFF
|
||||
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_28 0x1C
|
||||
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
|
||||
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||
|
||||
#define DDR0_29 0x1D
|
||||
|
||||
#define DDR0_30 0x1E
|
||||
|
||||
#define DDR0_31 0x1F
|
||||
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
|
||||
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_32 0x20
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_33 0x21
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_34 0x22
|
||||
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_35 0x23
|
||||
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_36 0x24
|
||||
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_37 0x25
|
||||
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_38 0x26
|
||||
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_39 0x27
|
||||
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_40 0x28
|
||||
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_41 0x29
|
||||
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_42 0x2A
|
||||
#define DDR0_42_ADDR_PINS_MASK 0x07000000
|
||||
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
|
||||
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_43 0x2B
|
||||
#define DDR0_43_TWR_MASK 0x07000000
|
||||
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_43_APREBIT_MASK 0x000F0000
|
||||
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
|
||||
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
|
||||
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_44 0x2C
|
||||
#define DDR0_44_TRCD_MASK 0x000000FF
|
||||
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#endif /* _SPD_SDRAM_DENALI_H_ */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* (C) Copyright 2007-2008
|
||||
* Larry Johnson, lrj@acm.org
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
|
|
@ -26,6 +26,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm-ppc/io.h>
|
||||
#include <i2c.h>
|
||||
|
|
@ -40,109 +41,12 @@ ulong flash_get_size(ulong base, int banknum);
|
|||
int board_early_init_f(void)
|
||||
{
|
||||
u32 sdr0_pfc1, sdr0_pfc2;
|
||||
u32 gpio0_ir;
|
||||
u32 reg;
|
||||
int eth;
|
||||
|
||||
mtdcr(ebccfga, xbcfg);
|
||||
mtdcr(ebccfgd, 0xb8400000);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the GPIO pins
|
||||
*
|
||||
* Korat GPIO usage:
|
||||
*
|
||||
* Init.
|
||||
* Pin Source I/O value Function
|
||||
* ------ ------ --- ----- ---------------------------------
|
||||
* GPIO00 Alt1 I/O x PerAddr07
|
||||
* GPIO01 Alt1 I/O x PerAddr06
|
||||
* GPIO02 Alt1 I/O x PerAddr05
|
||||
* GPIO03 GPIO x x GPIO03 to expansion bus connector
|
||||
* GPIO04 GPIO x x GPIO04 to expansion bus connector
|
||||
* GPIO05 GPIO x x GPIO05 to expansion bus connector
|
||||
* GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
|
||||
* GPIO07 Alt1 O x PerCS2 (CPLD)
|
||||
* GPIO08 Alt1 O x PerCS3 to expansion bus connector
|
||||
* GPIO09 Alt1 O x PerCS4 to expansion bus connector
|
||||
* GPIO10 Alt1 O x PerCS5 to expansion bus connector
|
||||
* GPIO11 Alt1 I x PerErr
|
||||
* GPIO12 GPIO O 0 ATMega !Reset
|
||||
* GPIO13 GPIO O 1 SPI Atmega !SS
|
||||
* GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
|
||||
* GPIO15 GPIO O 0 CPU Run LED !On
|
||||
* GPIO16 Alt1 O x GMC1TxD0
|
||||
* GPIO17 Alt1 O x GMC1TxD1
|
||||
* GPIO18 Alt1 O x GMC1TxD2
|
||||
* GPIO19 Alt1 O x GMC1TxD3
|
||||
* GPIO20 Alt1 O x RejectPkt0
|
||||
* GPIO21 Alt1 O x RejectPkt1
|
||||
* GPIO22 GPIO I x PGOOD_DDR
|
||||
* GPIO23 Alt1 O x SCPD0
|
||||
* GPIO24 Alt1 O x GMC0TxD2
|
||||
* GPIO25 Alt1 O x GMC0TxD3
|
||||
* GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
|
||||
* GPIO27 GPIO O 0 PHY #0 1000BASE-X
|
||||
* GPIO28 GPIO O 0 PHY #1 1000BASE-X
|
||||
* GPIO29 GPIO I x Test jumper !Present
|
||||
* GPIO30 GPIO I x SFP module #0 !Present
|
||||
* GPIO31 GPIO I x SFP module #1 !Present
|
||||
*
|
||||
* GPIO32 GPIO O 1 SFP module #0 Tx !Enable
|
||||
* GPIO33 GPIO O 1 SFP module #1 Tx !Enable
|
||||
* GPIO34 Alt2 I x !UART1_CTS
|
||||
* GPIO35 Alt2 O x !UART1_RTS
|
||||
* GPIO36 Alt1 I x !UART0_CTS
|
||||
* GPIO37 Alt1 O x !UART0_RTS
|
||||
* GPIO38 Alt2 O x UART1_Tx
|
||||
* GPIO39 Alt2 I x UART1_Rx
|
||||
* GPIO40 Alt1 I x IRQ0 (Ethernet 0)
|
||||
* GPIO41 Alt1 I x IRQ1 (Ethernet 1)
|
||||
* GPIO42 Alt1 I x IRQ2 (PCI interrupt)
|
||||
* GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
|
||||
* GPIO44 xxxx x x (grounded through pulldown)
|
||||
* GPIO45 GPIO O 0 PHY #0 Enable
|
||||
* GPIO46 GPIO O 0 PHY #1 Enable
|
||||
* GPIO47 GPIO I x Reset switch !Pressed
|
||||
* GPIO48 GPIO I x Shutdown switch !Pressed
|
||||
* GPIO49 xxxx x x (reserved for trace port)
|
||||
* . . . . .
|
||||
* . . . . .
|
||||
* . . . . .
|
||||
* GPIO63 xxxx x x (reserved for trace port)
|
||||
*-------------------------------------------------------------------*/
|
||||
|
||||
out_be32((u32 *) GPIO0_OR, 0x00060000);
|
||||
out_be32((u32 *) GPIO1_OR, 0xC0000000);
|
||||
|
||||
out_be32((u32 *) GPIO0_OSRL, 0x54055400);
|
||||
out_be32((u32 *) GPIO0_OSRH, 0x55015000);
|
||||
out_be32((u32 *) GPIO1_OSRL, 0x02180000);
|
||||
out_be32((u32 *) GPIO1_OSRH, 0x00000000);
|
||||
|
||||
out_be32((u32 *) GPIO0_TSRL, 0x54055500);
|
||||
out_be32((u32 *) GPIO0_TSRH, 0x00015000);
|
||||
out_be32((u32 *) GPIO1_TSRL, 0x00000000);
|
||||
out_be32((u32 *) GPIO1_TSRH, 0x00000000);
|
||||
|
||||
out_be32((u32 *) GPIO0_TCR, 0x000FF0D8);
|
||||
out_be32((u32 *) GPIO1_TCR, 0xD6060000);
|
||||
|
||||
out_be32((u32 *) GPIO0_ISR1L, 0x54000100);
|
||||
out_be32((u32 *) GPIO0_ISR1H, 0x00500000);
|
||||
out_be32((u32 *) GPIO1_ISR1L, 0x00405500);
|
||||
out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
|
||||
|
||||
out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
|
||||
out_be32((u32 *) GPIO0_ISR2H, 0x00000000);
|
||||
out_be32((u32 *) GPIO1_ISR2L, 0x04010000);
|
||||
out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
|
||||
|
||||
out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
|
||||
out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
|
||||
out_be32((u32 *) GPIO1_ISR3L, 0x00000000);
|
||||
out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
|
|
@ -176,9 +80,8 @@ int board_early_init_f(void)
|
|||
/* Configure the two Ethernet PHYs. For each PHY, configure for fiber
|
||||
* if the SFP module is present, and for copper if it is not present.
|
||||
*/
|
||||
gpio0_ir = in_be32((u32 *) GPIO0_IR);
|
||||
for (eth = 0; eth < 2; ++eth) {
|
||||
if (gpio0_ir & (0x00000001 << (1 - eth))) {
|
||||
if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) {
|
||||
/* SFP module not present: configure PHY for copper. */
|
||||
/* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
|
||||
out_8((u8 *) CFG_CPLD_BASE + 0x06,
|
||||
|
|
@ -187,14 +90,13 @@ int board_early_init_f(void)
|
|||
} else {
|
||||
/* SFP module present: configure PHY for fiber and
|
||||
enable output */
|
||||
out_be32((u32 *) GPIO0_OR, in_be32((u32 *) GPIO0_OR) |
|
||||
(0x00000001 << (4 - eth)));
|
||||
out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) &
|
||||
~(0x00000001 << (31 - eth)));
|
||||
gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1);
|
||||
gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0);
|
||||
}
|
||||
}
|
||||
/* enable Ethernet: set GPIO45 and GPIO46 to 1 */
|
||||
out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) | 0x00060000);
|
||||
gpio_write_bit(CFG_GPIO_PHY0_EN, 1);
|
||||
gpio_write_bit(CFG_GPIO_PHY1_EN, 1);
|
||||
|
||||
/* select Ethernet pins */
|
||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
|
|
@ -525,20 +427,19 @@ int checkboard(void)
|
|||
{
|
||||
char const *const s = getenv("serial#");
|
||||
u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
|
||||
u32 const gpio0_or = in_be32((u32 *) GPIO0_OR);
|
||||
|
||||
printf("Board: Korat, Rev. %X", rev);
|
||||
if (s != NULL)
|
||||
printf(", serial# %s", s);
|
||||
|
||||
printf(", Ethernet PHY 0: ");
|
||||
if (gpio0_or & 0x00000010)
|
||||
if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL))
|
||||
printf("fiber");
|
||||
else
|
||||
printf("copper");
|
||||
|
||||
printf(", PHY 1: ");
|
||||
if (gpio0_or & 0x00000008)
|
||||
if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL))
|
||||
printf("fiber");
|
||||
else
|
||||
printf("copper");
|
||||
|
|
|
|||
|
|
@ -36,8 +36,6 @@
|
|||
#include <asm/io.h>
|
||||
#include <ppc440.h>
|
||||
|
||||
#include "sdram.h"
|
||||
|
||||
/*
|
||||
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
|
||||
* region. Right now the cache should still be disabled in U-Boot because of the
|
||||
|
|
@ -54,8 +52,13 @@
|
|||
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
|
||||
#endif
|
||||
|
||||
void dcbz_area(u32 start_address, u32 num_bytes);
|
||||
void dflush(void);
|
||||
/*-----------------------------------------------------------------------------+
|
||||
* Prototypes
|
||||
*-----------------------------------------------------------------------------*/
|
||||
extern int denali_wait_for_dlllock(void);
|
||||
extern void denali_core_search_data_eye(void);
|
||||
extern void dcbz_area(u32 start_address, u32 num_bytes);
|
||||
extern void dflush(void);
|
||||
|
||||
static u32 is_ecc_enabled(void)
|
||||
{
|
||||
|
|
@ -87,330 +90,6 @@ void board_add_ram_info(int use_default)
|
|||
printf(", CL%d)", val);
|
||||
}
|
||||
|
||||
static int wait_for_dlllock(void)
|
||||
{
|
||||
u32 val;
|
||||
int wait = 0;
|
||||
|
||||
/*
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = DDR0_17_DLLLOCKREG_UNLOCKED;
|
||||
|
||||
while (wait != 0xffff) {
|
||||
val = mfdcr(ddrcfgd);
|
||||
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
|
||||
/* dlllockreg bit on */
|
||||
return 0;
|
||||
else
|
||||
wait++;
|
||||
}
|
||||
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
|
||||
debug("Waiting for dlllockreg bit to raise\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DDR_DATA_EYE)
|
||||
int wait_for_dram_init_complete(void)
|
||||
{
|
||||
u32 val;
|
||||
int wait = 0;
|
||||
|
||||
/*
|
||||
* Wait for 'DRAM initialization complete' bit in status register
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_00);
|
||||
|
||||
while (wait != 0xffff) {
|
||||
val = mfdcr(ddrcfgd);
|
||||
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
|
||||
/* 'DRAM initialization complete' bit */
|
||||
return 0;
|
||||
else
|
||||
wait++;
|
||||
}
|
||||
|
||||
debug("DRAM initialization complete bit in status register did not rise\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
#define NUM_TRIES 64
|
||||
#define NUM_READS 10
|
||||
|
||||
void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
|
||||
{
|
||||
int k, j;
|
||||
u32 val;
|
||||
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
|
||||
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
|
||||
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
|
||||
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
|
||||
volatile u32 *ram_pointer;
|
||||
u32 test[NUM_TRIES] = {
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
|
||||
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
|
||||
|
||||
ram_pointer = (volatile u32 *)start_addr;
|
||||
|
||||
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
|
||||
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
|
||||
|
||||
/*
|
||||
* De-assert 'start' parameter.
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/*
|
||||
* Set 'wr_dqs_shift'
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_09);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/*
|
||||
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||
*/
|
||||
dqs_out_shift = wr_dqs_shift + 32;
|
||||
mtdcr(ddrcfga, DDR0_22);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
passing_cases = 0;
|
||||
|
||||
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
|
||||
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
|
||||
/*
|
||||
* Set 'dll_dqs_delay_X'.
|
||||
*/
|
||||
/* dll_dqs_delay_0 */
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||
mtdcr(ddrcfga, DDR0_18);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||
mtdcr(ddrcfga, DDR0_19);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/*
|
||||
* Assert 'start' parameter.
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/*
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
*/
|
||||
if (wait_for_dlllock() != 0) {
|
||||
printf("dlllock did not occur !!!\n");
|
||||
printf("denali_core_search_data_eye!!!\n");
|
||||
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
|
||||
wr_dqs_shift, dll_dqs_delay_X);
|
||||
hang();
|
||||
}
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
if (wait_for_dram_init_complete() != 0) {
|
||||
printf("dram init complete did not occur !!!\n");
|
||||
printf("denali_core_search_data_eye!!!\n");
|
||||
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
|
||||
wr_dqs_shift, dll_dqs_delay_X);
|
||||
hang();
|
||||
}
|
||||
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||
|
||||
/* write values */
|
||||
for (j=0; j<NUM_TRIES; j++) {
|
||||
ram_pointer[j] = test[j];
|
||||
|
||||
/* clear any cache at ram location */
|
||||
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
|
||||
}
|
||||
|
||||
/* read values back */
|
||||
for (j=0; j<NUM_TRIES; j++) {
|
||||
for (k=0; k<NUM_READS; k++) {
|
||||
/* clear any cache at ram location */
|
||||
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
|
||||
|
||||
if (ram_pointer[j] != test[j])
|
||||
break;
|
||||
}
|
||||
|
||||
/* read error */
|
||||
if (k != NUM_READS)
|
||||
break;
|
||||
}
|
||||
|
||||
/* See if the dll_dqs_delay_X value passed.*/
|
||||
if (j < NUM_TRIES) {
|
||||
/* Failed */
|
||||
passing_cases = 0;
|
||||
/* break; */
|
||||
} else {
|
||||
/* Passed */
|
||||
if (passing_cases == 0)
|
||||
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
|
||||
passing_cases++;
|
||||
if (passing_cases >= max_passing_cases) {
|
||||
max_passing_cases = passing_cases;
|
||||
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
|
||||
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
|
||||
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* De-assert 'start' parameter.
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
|
||||
|
||||
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
|
||||
|
||||
/*
|
||||
* Largest passing window is now detected.
|
||||
*/
|
||||
|
||||
/* Compute dll_dqs_delay_X value */
|
||||
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
|
||||
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
|
||||
|
||||
debug("DQS calibration - Window detected:\n");
|
||||
debug("max_passing_cases = %d\n", max_passing_cases);
|
||||
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
|
||||
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
|
||||
debug("dll_dqs_delay_X window = %d - %d\n",
|
||||
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
|
||||
|
||||
/*
|
||||
* De-assert 'start' parameter.
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
/*
|
||||
* Set 'wr_dqs_shift'
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_09);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_09=0x%08lx\n", val);
|
||||
|
||||
/*
|
||||
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||
*/
|
||||
dqs_out_shift = wr_dqs_shift + 32;
|
||||
mtdcr(ddrcfga, DDR0_22);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_22=0x%08lx\n", val);
|
||||
|
||||
/*
|
||||
* Set 'dll_dqs_delay_X'.
|
||||
*/
|
||||
/* dll_dqs_delay_0 */
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_17=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||
mtdcr(ddrcfga, DDR0_18);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_18=0x%08lx\n", val);
|
||||
|
||||
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||
mtdcr(ddrcfga, DDR0_19);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||
mtdcr(ddrcfgd, val);
|
||||
debug("DDR0_19=0x%08lx\n", val);
|
||||
|
||||
/*
|
||||
* Assert 'start' parameter.
|
||||
*/
|
||||
mtdcr(ddrcfga, DDR0_02);
|
||||
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||
mtdcr(ddrcfgd, val);
|
||||
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
/*
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
*/
|
||||
if (wait_for_dlllock() != 0) {
|
||||
printf("dlllock did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
ppcMsync();
|
||||
ppcMbar();
|
||||
|
||||
if (wait_for_dram_init_complete() != 0) {
|
||||
printf("dram init complete did not occur !!!\n");
|
||||
hang();
|
||||
}
|
||||
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||
}
|
||||
#endif /* CONFIG_DDR_DATA_EYE */
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
static void wait_ddr_idle(void)
|
||||
{
|
||||
|
|
@ -610,12 +289,23 @@ long int initdram (int board_type)
|
|||
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
|
||||
#endif
|
||||
|
||||
wait_for_dlllock();
|
||||
denali_wait_for_dlllock();
|
||||
|
||||
#if defined(CONFIG_DDR_DATA_EYE)
|
||||
/* -----------------------------------------------------------+
|
||||
* Perform data eye search if requested.
|
||||
* ----------------------------------------------------------*/
|
||||
program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
|
||||
TLB_WORD2_I_ENABLE);
|
||||
denali_core_search_data_eye();
|
||||
remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Program tlb entries for this size (dynamic)
|
||||
*/
|
||||
program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
|
||||
program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
|
||||
MY_TLB_WORD2_I_ENABLE);
|
||||
|
||||
/*
|
||||
* Setup 2nd TLB with same physical address but different virtual address
|
||||
|
|
@ -623,13 +313,6 @@ long int initdram (int board_type)
|
|||
*/
|
||||
program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
|
||||
|
||||
#ifdef CONFIG_DDR_DATA_EYE
|
||||
/*
|
||||
* Perform data eye search if requested.
|
||||
*/
|
||||
denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
/*
|
||||
* If ECC is enabled, initialize the parity bits.
|
||||
|
|
|
|||
|
|
@ -1,505 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SPD_SDRAM_DENALI_H_
|
||||
#define _SPD_SDRAM_DENALI_H_
|
||||
|
||||
#define ppcMsync sync
|
||||
#define ppcMbar eieio
|
||||
|
||||
/* General definitions */
|
||||
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
|
||||
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
|
||||
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
|
||||
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
|
||||
#define MAXRANKS 2 /* 2 ranks maximum */
|
||||
|
||||
/* Supported PLB Frequencies */
|
||||
#define PLB_FREQ_133MHZ 133333333
|
||||
#define PLB_FREQ_152MHZ 152000000
|
||||
#define PLB_FREQ_160MHZ 160000000
|
||||
#define PLB_FREQ_166MHZ 166666666
|
||||
|
||||
/* Denali Core Registers */
|
||||
#define SDRAM_DCR_BASE 0x10
|
||||
|
||||
#define DDR_DCR_BASE 0x10
|
||||
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
|
||||
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Values for ddrcfga register - indirect addressing of these regs
|
||||
+-----------------------------------------------------------------------------*/
|
||||
|
||||
#define DDR0_00 0x00
|
||||
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
|
||||
#define DDR0_00_INT_ACK_ALL 0x7F000000
|
||||
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
/* Status */
|
||||
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
|
||||
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT0 0x00010000
|
||||
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT1 0x00020000
|
||||
/* Bit2. Single correctable ECC event detected */
|
||||
#define DDR0_00_INT_STATUS_BIT2 0x00040000
|
||||
/* Bit3. Multiple correctable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT3 0x00080000
|
||||
/* Bit4. Single uncorrectable ECC event detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT4 0x00100000
|
||||
/* Bit5. Multiple uncorrectable ECC events detected. */
|
||||
#define DDR0_00_INT_STATUS_BIT5 0x00200000
|
||||
/* Bit6. DRAM initialization complete. */
|
||||
#define DDR0_00_INT_STATUS_BIT6 0x00400000
|
||||
/* Bit7. Logical OR of all lower bits. */
|
||||
#define DDR0_00_INT_STATUS_BIT7 0x00800000
|
||||
|
||||
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
|
||||
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
|
||||
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
#define DDR0_01 0x01
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_01_INT_MASK_MASK 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
|
||||
|
||||
#define DDR0_02 0x02
|
||||
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
|
||||
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
|
||||
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
|
||||
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
|
||||
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
|
||||
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_02_START_MASK 0x00000001
|
||||
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
#define DDR0_02_START_OFF 0x00000000
|
||||
#define DDR0_02_START_ON 0x00000001
|
||||
|
||||
#define DDR0_03 0x03
|
||||
#define DDR0_03_BSTLEN_MASK 0x07000000
|
||||
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_03_CASLAT_MASK 0x00070000
|
||||
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
|
||||
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_03_INITAREF_MASK 0x0000000F
|
||||
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_04 0x04
|
||||
#define DDR0_04_TRC_MASK 0x1F000000
|
||||
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_04_TRRD_MASK 0x00070000
|
||||
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_04_TRTP_MASK 0x00000700
|
||||
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
|
||||
#define DDR0_05 0x05
|
||||
#define DDR0_05_TMRD_MASK 0x1F000000
|
||||
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_05_TEMRS_MASK 0x00070000
|
||||
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_05_TRP_MASK 0x00000F00
|
||||
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
|
||||
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#define DDR0_06 0x06
|
||||
#define DDR0_06_WRITEINTERP_MASK 0x01000000
|
||||
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_06_TWTR_MASK 0x00070000
|
||||
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
#define DDR0_06_TDLL_MASK 0x0000FF00
|
||||
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_06_TRFC_MASK 0x0000007F
|
||||
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_07 0x07
|
||||
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
|
||||
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_07_TFAW_MASK 0x001F0000
|
||||
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_07_AREFRESH_MASK 0x00000001
|
||||
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_08 0x08
|
||||
#define DDR0_08_WRLAT_MASK 0x07000000
|
||||
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_08_TCPD_MASK 0x00FF0000
|
||||
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_08_DQS_N_EN_MASK 0x00000100
|
||||
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
|
||||
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_09 0x09
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_09_RTT_0_MASK 0x00030000
|
||||
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
|
||||
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_10 0x0A
|
||||
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
|
||||
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_10_CS_MAP_MASK 0x00000300
|
||||
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
|
||||
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
|
||||
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
|
||||
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
|
||||
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
|
||||
|
||||
#define DDR0_11 0x0B
|
||||
#define DDR0_11_SREFRESH_MASK 0x01000000
|
||||
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||
#define DDR0_11_TXSNR_MASK 0x00FF0000
|
||||
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_11_TXSR_MASK 0x0000FF00
|
||||
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
|
||||
#define DDR0_12 0x0C
|
||||
#define DDR0_12_TCKE_MASK 0x0000007
|
||||
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
|
||||
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
|
||||
|
||||
#define DDR0_13 0x0D
|
||||
|
||||
#define DDR0_14 0x0E
|
||||
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
|
||||
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||
#define DDR0_14_REDUC_MASK 0x00010000
|
||||
#define DDR0_14_REDUC_64BITS 0x00000000
|
||||
#define DDR0_14_REDUC_32BITS 0x00010000
|
||||
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
|
||||
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||
|
||||
#define DDR0_15 0x0F
|
||||
|
||||
#define DDR0_16 0x10
|
||||
|
||||
#define DDR0_17 0x11
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
|
||||
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
|
||||
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
|
||||
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
|
||||
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
|
||||
#define DDR0_18 0x12
|
||||
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_19 0x13
|
||||
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_20 0x14
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_21 0x15
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
#define DDR0_22 0x16
|
||||
/* ECC */
|
||||
#define DDR0_22_CTRL_RAW_MASK 0x03000000
|
||||
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
|
||||
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
|
||||
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
|
||||
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
|
||||
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
|
||||
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||
|
||||
|
||||
#define DDR0_23 0x17
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
|
||||
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
|
||||
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
|
||||
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_24 0x18
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
|
||||
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
|
||||
|
||||
#define DDR0_25 0x19
|
||||
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
|
||||
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||
|
||||
#define DDR0_26 0x1A
|
||||
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
|
||||
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
#define DDR0_26_TREF_MASK 0x00003FFF
|
||||
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||
|
||||
#define DDR0_27 0x1B
|
||||
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_27_TINIT_MASK 0x0000FFFF
|
||||
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_28 0x1C
|
||||
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
|
||||
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
|
||||
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||
|
||||
#define DDR0_29 0x1D
|
||||
|
||||
#define DDR0_30 0x1E
|
||||
|
||||
#define DDR0_31 0x1F
|
||||
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
|
||||
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||
|
||||
#define DDR0_32 0x20
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_33 0x21
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_34 0x22
|
||||
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_35 0x23
|
||||
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_36 0x24
|
||||
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_37 0x25
|
||||
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_38 0x26
|
||||
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_39 0x27
|
||||
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
|
||||
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_40 0x28
|
||||
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_41 0x29
|
||||
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||
|
||||
#define DDR0_42 0x2A
|
||||
#define DDR0_42_ADDR_PINS_MASK 0x07000000
|
||||
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
|
||||
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||
|
||||
#define DDR0_43 0x2B
|
||||
#define DDR0_43_TWR_MASK 0x07000000
|
||||
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||
#define DDR0_43_APREBIT_MASK 0x000F0000
|
||||
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
|
||||
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
|
||||
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
|
||||
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||
|
||||
#define DDR0_44 0x2C
|
||||
#define DDR0_44_TRCD_MASK 0x000000FF
|
||||
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||
|
||||
#endif /* _SPD_SDRAM_DENALI_H_ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
|
||||
* DDR2 controller (non Denali Core). Those are 440SP/SPe.
|
||||
*
|
||||
* (C) Copyright 2007
|
||||
* (C) Copyright 2007-2008
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* COPYRIGHT AMCC CORPORATION 2004
|
||||
|
|
@ -111,8 +111,6 @@
|
|||
#define NUMMEMWORDS 8
|
||||
#define NUMLOOPS 64 /* memory test loops */
|
||||
|
||||
#undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
|
||||
|
||||
/*
|
||||
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
|
||||
* region. Right now the cache should still be disabled in U-Boot because of the
|
||||
|
|
@ -2268,39 +2266,6 @@ static void program_ecc(unsigned long *dimm_populated,
|
|||
return;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ECC_ERROR_RESET
|
||||
/*
|
||||
* Check for ECC errors and reset board upon any error here
|
||||
*
|
||||
* On the Katmai 440SPe eval board, from time to time, the first
|
||||
* lword write access after DDR2 initializazion with ECC checking
|
||||
* enabled, leads to an ECC error. I couldn't find a configuration
|
||||
* without this happening. On my board with the current setup it
|
||||
* happens about 1 from 10 times.
|
||||
*
|
||||
* The ECC modules used for testing are:
|
||||
* - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
|
||||
*
|
||||
* This has to get fixed for the Katmai and tested for the other
|
||||
* board (440SP/440SPe) that will eventually use this code in the
|
||||
* future.
|
||||
*
|
||||
* 2007-03-01, sr
|
||||
*/
|
||||
static void check_ecc(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mfsdram(SDRAM_ECCCR, val);
|
||||
if (val != 0) {
|
||||
printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
|
||||
val, mfdcr(0x4c), mfdcr(0x4e));
|
||||
printf("ECC error occured, resetting board...\n");
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void wait_ddr_idle(void)
|
||||
{
|
||||
u32 val;
|
||||
|
|
@ -2375,15 +2340,6 @@ static void program_ecc_addr(unsigned long start_address,
|
|||
sync();
|
||||
eieio();
|
||||
wait_ddr_idle();
|
||||
|
||||
#ifdef CONFIG_ECC_ERROR_RESET
|
||||
/*
|
||||
* One write to 0 is enough to trigger this ECC error
|
||||
* (see description above)
|
||||
*/
|
||||
out_be32(0, 0x12345678);
|
||||
check_ecc();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2409,17 +2365,10 @@ static void program_DQS_calibration(unsigned long *dimm_populated,
|
|||
* Read sample cycle auto-update enable
|
||||
*-----------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Modified for the Katmai platform: with some DIMMs, the DDR2
|
||||
* controller automatically selects the T2 read cycle, but this
|
||||
* proves unreliable. Go ahead and force the DDR2 controller
|
||||
* to use the T4 sample and disable the automatic update of the
|
||||
* RDSS field.
|
||||
*/
|
||||
mfsdram(SDRAM_RDCC, val);
|
||||
mtsdram(SDRAM_RDCC,
|
||||
(val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
|
||||
| (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
|
||||
| SDRAM_RDCC_RSAE_ENABLE);
|
||||
|
||||
/*------------------------------------------------------------------
|
||||
* Program RQDC register
|
||||
|
|
@ -2512,10 +2461,7 @@ static void DQS_calibration_process(void)
|
|||
{
|
||||
unsigned long rfdc_reg;
|
||||
unsigned long rffd;
|
||||
unsigned long rqdc_reg;
|
||||
unsigned long rqfd;
|
||||
unsigned long val;
|
||||
long rqfd_average;
|
||||
long rffd_average;
|
||||
long max_start;
|
||||
long min_end;
|
||||
|
|
@ -2533,10 +2479,14 @@ static void DQS_calibration_process(void)
|
|||
long max_end;
|
||||
unsigned char fail_found;
|
||||
unsigned char pass_found;
|
||||
#if !defined(CONFIG_DDR_RQDC_FIXED)
|
||||
u32 rqdc_reg;
|
||||
u32 rqfd;
|
||||
u32 rqfd_start;
|
||||
u32 rqfd_average;
|
||||
int loopi = 0;
|
||||
char str[] = "Auto calibration -";
|
||||
char slash[] = "\\|/-\\|/-";
|
||||
int loopi = 0;
|
||||
|
||||
/*------------------------------------------------------------------
|
||||
* Test to determine the best read clock delay tuning bits.
|
||||
|
|
@ -2571,6 +2521,16 @@ calibration_loop:
|
|||
mfsdram(SDRAM_RQDC, rqdc_reg);
|
||||
mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
|
||||
SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
|
||||
#else /* CONFIG_DDR_RQDC_FIXED */
|
||||
/*
|
||||
* On Katmai the complete auto-calibration somehow doesn't seem to
|
||||
* produce the best results, meaning optimal values for RQFD/RFFD.
|
||||
* This was discovered by GDA using a high bandwidth scope,
|
||||
* analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
|
||||
* so now on Katmai "only" RFFD is auto-calibrated.
|
||||
*/
|
||||
mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
|
||||
#endif /* CONFIG_DDR_RQDC_FIXED */
|
||||
|
||||
max_start = 0;
|
||||
min_end = 0;
|
||||
|
|
@ -2655,6 +2615,7 @@ calibration_loop:
|
|||
/* now fix RFDC[RFFD] found and find RQDC[RQFD] */
|
||||
mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
|
||||
|
||||
#if !defined(CONFIG_DDR_RQDC_FIXED)
|
||||
max_pass_length = 0;
|
||||
max_start = 0;
|
||||
max_end = 0;
|
||||
|
|
@ -2727,8 +2688,6 @@ calibration_loop:
|
|||
spd_ddr_init_hang ();
|
||||
}
|
||||
|
||||
blank_string(strlen(str));
|
||||
|
||||
if (rqfd_average < 0)
|
||||
rqfd_average = 0;
|
||||
|
||||
|
|
@ -2739,12 +2698,31 @@ calibration_loop:
|
|||
(rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
|
||||
SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
|
||||
|
||||
blank_string(strlen(str));
|
||||
#endif /* CONFIG_DDR_RQDC_FIXED */
|
||||
|
||||
/*
|
||||
* Now complete RDSS configuration as mentioned on page 7 of the AMCC
|
||||
* PowerPC440SP/SPe DDR2 application note:
|
||||
* "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
|
||||
*/
|
||||
mfsdram(SDRAM_RTSR, val);
|
||||
if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
|
||||
mfsdram(SDRAM_RDCC, val);
|
||||
if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
|
||||
val += 0x40000000;
|
||||
mtsdram(SDRAM_RDCC, val);
|
||||
}
|
||||
}
|
||||
|
||||
mfsdram(SDRAM_DLCR, val);
|
||||
debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
|
||||
mfsdram(SDRAM_RQDC, val);
|
||||
debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
|
||||
mfsdram(SDRAM_RFDC, val);
|
||||
debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
|
||||
mfsdram(SDRAM_RDCC, val);
|
||||
debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
|
||||
}
|
||||
#else /* calibration test with hardvalues */
|
||||
/*-----------------------------------------------------------------------------+
|
||||
|
|
|
|||
|
|
@ -99,14 +99,7 @@ static int wait_for_dram_init_complete(void)
|
|||
/*-----------------------------------------------------------------------------+
|
||||
* denali_core_search_data_eye.
|
||||
+----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* Avoid conflict with implementations of denali_core_search_data_eye in board-
|
||||
* specific code.
|
||||
*/
|
||||
void denali_core_search_data_eye(void)
|
||||
__attribute__ ((weak, alias("__denali_core_search_data_eye")));
|
||||
|
||||
void __denali_core_search_data_eye(void)
|
||||
{
|
||||
int k, j;
|
||||
u32 val;
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
#include <asm/gpio.h>
|
||||
|
||||
#if defined(CFG_4xx_GPIO_TABLE)
|
||||
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
|
||||
gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE;
|
||||
#endif
|
||||
|
||||
#if defined(GPIO0_OSRL)
|
||||
|
|
@ -120,6 +120,18 @@ int gpio_read_out_bit(int pin)
|
|||
return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
|
||||
}
|
||||
|
||||
int gpio_read_in_bit(int pin)
|
||||
{
|
||||
u32 offs = 0;
|
||||
|
||||
if (pin >= GPIO_MAX) {
|
||||
offs = 0x100;
|
||||
pin -= GPIO_MAX;
|
||||
}
|
||||
|
||||
return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0);
|
||||
}
|
||||
|
||||
#if defined(CFG_4xx_GPIO_TABLE)
|
||||
void gpio_set_chip_configuration(void)
|
||||
{
|
||||
|
|
@ -171,6 +183,8 @@ void gpio_set_chip_configuration(void)
|
|||
if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
|
||||
(gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
|
||||
|
||||
u32 gpio_alt_sel = 0;
|
||||
|
||||
switch (gpio_tab[gpio_core][i].alt_nb) {
|
||||
case GPIO_SEL:
|
||||
/*
|
||||
|
|
@ -199,37 +213,40 @@ void gpio_set_chip_configuration(void)
|
|||
break;
|
||||
|
||||
case GPIO_ALT1:
|
||||
reg = in_be32((void *)GPIO_OS(core_add+offs))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
reg = reg | (GPIO_ALT1_SEL >> (j*2));
|
||||
out_be32((void *)GPIO_OS(core_add+offs), reg);
|
||||
reg = in_be32((void *)GPIO_TS(core_add+offs))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
reg = reg | (GPIO_ALT1_SEL >> (j*2));
|
||||
out_be32((void *)GPIO_TS(core_add+offs), reg);
|
||||
gpio_alt_sel = GPIO_ALT1_SEL;
|
||||
break;
|
||||
|
||||
case GPIO_ALT2:
|
||||
reg = in_be32((void *)GPIO_OS(core_add+offs))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
reg = reg | (GPIO_ALT2_SEL >> (j*2));
|
||||
out_be32((void *)GPIO_OS(core_add+offs), reg);
|
||||
reg = in_be32((void *)GPIO_TS(core_add+offs))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
reg = reg | (GPIO_ALT2_SEL >> (j*2));
|
||||
out_be32((void *)GPIO_TS(core_add+offs), reg);
|
||||
gpio_alt_sel = GPIO_ALT2_SEL;
|
||||
break;
|
||||
|
||||
case GPIO_ALT3:
|
||||
gpio_alt_sel = GPIO_ALT3_SEL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (0 != gpio_alt_sel) {
|
||||
reg = in_be32((void *)GPIO_OS(core_add+offs))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
reg = reg | (GPIO_ALT3_SEL >> (j*2));
|
||||
reg = reg | (gpio_alt_sel >> (j*2));
|
||||
out_be32((void *)GPIO_OS(core_add+offs), reg);
|
||||
|
||||
if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) {
|
||||
reg = in_be32((void *)GPIO_TCR(core_add))
|
||||
| (0x80000000 >> (i));
|
||||
out_be32((void *)GPIO_TCR(core_add), reg);
|
||||
reg = in_be32((void *)GPIO_TS(core_add+offs))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
reg = reg | (GPIO_ALT3_SEL >> (j*2));
|
||||
out_be32((void *)GPIO_TS(core_add+offs), reg);
|
||||
break;
|
||||
} else {
|
||||
reg = in_be32((void *)GPIO_TCR(core_add))
|
||||
& ~(0x80000000 >> (i));
|
||||
out_be32((void *)GPIO_TCR(core_add), reg);
|
||||
reg = in_be32((void *)GPIO_TS(core_add+offs))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
reg = reg | (gpio_alt_sel >> (j*2));
|
||||
out_be32((void *)GPIO_TS(core_add+offs), reg);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -88,6 +88,7 @@ typedef struct {
|
|||
void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
|
||||
void gpio_write_bit(int pin, int val);
|
||||
int gpio_read_out_bit(int pin);
|
||||
int gpio_read_in_bit(int pin);
|
||||
void gpio_set_chip_configuration(void);
|
||||
|
||||
#endif /* __ASM_PPC_GPIO_H */
|
||||
|
|
|
|||
|
|
@ -111,6 +111,7 @@
|
|||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
|
||||
#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
|
||||
#define CONFIG_DDR_ECC 1 /* with ECC support */
|
||||
#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
|
||||
#undef CONFIG_STRESS
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* (C) Copyright 2007-2008
|
||||
* Larry Johnson, lrj@acm.org
|
||||
*
|
||||
* (C) Copyright 2006-2007
|
||||
|
|
@ -361,6 +361,157 @@
|
|||
#define CFG_EBC_PB2AP 0x04017300
|
||||
#define CFG_EBC_PB2CR (CFG_CPLD_BASE | 0x00038000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* GPIO Setup
|
||||
*
|
||||
* Korat GPIO usage:
|
||||
*
|
||||
* Init.
|
||||
* Pin Source I/O value Function
|
||||
* ------ ------ --- ----- ---------------------------------
|
||||
* GPIO00 Alt1 I/O x PerAddr07
|
||||
* GPIO01 Alt1 I/O x PerAddr06
|
||||
* GPIO02 Alt1 I/O x PerAddr05
|
||||
* GPIO03 GPIO x x GPIO03 to expansion bus connector
|
||||
* GPIO04 GPIO x x GPIO04 to expansion bus connector
|
||||
* GPIO05 GPIO x x GPIO05 to expansion bus connector
|
||||
* GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
|
||||
* GPIO07 Alt1 O x PerCS2 (CPLD)
|
||||
* GPIO08 Alt1 O x PerCS3 to expansion bus connector
|
||||
* GPIO09 Alt1 O x PerCS4 to expansion bus connector
|
||||
* GPIO10 Alt1 O x PerCS5 to expansion bus connector
|
||||
* GPIO11 Alt1 I x PerErr
|
||||
* GPIO12 GPIO O 0 ATMega !Reset
|
||||
* GPIO13 GPIO O 1 SPI Atmega !SS
|
||||
* GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
|
||||
* GPIO15 GPIO O 0 CPU Run LED !On
|
||||
* GPIO16 Alt1 O x GMC1TxD0
|
||||
* GPIO17 Alt1 O x GMC1TxD1
|
||||
* GPIO18 Alt1 O x GMC1TxD2
|
||||
* GPIO19 Alt1 O x GMC1TxD3
|
||||
* GPIO20 Alt1 I x RejectPkt0
|
||||
* GPIO21 Alt1 I x RejectPkt1
|
||||
* GPIO22 GPIO I x PGOOD_DDR
|
||||
* GPIO23 Alt1 O x SCPD0
|
||||
* GPIO24 Alt1 O x GMC0TxD2
|
||||
* GPIO25 Alt1 O x GMC0TxD3
|
||||
* GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
|
||||
* GPIO27 GPIO O 0 PHY #0 1000BASE-X select
|
||||
* GPIO28 GPIO O 0 PHY #1 1000BASE-X select
|
||||
* GPIO29 GPIO I x Test jumper !Present
|
||||
* GPIO30 GPIO I x SFP module #0 !Present
|
||||
* GPIO31 GPIO I x SFP module #1 !Present
|
||||
*
|
||||
* GPIO32 GPIO O 1 SFP module #0 Tx !Enable
|
||||
* GPIO33 GPIO O 1 SFP module #1 Tx !Enable
|
||||
* GPIO34 Alt2 I x !UART1_CTS
|
||||
* GPIO35 Alt2 O x !UART1_RTS
|
||||
* GPIO36 Alt1 I x !UART0_CTS
|
||||
* GPIO37 Alt1 O x !UART0_RTS
|
||||
* GPIO38 Alt2 O x UART1_Tx
|
||||
* GPIO39 Alt2 I x UART1_Rx
|
||||
* GPIO40 Alt1 I x IRQ0 (Ethernet 0)
|
||||
* GPIO41 Alt1 I x IRQ1 (Ethernet 1)
|
||||
* GPIO42 Alt1 I x IRQ2 (PCI interrupt)
|
||||
* GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
|
||||
* GPIO44 xxxx x x (grounded through pulldown)
|
||||
* GPIO45 GPIO O 0 PHY #0 Enable
|
||||
* GPIO46 GPIO O 0 PHY #1 Enable
|
||||
* GPIO47 GPIO I x Reset switch !Pressed
|
||||
* GPIO48 GPIO I x Shutdown switch !Pressed
|
||||
* GPIO49 xxxx x x (reserved for trace port)
|
||||
* . . . . .
|
||||
* . . . . .
|
||||
* . . . . .
|
||||
* GPIO63 xxxx x x (reserved for trace port)
|
||||
*----------------------------------------------------------------------*/
|
||||
|
||||
#define CFG_GPIO_ATMEGA_SS_ 13
|
||||
#define CFG_GPIO_PHY0_FIBER_SEL 27
|
||||
#define CFG_GPIO_PHY1_FIBER_SEL 28
|
||||
#define CFG_GPIO_SFP0_PRESENT_ 30
|
||||
#define CFG_GPIO_SFP1_PRESENT_ 31
|
||||
#define CFG_GPIO_SFP0_TX_EN_ 32
|
||||
#define CFG_GPIO_SFP1_TX_EN_ 33
|
||||
#define CFG_GPIO_PHY0_EN 45
|
||||
#define CFG_GPIO_PHY1_EN 46
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PPC440 GPIO Configuration
|
||||
*/
|
||||
#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
|
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
|
||||
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
|
||||
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
|
||||
{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
|
||||
{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
|
||||
{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO13 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
|
||||
}, \
|
||||
{ \
|
||||
/* GPIO Core 1 */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
|
||||
} \
|
||||
}
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
|
|
|
|||
|
|
@ -476,6 +476,83 @@
|
|||
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
|
||||
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PPC440 GPIO Configuration
|
||||
*/
|
||||
/* test-only: take GPIO init from pcs440ep ???? in config file */
|
||||
#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
|
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
|
||||
{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
|
||||
{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
|
||||
{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
|
||||
}, \
|
||||
{ \
|
||||
/* GPIO Core 1 */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
|
||||
{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
|
||||
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
|
||||
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
|
||||
} \
|
||||
}
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
|
|
|
|||
|
|
@ -492,6 +492,7 @@
|
|||
#define SDRAM_ECCCR 0x98 /* ECC error status */
|
||||
#define SDRAM_CID 0xA4 /* core ID */
|
||||
#define SDRAM_RID 0xA8 /* revision ID */
|
||||
#define SDRAM_RTSR 0xB1 /* run time status tracking */
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Memory Controller Status
|
||||
|
|
@ -605,8 +606,8 @@
|
|||
#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
|
||||
#define SDRAM_RFDC_RFOS_MASK 0x007F0000
|
||||
#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||
#define SDRAM_RFDC_RFFD_MASK 0x000003FF
|
||||
#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||
#define SDRAM_RFDC_RFFD_MASK 0x000007FF
|
||||
#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x7FF)<<0)
|
||||
|
||||
#define SDRAM_RFDC_RFFD_MAX 0x7FF
|
||||
|
||||
|
|
@ -690,6 +691,7 @@
|
|||
#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
|
||||
#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
|
||||
#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
|
||||
#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| SDRAM Write Timing Register
|
||||
|
|
@ -790,6 +792,12 @@
|
|||
#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
|
||||
#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
|
||||
|
||||
#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/
|
||||
#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */
|
||||
#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */
|
||||
#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */
|
||||
#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */
|
||||
|
||||
#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */
|
||||
#endif /* CONFIG_440SPE */
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ AFLAGS += -DCONFIG_NAND_SPL
|
|||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o init.o resetvec.o
|
||||
COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
|
||||
COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
|
@ -57,6 +57,10 @@ $(nandobj)u-boot-spl: $(OBJS)
|
|||
# create symbolic links for common files
|
||||
|
||||
# from cpu directory
|
||||
$(obj)denali_data_eye.c:
|
||||
@rm -f $(obj)denali_data_eye.c
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
|
||||
|
||||
$(obj)ndfc.c:
|
||||
@rm -f $(obj)ndfc.c
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
|
||||
|
|
|
|||
Loading…
Reference in a new issue