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ARM: OMAP5: set mmc clock frequency to 192MHz

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Now that omap_hsmmc has support for hs200 mode, change the clock
frequency to 192MHz. Also change the REFERENCE CLOCK frequency to
192MHz based on which the internal mmc clock divider is calculated.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This commit is contained in:
Kishon Vijay Abraham I 2018-01-30 16:01:47 +01:00 committed by Jaehoon Chung
parent 04f9f8be83
commit 2022270c7d
3 changed files with 10 additions and 6 deletions
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2
arch/arm/include/asm/arch-omap5/clock.h
View file

@ -135,7 +135,7 @@
/* CM_L3INIT_HSMMCn_CLKCTRL */ /* CM_L3INIT_HSMMCn_CLKCTRL */
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25)
/* CM_L3INIT_SATA_CLKCTRL */ /* CM_L3INIT_SATA_CLKCTRL */
#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) #define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)

4
arch/arm/include/asm/omap_mmc.h
View file

@ -199,7 +199,11 @@ struct omap_hsmmc_plat {
#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
/* Clock Configurations and Macros */ /* Clock Configurations and Macros */
#ifdef CONFIG_OMAP54XX
#define MMC_CLOCK_REFERENCE 192 /* MHz */
#else
#define MMC_CLOCK_REFERENCE 96 /* MHz */ #define MMC_CLOCK_REFERENCE 96 /* MHz */
#endif
/* DLL */ /* DLL */
#define DLL_SWT BIT(20) #define DLL_SWT BIT(20)

10
arch/arm/mach-omap2/omap5/hw_data.c
View file

@ -438,17 +438,17 @@ void enable_basic_clocks(void)
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK); GPIO4_CLKCTRL_OPTFCLKEN_MASK);
/* Enable 96 MHz clock for MMC1 & MMC2 */ /* Enable 192 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK); HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK); HSMMC_CLKCTRL_CLKSEL_MASK);
/* Set the correct clock dividers for mmc */ /* Set the correct clock dividers for mmc */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK); HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_DIV_MASK); HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
/* Select 32KHz clock as the source of GPTIMER1 */ /* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,