mirror of
https://github.com/AsahiLinux/u-boot
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Rename common ns16550 constants with UART_ prefix to prevent conflicts
Fix problems introduced in commit
7b5611cdd1 [inka4x0: Add hardware
diagnosis functions for inka4x0] which redefined MSR_RI which is
already used on PowerPC systems.
Also eliminate redundant definitions in ps2mult.h. More cleanup will
be needed for other redundant occurrences though.
Signed-off-by: Detlev Zundel <dzu@denx.de>
This commit is contained in:
Detlev Zundel
Wolfgang Denk
parent
74de7aefd7
commit
200779e3e2
6 changed files with 135 additions and 178 deletions
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@ -280,48 +280,48 @@ static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
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if ((num >= 0) && (num <= 7)) {
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if (mode & 1) {
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/* turn on 'loopback' mode */
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out_8(&uart->mcr, MCR_LOOP);
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out_8(&uart->mcr, UART_MCR_LOOP);
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} else {
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/*
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* establish the UART's operational parameters
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* set DLAB=1, so rbr accesses DLL
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*/
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out_8(&uart->lcr, LCR_DLAB);
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out_8(&uart->lcr, UART_LCR_DLAB);
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/* set baudrate */
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out_8(&uart->rbr, combrd);
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/* set data-format: 8-N-1 */
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out_8(&uart->lcr, LCR_WLS_8);
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out_8(&uart->lcr, UART_LCR_WLS_8);
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}
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if (mode & 2) {
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/* set request to send */
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out_8(&uart->mcr, MCR_RTS);
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out_8(&uart->mcr, UART_MCR_RTS);
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udelay(10);
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/* check clear to send */
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if ((in_8(&uart->msr) & MSR_CTS) == 0x00)
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if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00)
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return -1;
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}
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if (mode & 4) {
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/* set data terminal ready */
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out_8(&uart->mcr, MCR_DTR);
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out_8(&uart->mcr, UART_MCR_DTR);
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udelay(10);
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/* check data set ready and carrier detect */
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if ((in_8(&uart->msr) & (MSR_DSR | MSR_DCD))
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!= (MSR_DSR | MSR_DCD))
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if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD))
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!= (UART_MSR_DSR | UART_MSR_DCD))
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return -1;
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}
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/* write each message-character, read it back, and display it */
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for (i = 0, len = strlen(argv[3]); i < len; ++i) {
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j = 0;
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while ((in_8(&uart->lsr) & LSR_THRE) == 0x00) {
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while ((in_8(&uart->lsr) & UART_LSR_THRE) == 0x00) {
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if (j++ > CONFIG_SYS_HZ)
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break;
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udelay(10);
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}
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out_8(&uart->rbr, argv[3][i]);
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j = 0;
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while ((in_8(&uart->lsr) & LSR_DR) == 0x00) {
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while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) {
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if (j++ > CONFIG_SYS_HZ)
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break;
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udelay(10);
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@ -90,12 +90,12 @@ void init_AVR_DUART (void)
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*/
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AVR_port->lcr = 0x00;
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AVR_port->ier = 0x00;
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AVR_port->lcr = LCR_BKSE;
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AVR_port->lcr = UART_LCR_BKSE;
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AVR_port->dll = clock_divisor & 0xff;
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AVR_port->dlm = (clock_divisor >> 8) & 0xff;
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AVR_port->lcr = LCR_WLS_8 | LCR_PEN | LCR_EPS;
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AVR_port->lcr = UART_LCR_WLS_8 | UART_LCR_PEN | UART_LCR_EPS;
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AVR_port->mcr = 0x00;
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AVR_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
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AVR_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR;
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miconCntl_DisWDT();
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@ -1,6 +1,6 @@
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/***********************************************************************
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*
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* (C) Copyright 2004
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* (C) Copyright 2004-2009
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* DENX Software Engineering
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* Wolfgang Denk, wd@denx.de
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* All rights reserved.
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@ -18,9 +18,11 @@
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#include <asm/io.h>
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#include <asm/atomic.h>
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#include <ps2mult.h>
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#if defined(CONFIG_SYS_NS16550) || defined(CONFIG_MPC85xx)
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#include <ns16550.h>
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/* This is needed for ns16550.h */
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#ifndef CONFIG_SYS_NS16550_REG_SIZE
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#endif
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#include <ns16550.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -128,12 +130,12 @@ int ps2ser_init(void)
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NS16550_t com_port = (NS16550_t)COM_BASE;
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com_port->ier = 0x00;
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com_port->lcr = LCR_BKSE | LCR_8N1;
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com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
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com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
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com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
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com_port->lcr = LCR_8N1;
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com_port->mcr = (MCR_DTR | MCR_RTS);
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com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
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com_port->lcr = UART_LCR_8N1;
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com_port->mcr = (UART_MCR_DTR | UART_MCR_RTS);
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com_port->fcr = (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR);
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return (0);
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}
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@ -202,7 +204,7 @@ void ps2ser_putc(int chr)
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psc->psc_buffer_8 = chr;
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
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defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
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while ((com_port->lsr & LSR_THRE) == 0);
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while ((com_port->lsr & UART_LSR_THRE) == 0);
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com_port->thr = chr;
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#else
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while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
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@ -227,7 +229,7 @@ static int ps2ser_getc_hw(void)
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}
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
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defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
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if (com_port->lsr & LSR_DR) {
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if (com_port->lsr & UART_LSR_DR) {
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res = com_port->rbr;
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}
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#else
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@ -315,7 +317,7 @@ static void ps2ser_interrupt(void *dev_id)
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} while (status & PSC_SR_RXRDY);
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#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
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defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
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} while (status & LSR_DR);
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} while (status & UART_LSR_DR);
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#else
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} while (status & UART_IIR_RDI);
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#endif
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@ -7,9 +7,12 @@
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#include <config.h>
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#include <ns16550.h>
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#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */
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#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */
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#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */
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#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
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#define UART_MCRVAL (UART_MCR_DTR | \
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UART_MCR_RTS) /* RTS/DTR */
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#define UART_FCRVAL (UART_FCR_FIFO_EN | \
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UART_FCR_RXSR | \
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UART_FCR_TXSR) /* Clear & enable FIFOs */
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void NS16550_init (NS16550_t com_port, int baud_divisor)
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{
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@ -17,16 +20,16 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
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#ifdef CONFIG_OMAP
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com_port->mdr1 = 0x7; /* mode select reset TL16C750*/
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#endif
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com_port->lcr = LCR_BKSE | LCRVAL;
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com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;
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com_port->dll = 0;
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com_port->dlm = 0;
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com_port->lcr = LCRVAL;
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com_port->mcr = MCRVAL;
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com_port->fcr = FCRVAL;
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com_port->lcr = LCR_BKSE | LCRVAL;
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com_port->lcr = UART_LCRVAL;
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com_port->mcr = UART_MCRVAL;
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com_port->fcr = UART_FCRVAL;
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com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;
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com_port->dll = baud_divisor & 0xff;
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com_port->dlm = (baud_divisor >> 8) & 0xff;
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com_port->lcr = LCRVAL;
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com_port->lcr = UART_LCRVAL;
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#if defined(CONFIG_OMAP)
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#if defined(CONFIG_APTIX)
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com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */
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@ -40,29 +43,29 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
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void NS16550_reinit (NS16550_t com_port, int baud_divisor)
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{
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com_port->ier = 0x00;
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com_port->lcr = LCR_BKSE | LCRVAL;
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com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;
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com_port->dll = 0;
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com_port->dlm = 0;
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com_port->lcr = LCRVAL;
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com_port->mcr = MCRVAL;
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com_port->fcr = FCRVAL;
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com_port->lcr = LCR_BKSE;
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com_port->lcr = UART_LCRVAL;
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com_port->mcr = UART_MCRVAL;
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com_port->fcr = UART_FCRVAL;
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com_port->lcr = UART_LCR_BKSE;
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com_port->dll = baud_divisor & 0xff;
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com_port->dlm = (baud_divisor >> 8) & 0xff;
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com_port->lcr = LCRVAL;
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com_port->lcr = UART_LCRVAL;
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}
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#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
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void NS16550_putc (NS16550_t com_port, char c)
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{
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while ((com_port->lsr & LSR_THRE) == 0);
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while ((com_port->lsr & UART_LSR_THRE) == 0);
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com_port->thr = c;
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}
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#ifndef CONFIG_NS16550_MIN_FUNCTIONS
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char NS16550_getc (NS16550_t com_port)
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{
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while ((com_port->lsr & LSR_DR) == 0) {
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while ((com_port->lsr & UART_LSR_DR) == 0) {
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#ifdef CONFIG_USB_TTY
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extern void usbtty_poll(void);
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usbtty_poll();
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@ -73,7 +76,7 @@ char NS16550_getc (NS16550_t com_port)
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int NS16550_tstc (NS16550_t com_port)
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{
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return ((com_port->lsr & LSR_DR) != 0);
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return ((com_port->lsr & UART_LSR_DR) != 0);
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}
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#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
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@ -1,6 +1,10 @@
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/*
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* NS16550 Serial Port
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* originally from linux source (arch/ppc/boot/ns16550.h)
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*
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* Cleanup and unification
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* (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
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*
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* modified slightly to
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* have addresses as offsets from CONFIG_SYS_ISA_BASE
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* added a few more definitions
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@ -115,53 +119,100 @@ struct NS16550 {
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typedef volatile struct NS16550 *NS16550_t;
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#define FCR_FIFO_EN 0x01 /* Fifo enable */
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#define FCR_RXSR 0x02 /* Receiver soft reset */
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#define FCR_TXSR 0x04 /* Transmitter soft reset */
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/*
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* These are the definitions for the FIFO Control Register
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*/
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#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
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#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
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#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
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#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
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#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
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#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
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#define MCR_DTR 0x01
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#define MCR_RTS 0x02
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#define MCR_DMA_EN 0x04
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#define MCR_TX_DFR 0x08
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#define MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
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#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
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#define LCR_WLS_MSK 0x03 /* character length select mask */
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#define LCR_WLS_5 0x00 /* 5 bit character length */
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#define LCR_WLS_6 0x01 /* 6 bit character length */
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#define LCR_WLS_7 0x02 /* 7 bit character length */
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#define LCR_WLS_8 0x03 /* 8 bit character length */
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#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
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#define LCR_PEN 0x08 /* Parity eneble */
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#define LCR_EPS 0x10 /* Even Parity Select */
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#define LCR_STKP 0x20 /* Stick Parity */
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#define LCR_SBRK 0x40 /* Set Break */
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#define LCR_BKSE 0x80 /* Bank select enable */
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#define LCR_DLAB 0x80 /* Divisor latch access bit */
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_DTR 0x01 /* DTR */
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#define UART_MCR_RTS 0x02 /* RTS */
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#define UART_MCR_OUT1 0x04 /* Out 1 */
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#define UART_MCR_OUT2 0x08 /* Out 2 */
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define LSR_DR 0x01 /* Data ready */
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#define LSR_OE 0x02 /* Overrun */
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#define LSR_PE 0x04 /* Parity error */
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#define LSR_FE 0x08 /* Framing error */
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#define LSR_BI 0x10 /* Break */
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#define LSR_THRE 0x20 /* Xmit holding register empty */
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#define LSR_TEMT 0x40 /* Xmitter empty */
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#define LSR_ERR 0x80 /* Error */
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#define UART_MCR_DMA_EN 0x04
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#define UART_MCR_TX_DFR 0x08
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/*
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* These are the definitions for the Line Control Register
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*
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* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
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* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
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*/
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#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
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#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
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#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
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#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
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#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
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#define UART_LCR_PEN 0x08 /* Parity eneble */
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#define UART_LCR_EPS 0x10 /* Even Parity Select */
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#define UART_LCR_STKP 0x20 /* Stick Parity */
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#define UART_LCR_SBRK 0x40 /* Set Break */
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#define UART_LCR_BKSE 0x80 /* Bank select enable */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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/*
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* These are the definitions for the Line Status Register
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*/
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#define UART_LSR_DR 0x01 /* Data ready */
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#define UART_LSR_OE 0x02 /* Overrun */
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#define UART_LSR_PE 0x04 /* Parity error */
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#define UART_LSR_FE 0x08 /* Framing error */
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#define UART_LSR_BI 0x10 /* Break */
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#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
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#define UART_LSR_TEMT 0x40 /* Xmitter empty */
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#define UART_LSR_ERR 0x80 /* Error */
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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/*
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* These are the definitions for the Interrupt Identification Register
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*/
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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/*
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* These are the definitions for the Interrupt Enable Register
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*/
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define MSR_DCD 0x80 /* Data Carrier Detect */
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#define MSR_RI 0x40 /* Ring Indicator */
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#define MSR_DSR 0x20 /* Data Set Ready */
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#define MSR_CTS 0x10 /* Clear to Send */
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#define MSR_DDCD 0x08 /* Delta DCD */
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#define MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define MSR_DDSR 0x02 /* Delta DSR */
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#define MSR_DCTS 0x01 /* Delta CTS */
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#ifdef CONFIG_OMAP1510
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#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
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#endif
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||||
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/* useful defaults for LCR */
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#define LCR_8N1 0x03
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#define UART_LCR_8N1 0x03
|
||||
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||||
void NS16550_init (NS16550_t com_port, int baud_divisor);
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||||
void NS16550_putc (NS16550_t com_port, char c);
|
||||
|
|
|
|||
|
|
@ -53,103 +53,4 @@ struct serial_state {
|
|||
u8 *iomem_base;
|
||||
};
|
||||
|
||||
#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
|
||||
#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
|
||||
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
|
||||
|
||||
#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
|
||||
#define UART_IER 1 /* Out: Interrupt Enable Register */
|
||||
|
||||
#define UART_IIR 2 /* In: Interrupt ID Register */
|
||||
#define UART_FCR 2 /* Out: FIFO Control Register */
|
||||
|
||||
#define UART_LCR 3 /* Out: Line Control Register */
|
||||
#define UART_MCR 4 /* Out: Modem Control Register */
|
||||
#define UART_LSR 5 /* In: Line Status Register */
|
||||
#define UART_MSR 6 /* In: Modem Status Register */
|
||||
#define UART_SCR 7 /* I/O: Scratch Register */
|
||||
|
||||
/*
|
||||
* These are the definitions for the FIFO Control Register
|
||||
* (16650 only)
|
||||
*/
|
||||
#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
|
||||
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
|
||||
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
|
||||
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
|
||||
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
|
||||
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
|
||||
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
|
||||
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
|
||||
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Line Control Register
|
||||
*
|
||||
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
|
||||
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
|
||||
*/
|
||||
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
|
||||
#define UART_LCR_SBC 0x40 /* Set break control */
|
||||
#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
|
||||
#define UART_LCR_EPAR 0x10 /* Even parity select */
|
||||
#define UART_LCR_PARITY 0x08 /* Parity Enable */
|
||||
#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
|
||||
#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
|
||||
#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
|
||||
#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
|
||||
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Line Status Register
|
||||
*/
|
||||
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
|
||||
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
|
||||
#define UART_LSR_BI 0x10 /* Break interrupt indicator */
|
||||
#define UART_LSR_FE 0x08 /* Frame error indicator */
|
||||
#define UART_LSR_PE 0x04 /* Parity error indicator */
|
||||
#define UART_LSR_OE 0x02 /* Overrun error indicator */
|
||||
#define UART_LSR_DR 0x01 /* Receiver data ready */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Interrupt Identification Register
|
||||
*/
|
||||
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
|
||||
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
|
||||
|
||||
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
|
||||
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
|
||||
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
|
||||
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Interrupt Enable Register
|
||||
*/
|
||||
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
|
||||
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
|
||||
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
|
||||
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Modem Control Register
|
||||
*/
|
||||
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
|
||||
#define UART_MCR_OUT2 0x08 /* Out2 complement */
|
||||
#define UART_MCR_OUT1 0x04 /* Out1 complement */
|
||||
#define UART_MCR_RTS 0x02 /* RTS complement */
|
||||
#define UART_MCR_DTR 0x01 /* DTR complement */
|
||||
|
||||
/*
|
||||
* These are the definitions for the Modem Status Register
|
||||
*/
|
||||
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
|
||||
#define UART_MSR_RI 0x40 /* Ring Indicator */
|
||||
#define UART_MSR_DSR 0x20 /* Data Set Ready */
|
||||
#define UART_MSR_CTS 0x10 /* Clear to Send */
|
||||
#define UART_MSR_DDCD 0x08 /* Delta DCD */
|
||||
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
|
||||
#define UART_MSR_DDSR 0x02 /* Delta DSR */
|
||||
#define UART_MSR_DCTS 0x01 /* Delta CTS */
|
||||
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
|
||||
|
||||
#endif /* __LINUX_PS2MULT_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue