mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
board:trats2: Enable device tree on Trats2
This patch enables to run Trats2 board on device tree. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Piotr Wilczek
Minkyu Kang
parent
fe60164792
commit
1ecab0f30f
4 changed files with 485 additions and 393 deletions
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@ -1,6 +1,7 @@
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dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
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exynos4210-universal_c210.dtb \
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exynos4210-trats.dtb
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exynos4210-trats.dtb \
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exynos4412-trats2.dtb
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dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
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exynos5250-snow.dtb \
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434
arch/arm/dts/exynos4412-trats2.dts
Normal file
434
arch/arm/dts/exynos4412-trats2.dts
Normal file
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@ -0,0 +1,434 @@
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/*
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* Samsung's Exynos4412 based Trats2 board device tree source
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/include/ "exynos4.dtsi"
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/ {
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model = "Samsung Trats2 based on Exynos4412";
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compatible = "samsung,trats2", "samsung,exynos4412";
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config {
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samsung,dsim-device-name = "s6e8ax0";
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};
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aliases {
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i2c0 = "/i2c@13860000";
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i2c1 = "/i2c@13870000";
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i2c2 = "/i2c@13880000";
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i2c3 = "/i2c@13890000";
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i2c4 = "/i2c@138a0000";
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i2c5 = "/i2c@138b0000";
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i2c6 = "/i2c@138c0000";
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i2c7 = "/i2c@138d0000";
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serial0 = "/serial@13800000";
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console = "/serial@13820000";
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mmc0 = "sdhci@12510000";
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mmc2 = "sdhci@12530000";
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};
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i2c@138d0000 {
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samsung,i2c-sda-delay = <100>;
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samsung,i2c-slave-addr = <0x10>;
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samsung,i2c-max-bus-freq = <100000>;
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status = "okay";
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max77686_pmic@09 {
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compatible = "maxim,max77686_pmic";
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interrupts = <7 0>;
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reg = <0x09 0 0>;
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#clock-cells = <1>;
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voltage-regulators {
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ldo1_reg: ldo1 {
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regulator-compatible = "LDO1";
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regulator-name = "VALIVE_1.0V_AP";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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regulator-mem-on;
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};
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ldo2_reg: ldo2 {
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regulator-compatible = "LDO2";
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regulator-name = "VM1M2_1.2V_AP";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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regulator-mem-on;
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};
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ldo3_reg: ldo3 {
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regulator-compatible = "LDO3";
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regulator-name = "VCC_1.8V_AP";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-mem-on;
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};
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ldo4_reg: ldo4 {
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regulator-compatible = "LDO4";
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regulator-name = "VCC_2.8V_AP";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-always-on;
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regulator-mem-on;
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};
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ldo5_reg: ldo5 {
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regulator-compatible = "LDO5";
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regulator-name = "VCC_1.8V_IO";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-mem-on;
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};
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ldo6_reg: ldo6 {
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regulator-compatible = "LDO6";
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regulator-name = "VMPLL_1.0V_AP";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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regulator-mem-on;
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};
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ldo7_reg: ldo7 {
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regulator-compatible = "LDO7";
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regulator-name = "VPLL_1.0V_AP";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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regulator-mem-on;
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};
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ldo8_reg: ldo8 {
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regulator-compatible = "LDO8";
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regulator-name = "VMIPI_1.0V";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-mem-off;
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};
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ldo9_reg: ldo9 {
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regulator-compatible = "LDO9";
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regulator-name = "CAM_ISP_MIPI_1.2V";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-mem-idle;
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};
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ldo10_reg: ldo10 {
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regulator-compatible = "LDO10";
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regulator-name = "VMIPI_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-mem-off;
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};
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ldo11_reg: ldo11 {
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regulator-compatible = "LDO11";
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regulator-name = "VABB1_1.95V";
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regulator-min-microvolt = <1950000>;
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regulator-max-microvolt = <1950000>;
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regulator-always-on;
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regulator-mem-off;
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};
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ldo12_reg: ldo12 {
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regulator-compatible = "LDO12";
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regulator-name = "VUOTG_3.0V";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-mem-off;
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};
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ldo13_reg: ldo13 {
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regulator-compatible = "LDO13";
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regulator-name = "NFC_AVDD_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-mem-idle;
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};
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ldo14_reg: ldo14 {
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regulator-compatible = "LDO14";
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regulator-name = "VABB2_1.95V";
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regulator-min-microvolt = <1950000>;
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regulator-max-microvolt = <1950000>;
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regulator-always-on;
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regulator-mem-off;
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};
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ldo15_reg: ldo15 {
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regulator-compatible = "LDO15";
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regulator-name = "VHSIC_1.0V";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-mem-off;
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};
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ldo16_reg: ldo16 {
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regulator-compatible = "LDO16";
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regulator-name = "VHSIC_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-mem-off;
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};
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ldo17_reg: ldo17 {
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regulator-compatible = "LDO17";
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regulator-name = "CAM_SENSOR_CORE_1.2V";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-mem-idle;
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};
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ldo18_reg: ldo18 {
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regulator-compatible = "LDO18";
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regulator-name = "CAM_ISP_SEN_IO_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-mem-idle;
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};
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ldo19_reg: ldo19 {
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regulator-compatible = "LDO19";
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regulator-name = "VT_CAM_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-mem-idle;
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};
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ldo20_reg: ldo20 {
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regulator-compatible = "LDO20";
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regulator-name = "VDDQ_PRE_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-mem-idle;
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};
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ldo21_reg: ldo21 {
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regulator-compatible = "LDO21";
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regulator-name = "VTF_2.8V";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-mem-idle;
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};
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ldo22_reg: ldo22 {
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regulator-compatible = "LDO22";
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regulator-name = "VMEM_VDD_2.8V";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-always-on;
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regulator-mem-off;
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};
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ldo23_reg: ldo23 {
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regulator-compatible = "LDO23";
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regulator-name = "TSP_AVDD_3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-mem-idle;
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};
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ldo24_reg: ldo24 {
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regulator-compatible = "LDO24";
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regulator-name = "TSP_VDD_1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-mem-idle;
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};
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ldo25_reg: ldo25 {
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regulator-compatible = "LDO25";
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regulator-name = "LCD_VCC_3.3V";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-mem-idle;
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};
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ldo26_reg: ldo26 {
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regulator-compatible = "LDO26";
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regulator-name = "MOTOR_VCC_3.0V";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-mem-idle;
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};
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buck1_reg: buck1 {
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regulator-compatible = "BUCK1";
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regulator-name = "vdd_mif";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-mem-off;
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};
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buck2_reg: buck2 {
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regulator-compatible = "BUCK2";
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regulator-name = "vdd_arm";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1500000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-mem-off;
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};
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buck3_reg: buck3 {
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regulator-compatible = "BUCK3";
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regulator-name = "vdd_int";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1150000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-mem-off;
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};
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buck4_reg: buck4 {
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regulator-compatible = "BUCK4";
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regulator-name = "vdd_g3d";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1150000>;
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regulator-boot-on;
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regulator-mem-off;
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};
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buck5_reg: buck5 {
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regulator-compatible = "BUCK5";
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regulator-name = "VMEM_1.2V_AP";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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buck6_reg: buck6 {
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regulator-compatible = "BUCK6";
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regulator-name = "VCC_SUB_1.35V";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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};
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buck7_reg: buck7 {
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regulator-compatible = "BUCK7";
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regulator-name = "VCC_SUB_2.0V";
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regulator-min-microvolt = <2000000>;
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regulator-max-microvolt = <2000000>;
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regulator-always-on;
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};
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buck8_reg: buck8 {
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regulator-compatible = "BUCK8";
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regulator-name = "VMEM_VDDF_3.0V";
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <2850000>;
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regulator-always-on;
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regulator-mem-off;
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};
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buck9_reg: buck9 {
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regulator-compatible = "BUCK9";
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regulator-name = "CAM_ISP_CORE_1.2V";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1200000>;
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regulator-mem-off;
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};
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};
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};
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};
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fimd@11c00000 {
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compatible = "samsung,exynos-fimd";
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reg = <0x11c00000 0xa4>;
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samsung,vl-freq = <60>;
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samsung,vl-col = <720>;
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samsung,vl-row = <1280>;
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samsung,vl-width = <720>;
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samsung,vl-height = <1280>;
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samsung,vl-clkp = <0>;
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samsung,vl-oep = <0>;
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samsung,vl-hsp = <1>;
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samsung,vl-vsp = <1>;
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samsung,vl-dp = <1>;
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samsung,vl-bpix = <4>;
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samsung,vl-hspw = <5>;
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samsung,vl-hbpd = <10>;
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samsung,vl-hfpd = <10>;
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samsung,vl-vspw = <2>;
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samsung,vl-vbpd = <1>;
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samsung,vl-vfpd = <13>;
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samsung,vl-cmd-allow-len = <0xf>;
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samsung,winid = <0>;
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samsung,power-on-delay = <30>;
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samsung,interface-mode = <1>;
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samsung,mipi-enabled = <1>;
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samsung,dp-enabled;
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samsung,dual-lcd-enabled;
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samsung,logo-on = <1>;
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samsung,resolution = <0>;
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samsung,rgb-mode = <0>;
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};
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mipidsi@11c80000 {
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compatible = "samsung,exynos-mipi-dsi";
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reg = <0x11c80000 0x5c>;
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samsung,dsim-config-e-interface = <1>;
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samsung,dsim-config-e-virtual-ch = <0>;
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samsung,dsim-config-e-pixel-format = <7>;
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samsung,dsim-config-e-burst-mode = <1>;
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samsung,dsim-config-e-no-data-lane = <3>;
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samsung,dsim-config-e-byte-clk = <0>;
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samsung,dsim-config-hfp = <1>;
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samsung,dsim-config-p = <3>;
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samsung,dsim-config-m = <120>;
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samsung,dsim-config-s = <1>;
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samsung,dsim-config-pll-stable-time = <500>;
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samsung,dsim-config-esc-clk = <20000000>;
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samsung,dsim-config-stop-holding-cnt = <0x7ff>;
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samsung,dsim-config-bta-timeout = <0xff>;
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samsung,dsim-config-rx-timeout = <0xffff>;
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samsung,dsim-device-id = <0xffffffff>;
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samsung,dsim-device-bus-id = <0>;
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samsung,dsim-device-reverse-panel = <1>;
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};
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sdhci@12510000 {
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samsung,bus-width = <8>;
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samsung,timing = <1 3 3>;
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pwr-gpios = <&gpio 0x2004002 0>;
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};
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sdhci@12520000 {
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status = "disabled";
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};
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sdhci@12530000 {
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samsung,bus-width = <4>;
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samsung,timing = <1 2 3>;
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cd-gpios = <&gpio 0x20C6004 0>;
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};
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sdhci@12540000 {
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status = "disabled";
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};
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};
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@ -8,15 +8,9 @@
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#include <common.h>
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#include <lcd.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/power.h>
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#include <asm/arch/clk.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/mipi_dsim.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/power.h>
|
||||
#include <asm/arch/mipi_dsim.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/max77686_pmic.h>
|
||||
#include <power/battery.h>
|
||||
|
|
@ -28,7 +22,6 @@
|
|||
#include <usb.h>
|
||||
#include <usb/s3c_udc.h>
|
||||
#include <usb_mass_storage.h>
|
||||
#include <samsung/misc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -69,16 +62,6 @@ static void check_hw_revision(void)
|
|||
board_rev = modelrev << 8;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DISPLAY_BOARDINFO
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board:\tTRATS2\n");
|
||||
printf("HW Revision:\t0x%04x\n", board_rev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return board_rev;
|
||||
|
|
@ -156,33 +139,24 @@ int get_soft_i2c_sda_pin(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
int exynos_early_init_f(void)
|
||||
{
|
||||
check_hw_revision();
|
||||
board_external_gpio_init();
|
||||
|
||||
gd->flags |= GD_FLG_DISABLE_CONSOLE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmic_init_max77686(void);
|
||||
|
||||
int board_init(void)
|
||||
int exynos_init(void)
|
||||
{
|
||||
struct exynos4_power *pwr =
|
||||
(struct exynos4_power *)samsung_get_base_power();
|
||||
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
/* workaround: clear INFORM4..5 */
|
||||
writel(0, (unsigned int)&pwr->inform4);
|
||||
writel(0, (unsigned int)&pwr->inform5);
|
||||
check_hw_revision();
|
||||
printf("HW Revision:\t0x%04x\n", board_rev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int power_init_board(void)
|
||||
int exynos_power_init(void)
|
||||
{
|
||||
int chrg;
|
||||
struct power_battery *pb;
|
||||
|
|
@ -248,90 +222,6 @@ int power_init_board(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
u32 size_mb;
|
||||
|
||||
size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
|
||||
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
|
||||
get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
|
||||
get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20;
|
||||
|
||||
gd->ram_size = size_mb << 20;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
|
||||
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
|
||||
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
|
||||
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
|
||||
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int err0, err2 = 0;
|
||||
|
||||
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
|
||||
|
||||
/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
|
||||
s5p_gpio_direction_output(&gpio2->k0, 2, 1);
|
||||
s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE);
|
||||
|
||||
/*
|
||||
* eMMC GPIO:
|
||||
* SDR 8-bit@48MHz at MMC0
|
||||
* GPK0[0] SD_0_CLK(2)
|
||||
* GPK0[1] SD_0_CMD(2)
|
||||
* GPK0[2] SD_0_CDn -> Not used
|
||||
* GPK0[3:6] SD_0_DATA[0:3](2)
|
||||
* GPK1[3:6] SD_0_DATA[0:3](3)
|
||||
*
|
||||
* DDR 4-bit@26MHz at MMC4
|
||||
* GPK0[0] SD_4_CLK(3)
|
||||
* GPK0[1] SD_4_CMD(3)
|
||||
* GPK0[2] SD_4_CDn -> Not used
|
||||
* GPK0[3:6] SD_4_DATA[0:3](3)
|
||||
* GPK1[3:6] SD_4_DATA[4:7](4)
|
||||
*/
|
||||
|
||||
err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
|
||||
|
||||
/*
|
||||
* MMC device init
|
||||
* mmc0 : eMMC (8-bit buswidth)
|
||||
* mmc2 : SD card (4-bit buswidth)
|
||||
*/
|
||||
if (err0)
|
||||
debug("SDMMC0 not configured\n");
|
||||
else
|
||||
err0 = s5p_mmc_init(0, 8);
|
||||
|
||||
/* T-flash detect */
|
||||
s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
|
||||
s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
|
||||
|
||||
/*
|
||||
* Check the T-flash detect pin
|
||||
* GPX3[4] T-flash detect pin
|
||||
*/
|
||||
if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
|
||||
err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
|
||||
if (err2)
|
||||
debug("SDMMC2 not configured\n");
|
||||
else
|
||||
err2 = s5p_mmc_init(2, 4);
|
||||
}
|
||||
|
||||
return err0 & err2;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_GADGET
|
||||
static int s5pc210_phy_control(int on)
|
||||
{
|
||||
|
|
@ -479,46 +369,7 @@ static int pmic_init_max77686(void)
|
|||
*/
|
||||
|
||||
#ifdef CONFIG_LCD
|
||||
static struct mipi_dsim_config dsim_config = {
|
||||
.e_interface = DSIM_VIDEO,
|
||||
.e_virtual_ch = DSIM_VIRTUAL_CH_0,
|
||||
.e_pixel_format = DSIM_24BPP_888,
|
||||
.e_burst_mode = DSIM_BURST_SYNC_EVENT,
|
||||
.e_no_data_lane = DSIM_DATA_LANE_4,
|
||||
.e_byte_clk = DSIM_PLL_OUT_DIV8,
|
||||
.hfp = 1,
|
||||
|
||||
.p = 3,
|
||||
.m = 120,
|
||||
.s = 1,
|
||||
|
||||
/* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
|
||||
.pll_stable_time = 500,
|
||||
|
||||
/* escape clk : 10MHz */
|
||||
.esc_clk = 20 * 1000000,
|
||||
|
||||
/* stop state holding counter after bta change count 0 ~ 0xfff */
|
||||
.stop_holding_cnt = 0x7ff,
|
||||
/* bta timeout 0 ~ 0xff */
|
||||
.bta_timeout = 0xff,
|
||||
/* lp rx timeout 0 ~ 0xffff */
|
||||
.rx_timeout = 0xffff,
|
||||
};
|
||||
|
||||
static struct exynos_platform_mipi_dsim dsim_platform_data = {
|
||||
.lcd_panel_info = NULL,
|
||||
.dsim_config = &dsim_config,
|
||||
};
|
||||
|
||||
static struct mipi_dsim_lcd_device mipi_lcd_device = {
|
||||
.name = "s6e8ax0",
|
||||
.id = -1,
|
||||
.bus_id = 0,
|
||||
.platform_data = (void *)&dsim_platform_data,
|
||||
};
|
||||
|
||||
static int mipi_power(void)
|
||||
int mipi_power(void)
|
||||
{
|
||||
struct pmic *p = pmic_get("MAX77686_PMIC");
|
||||
|
||||
|
|
@ -556,77 +407,13 @@ void exynos_reset_lcd(void)
|
|||
s5p_gpio_set_value(&gpio1->f2, 1, 1);
|
||||
}
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
.vl_freq = 60,
|
||||
.vl_col = 720,
|
||||
.vl_row = 1280,
|
||||
.vl_width = 720,
|
||||
.vl_height = 1280,
|
||||
.vl_clkp = CONFIG_SYS_HIGH,
|
||||
.vl_hsp = CONFIG_SYS_LOW,
|
||||
.vl_vsp = CONFIG_SYS_LOW,
|
||||
.vl_dp = CONFIG_SYS_LOW,
|
||||
.vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */
|
||||
|
||||
/* s6e8ax0 Panel infomation */
|
||||
.vl_hspw = 5,
|
||||
.vl_hbpd = 10,
|
||||
.vl_hfpd = 10,
|
||||
|
||||
.vl_vspw = 2,
|
||||
.vl_vbpd = 1,
|
||||
.vl_vfpd = 13,
|
||||
.vl_cmd_allow_len = 0xf,
|
||||
.mipi_enabled = 1,
|
||||
|
||||
.dual_lcd_enabled = 0,
|
||||
|
||||
.init_delay = 0,
|
||||
.power_on_delay = 25,
|
||||
.reset_delay = 0,
|
||||
.interface_mode = FIMD_RGB_INTERFACE,
|
||||
};
|
||||
|
||||
void init_panel_info(vidinfo_t *vid)
|
||||
void exynos_lcd_misc_init(vidinfo_t *vid)
|
||||
{
|
||||
vid->logo_on = 1;
|
||||
vid->resolution = HD_RESOLUTION;
|
||||
vid->rgb_mode = MODE_RGB_P;
|
||||
|
||||
vid->power_on_delay = 30;
|
||||
|
||||
mipi_lcd_device.reverse_panel = 1;
|
||||
|
||||
#ifdef CONFIG_TIZEN
|
||||
get_tizen_logo_info(vid);
|
||||
#endif
|
||||
|
||||
strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name);
|
||||
dsim_platform_data.mipi_power = mipi_power;
|
||||
dsim_platform_data.phy_enable = set_mipi_phy_ctrl;
|
||||
dsim_platform_data.lcd_panel_info = (void *)vid;
|
||||
exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
|
||||
|
||||
#ifdef CONFIG_S6E8AX0
|
||||
s6e8ax0_init();
|
||||
|
||||
exynos_set_dsim_platform_data(&dsim_platform_data);
|
||||
#endif
|
||||
}
|
||||
#endif /* LCD */
|
||||
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
set_board_info();
|
||||
#endif
|
||||
#ifdef CONFIG_LCD_MENU
|
||||
keys_init();
|
||||
check_boot_mode();
|
||||
#endif
|
||||
#ifdef CONFIG_CMD_BMP
|
||||
if (panel_info.logo_on)
|
||||
draw_logo();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -8,27 +8,17 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
#ifndef __CONFIG_TRATS2_H
|
||||
#define __CONFIG_TRATS2_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P /* which is in a S5P Family */
|
||||
#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
|
||||
#define CONFIG_TIZEN /* TIZEN lib */
|
||||
#include <configs/exynos4-dt.h>
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#undef CONFIG_DEFAULT_DEVICE_TREE
|
||||
#define CONFIG_DEFAULT_DEVICE_TREE exynos4412-trats2
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
#define CONFIG_TIZEN /* TIZEN lib */
|
||||
|
||||
#define CONFIG_SYS_L2CACHE_OFF
|
||||
#ifndef CONFIG_SYS_L2CACHE_OFF
|
||||
|
|
@ -36,122 +26,48 @@
|
|||
#define CONFIG_SYS_PL310_BASE 0x10502000
|
||||
#endif
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 4
|
||||
#define PHYS_SDRAM_1 0x40000000 /* LDDDR2 DMC 0 */
|
||||
#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
|
||||
#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
|
||||
#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
|
||||
#define PHYS_SDRAM_3 0x60000000 /* LPDDR2 DMC 1 */
|
||||
#define PHYS_SDRAM_3_SIZE (256 << 20) /* 256 MB in CS 0 */
|
||||
#define PHYS_SDRAM_4 0x70000000 /* LPDDR2 DMC 1 */
|
||||
#define PHYS_SDRAM_4_SIZE (256 << 20) /* 256 MB in CS 0 */
|
||||
#define PHYS_SDRAM_END 0x80000000
|
||||
/* TRATS2 has 4 banks of DRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 4
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
|
||||
#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
|
||||
/* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
|
||||
|
||||
#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
|
||||
#define CONFIG_SYS_TEXT_BASE 0x78100000
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 24000000
|
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
|
||||
/* MACH_TYPE_TRATS2 */
|
||||
#define MACH_TYPE_TRATS2 3765
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_TRATS2
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
#include <linux/sizes.h>
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_SERIAL2
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* It should define before config_cmd_default.h */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
/***********************************************************
|
||||
* Command definition
|
||||
***********************************************************/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_ECHO
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_FLASH
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_NAND
|
||||
#undef CONFIG_CMD_MISC
|
||||
#undef CONFIG_CMD_NFS
|
||||
#undef CONFIG_CMD_SOURCE
|
||||
#undef CONFIG_CMD_XIMG
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_DFU
|
||||
#define CONFIG_CMD_GPT
|
||||
#define CONFIG_CMD_PMIC
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_FAT_WRITE
|
||||
|
||||
/* EXT4 */
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_EXT4_WRITE
|
||||
|
||||
/* USB Composite download gadget - g_dnl */
|
||||
#define CONFIG_USBDOWNLOAD_GADGET
|
||||
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
|
||||
#define DFU_DEFAULT_POLL_TIMEOUT 300
|
||||
#define CONFIG_DFU_FUNCTION
|
||||
#define CONFIG_DFU_MMC
|
||||
|
||||
/* TIZEN THOR downloader support */
|
||||
#define CONFIG_CMD_THOR_DOWNLOAD
|
||||
#define CONFIG_THOR_FUNCTION
|
||||
|
||||
/* USB Samsung's IDs */
|
||||
#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
|
||||
#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
|
||||
#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
|
||||
#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
|
||||
#define CONFIG_G_DNL_MANUFACTURER "Samsung"
|
||||
|
||||
/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
|
||||
#undef CONFIG_CMD_NET
|
||||
|
||||
/* MMC */
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_S5P_SDHCI
|
||||
#define CONFIG_SDHCI
|
||||
#define CONFIG_MMC_SDMA
|
||||
#define CONFIG_MMC_DEFAULT_DEV 0
|
||||
|
||||
/* PWM */
|
||||
#define CONFIG_PWM
|
||||
|
||||
#define CONFIG_BOOTARGS "Please use defined boot"
|
||||
#define CONFIG_BOOTCOMMAND "run mmcboot"
|
||||
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
/* Console configuration */
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
|
||||
#define CONFIG_BOOTARGS "Please use defined boot"
|
||||
#define CONFIG_BOOTCOMMAND "run mmcboot"
|
||||
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
|
||||
- GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000
|
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
|
||||
#define CONFIG_ENV_SIZE 4096
|
||||
#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_CONFIG
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
|
||||
|
|
@ -246,49 +162,11 @@
|
|||
"setenv spl_addr_tmp;\0" \
|
||||
"fdtaddr=40800000\0" \
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
|
||||
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
/* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
|
||||
- GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/* valid baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
|
||||
#define CONFIG_ENV_SIZE 4096
|
||||
#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_PARTITION_UUIDS
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* I2C */
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
#define CONFIG_CMD_I2C
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_S3C24X0
|
||||
#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
|
||||
|
|
@ -318,11 +196,6 @@ int get_soft_i2c_sda_pin(void);
|
|||
#define CONFIG_POWER_MUIC_MAX77693
|
||||
#define CONFIG_POWER_FG_MAX77693
|
||||
#define CONFIG_POWER_BATTERY_TRATS2
|
||||
#define CONFIG_USB_GADGET
|
||||
#define CONFIG_USB_GADGET_S3C_UDC_OTG
|
||||
#define CONFIG_USB_GADGET_DUALSPEED
|
||||
#define CONFIG_USB_GADGET_VBUS_DRAW 2
|
||||
#define CONFIG_USB_CABLE_CHECK
|
||||
|
||||
/* Common misc for Samsung */
|
||||
#define CONFIG_MISC_COMMON
|
||||
|
|
@ -362,10 +235,7 @@ int get_soft_i2c_sda_pin(void);
|
|||
#define CONFIG_VIDEO_BMP_GZIP
|
||||
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
|
||||
|
||||
#define CONFIG_CMD_USB_MASS_STORAGE
|
||||
#define CONFIG_USB_GADGET_MASS_STORAGE
|
||||
|
||||
/* Pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define LCD_XRES 720
|
||||
#define LCD_YRES 1280
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue