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lx2160aqds : Add support for LX2160AQDS platform
LX2160AQDS is a development board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> [PK: Sqaush patch for "secure boot defconfig" & add maintainer] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Pankaj Bansal
Prabhakar Kushwaha
parent
edc975b8aa
commit
1eba723c72
14 changed files with 1526 additions and 3 deletions
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@ -1096,6 +1096,19 @@ config TARGET_LX2160ARDB
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is a high-performance development platform that supports the
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QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
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config TARGET_LX2160AQDS
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bool "Support lx2160aqds"
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select ARCH_LX2160A
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select ARCH_MISC_INIT
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select ARM64
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select ARMV8_MULTIENTRY
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select BOARD_LATE_INIT
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help
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Support for NXP LX2160AQDS platform.
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The lx2160aqds (LX2160A QorIQ Development System (QDS)
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is a high-performance development platform that supports the
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QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
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config TARGET_HIKEY
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bool "Support HiKey 96boards Consumer Edition Platform"
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select ARM64
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@ -107,6 +107,7 @@ config PSCI_RESET
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!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
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!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
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!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
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!TARGET_LX2160AQDS && \
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!ARCH_UNIPHIER && !TARGET_S32V234EVB
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help
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Most armv8 systems have PSCI support enabled in EL3, either through
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@ -247,7 +247,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
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fsl-ls2088a-rdb-qspi.dtb \
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fsl-ls1088a-rdb.dtb \
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fsl-ls1088a-qds.dtb \
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fsl-lx2160a-rdb.dtb
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fsl-lx2160a-rdb.dtb \
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fsl-lx2160a-qds.dtb
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dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
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fsl-ls1043a-qds-lpuart.dtb \
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fsl-ls1043a-rdb.dtb \
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17
arch/arm/dts/fsl-lx2160a-qds.dts
Normal file
17
arch/arm/dts/fsl-lx2160a-qds.dts
Normal file
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@ -0,0 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source
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*
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* Copyright 2018-2019 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS Board";
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compatible = "fsl,lx2160aqds", "fsl,lx2160a";
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};
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@ -2,7 +2,7 @@
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/*
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* LayerScape Internal Memory Map
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*
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* Copyright 2017-2018 NXP
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* Copyright 2017-2019 NXP
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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@ -350,6 +350,14 @@ struct ccsr_gur {
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#define FSL_CHASSIS3_SRDS1_REGSR 29
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#define FSL_CHASSIS3_SRDS2_REGSR 29
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#define FSL_CHASSIS3_SRDS3_REGSR 29
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#define FSL_CHASSIS3_RCWSR12_REGSR 12
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#define FSL_CHASSIS3_RCWSR13_REGSR 13
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#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000
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#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
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#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038
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#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
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#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00
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#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9
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#elif defined(CONFIG_ARCH_LS1088A)
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#define FSL_CHASSIS3_EC1_REGSR 26
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#define FSL_CHASSIS3_EC2_REGSR 26
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@ -14,3 +14,21 @@ config SYS_CONFIG_NAME
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source "board/freescale/common/Kconfig"
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endif
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if TARGET_LX2160AQDS
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config SYS_BOARD
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default "lx2160a"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "lx2160aqds"
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source "board/freescale/common/Kconfig"
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endif
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@ -11,3 +11,16 @@ LX2160ARDB_SECURE_BOOT BOARD
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M: Udit Agarwal <udit.agarwal@nxp.com>
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S: Maintained
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F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
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LX2160AQDS BOARD
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M: Pankaj Bansal <pankaj.bansal@nxp.com>
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S: Maintained
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F: board/freescale/lx2160a/eth_lx2160aqds.h
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F: include/configs/lx2160aqds.h
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F: configs/lx2160aqds_tfa_defconfig
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F: arch/arm/dts/fsl-lx2160a-qds.dts
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LX2160AQDS_SECURE_BOOT BOARD
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M: Udit Agarwal <udit.agarwal@nxp.com>
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S: Maintained
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F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
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@ -7,3 +7,4 @@
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obj-y += lx2160a.o
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obj-y += ddr.o
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obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
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obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
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@ -77,3 +77,121 @@ DPAA2 MC Firmware 0x05000
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DPAA2 DPL 0x06800
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DPAA2 DPC 0x07000
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Kernel.itb 0x08000
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LX2160AQDS board Overview
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----------------------
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Various Mezzanine cards and their connection for different SERDES protocols is
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as below:
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SERDES1 |CARDS
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-----------------------------------------------------------------------
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1 |Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
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|Connect I/O cable to IO_SLOT1(J110)
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|Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
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|Connect I/O cable to IO_SLOT2(J113)
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------------------------------------------------------------------------
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3 |Mezzanine:X-M11-USXGMII (29828)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
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|Connect I/O cable to IO_SLOT1(J110)
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|Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
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|Connect I/O cable to IO_SLOT2(J113)
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------------------------------------------------------------------------
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7 |Mezzanine:X-M11-USXGMII (29828)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
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|Connect I/O cable to IO_SLOT1(J110)
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|Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
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|Connect I/O cable to IO_SLOT2(J113)
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------------------------------------------------------------------------
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8 |Mezzanine:X-M12-XFI (29829)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
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|Connect I/O cable to IO_SLOT1(J110)
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|Mezzanine:X-M12-XFI (29829)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
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|Connect I/O cable to IO_SLOT2(J113)
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------------------------------------------------------------------------
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13 |Mezzanine:X-M8-100G (29734)
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|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
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|Connect I/O cable to IO_SLOT1(J110)
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|Mezzanine:X-M8-100G (29734)
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|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT2(J111)
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|Connect I/O cable to IO_SLOT2(J113)
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------------------------------------------------------------------------
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15 |Mezzanine:X-M8-100G (29734)
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|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
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|Connect I/O cable to IO_SLOT1(J110)
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|Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
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|Connect I/O cable to IO_SLOT2(J113)
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------------------------------------------------------------------------
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17 |Mezzanine:X-M13-25G (32133)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
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|Connect I/O cable to IO_SLOT1(J110)
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|Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
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|Connect I/O cable to IO_SLOT2(J113)
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------------------------------------------------------------------------
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19 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
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|Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125)
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|Mezzanine:X-M7-40G (29738)
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|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)
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|Connect I/O cable to IO_SLOT2(J113)
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------------------------------------------------------------------------
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20 |Mezzanine:X-M7-40G (29738)
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|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
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|Connect I/O cable to IO_SLOT1(J108)
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|Mezzanine:X-M7-40G (29738)
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|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)
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|Connect I/O cable to IO_SLOT2(J113)
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------------------------------------------------------------------------
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SERDES2 |CARDS
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-----------------------------------------------------------------------
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2 |Mezzanine:X-M6-PCIE-X8 (29737) *
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
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|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117)
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|Connect I/O cable to IO_SLOT3(J116)
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------------------------------------------------------------------------
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3 |Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
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|Connect I/O cable to IO_SLOT3(J116)
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|Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
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|Connect I/O cable to IO_SLOT4(J119)
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------------------------------------------------------------------------
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5 |Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
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|Connect I/O cable to IO_SLOT3(J116)
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|Mezzanine:X-M5-SATA (29687)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
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|Connect I/O cable to IO_SLOT4(J119)
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------------------------------------------------------------------------
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11 |Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
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|Connect I/O cable to IO_SLOT7(J127)
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|Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
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|Connect I/O cable to IO_SLOT8(J131)
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------------------------------------------------------------------------
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SERDES3 |CARDS
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-----------------------------------------------------------------------
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2 |Mezzanine:X-M6-PCIE-X8 (29737) *
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)
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|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT6 (J123)
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|Connect I/O cable to IO_SLOT5(J122)
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-------------------------------------------------------------------------
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3 |Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)
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|Connect I/O cable to IO_SLOT5(J122)
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|Mezzanine:X-M4-PCIE-SGMII (29733)
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|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT6 (J123)
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|Connect I/O cable to IO_SLOT6(J125)
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-------------------------------------------------------------------------
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805
board/freescale/lx2160a/eth_lx2160aqds.c
Normal file
805
board/freescale/lx2160a/eth_lx2160aqds.c
Normal file
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@ -0,0 +1,805 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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*
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <command.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <exports.h>
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#include <asm/arch/fsl_serdes.h>
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#include <fsl-mc/fsl_mc.h>
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#include <fsl-mc/ldpaa_wriop.h>
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#include "../common/qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define EMI_NONE 0
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#define EMI1 1 /* Mdio Bus 1 */
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#define EMI2 2 /* Mdio Bus 2 */
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#if defined(CONFIG_FSL_MC_ENET)
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enum io_slot {
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IO_SLOT_NONE = 0,
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IO_SLOT_1,
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IO_SLOT_2,
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IO_SLOT_3,
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IO_SLOT_4,
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IO_SLOT_5,
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IO_SLOT_6,
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IO_SLOT_7,
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IO_SLOT_8,
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EMI1_RGMII1,
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EMI1_RGMII2,
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IO_SLOT_MAX
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};
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struct lx2160a_qds_mdio {
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enum io_slot ioslot : 4;
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u8 realbusnum : 4;
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struct mii_dev *realbus;
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};
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/* structure explaining the phy configuration on 8 lanes of a serdes*/
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struct serdes_phy_config {
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u8 serdes; /* serdes protocol */
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struct phy_config {
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u8 dpmacid;
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/* -1 terminated array */
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int phy_address[WRIOP_MAX_PHY_NUM + 1];
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u8 mdio_bus;
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enum io_slot ioslot;
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} phy_config[SRDS_MAX_LANES];
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};
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/* Table defining the phy configuration on 8 lanes of a serdes.
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* Various assumptions have been made while defining this table.
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* e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
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* card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
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* And also that this card is connected to IO Slot 1 (could have been connected
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* to any of the 8 IO slots (IO slot 1 - IO slot 8)).
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* similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
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* used in serdes1 protocol 19 (could have selected MDIO 2)
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* To override these settings "dpmac" environment variable can be used after
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* defining "dpmac_override" in hwconfig environment variable.
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* This table has limited serdes protocol entries. It can be expanded as per
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* requirement.
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*/
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static const struct serdes_phy_config serdes1_phy_config[] = {
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{3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
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EMI1, IO_SLOT_1},
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{WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
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EMI1, IO_SLOT_1},
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{WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
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EMI1, IO_SLOT_1},
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{WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
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EMI1, IO_SLOT_1} } },
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{7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
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EMI1, IO_SLOT_1},
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{WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
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EMI1, IO_SLOT_1},
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{WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
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EMI1, IO_SLOT_1},
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{WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
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EMI1, IO_SLOT_1},
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{WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
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EMI1, IO_SLOT_2},
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{WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
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EMI1, IO_SLOT_2},
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{WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
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EMI1, IO_SLOT_2},
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{WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
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EMI1, IO_SLOT_2} } },
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{8, {} },
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{13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
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EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_2} } },
|
||||
{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1} } },
|
||||
{17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1} } },
|
||||
{19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
|
||||
EMI1, IO_SLOT_2},
|
||||
{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_6},
|
||||
{WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_6} } },
|
||||
{20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
|
||||
EMI1, IO_SLOT_2} } }
|
||||
};
|
||||
|
||||
static const struct serdes_phy_config serdes2_phy_config[] = {
|
||||
{2, {} },
|
||||
{3, {} },
|
||||
{5, {} },
|
||||
{11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_7},
|
||||
{WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_7},
|
||||
{WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_7},
|
||||
{WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_8},
|
||||
{WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_8},
|
||||
{WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_8} } },
|
||||
};
|
||||
|
||||
static const struct serdes_phy_config serdes3_phy_config[] = {
|
||||
{2, {} },
|
||||
{3, {} }
|
||||
};
|
||||
|
||||
static inline
|
||||
const struct phy_config *get_phy_config(u8 serdes,
|
||||
const struct serdes_phy_config *table,
|
||||
u8 table_size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < table_size; i++) {
|
||||
if (table[i].serdes == serdes)
|
||||
return table[i].phy_config;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* BRDCFG4 controls EMI routing for the board.
|
||||
* Bits Function
|
||||
* 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
|
||||
* EMI1 00= On-board PHY #1
|
||||
* 01= On-board PHY #2
|
||||
* 10= (reserved)
|
||||
* 11= Slots 1..8 multiplexer and translator.
|
||||
* 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
|
||||
* EMI1X 000= Slot #1
|
||||
* 001= Slot #2
|
||||
* 010= Slot #3
|
||||
* 011= Slot #4
|
||||
* 100= Slot #5
|
||||
* 101= Slot #6
|
||||
* 110= Slot #7
|
||||
* 111= Slot #8
|
||||
* 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
|
||||
* EMI2 000= Slot #1 (secondary EMI)
|
||||
* 001= Slot #2 (secondary EMI)
|
||||
* 010= Slot #3 (secondary EMI)
|
||||
* 011= Slot #4 (secondary EMI)
|
||||
* 100= Slot #5 (secondary EMI)
|
||||
* 101= Slot #6 (secondary EMI)
|
||||
* 110= Slot #7 (secondary EMI)
|
||||
* 111= Slot #8 (secondary EMI)
|
||||
*/
|
||||
static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
|
||||
{
|
||||
switch (realbusnum) {
|
||||
case EMI1:
|
||||
switch (ioslot) {
|
||||
case EMI1_RGMII1:
|
||||
return 0;
|
||||
case EMI1_RGMII2:
|
||||
return 0x40;
|
||||
default:
|
||||
return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
|
||||
}
|
||||
break;
|
||||
case EMI2:
|
||||
return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
|
||||
{
|
||||
u8 brdcfg4, mux_val, reg;
|
||||
|
||||
brdcfg4 = QIXIS_READ(brdcfg[4]);
|
||||
reg = brdcfg4;
|
||||
mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
|
||||
|
||||
switch (priv->realbusnum) {
|
||||
case EMI1:
|
||||
brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
|
||||
brdcfg4 |= mux_val;
|
||||
break;
|
||||
case EMI2:
|
||||
brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
|
||||
brdcfg4 |= mux_val;
|
||||
break;
|
||||
}
|
||||
|
||||
if (brdcfg4 ^ reg)
|
||||
QIXIS_WRITE(brdcfg[4], brdcfg4);
|
||||
}
|
||||
|
||||
static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
|
||||
int devad, int regnum)
|
||||
{
|
||||
struct lx2160a_qds_mdio *priv = bus->priv;
|
||||
|
||||
lx2160a_qds_mux_mdio(priv);
|
||||
|
||||
return priv->realbus->read(priv->realbus, addr, devad, regnum);
|
||||
}
|
||||
|
||||
static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
|
||||
int regnum, u16 value)
|
||||
{
|
||||
struct lx2160a_qds_mdio *priv = bus->priv;
|
||||
|
||||
lx2160a_qds_mux_mdio(priv);
|
||||
|
||||
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
|
||||
}
|
||||
|
||||
static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
|
||||
{
|
||||
struct lx2160a_qds_mdio *priv = bus->priv;
|
||||
|
||||
return priv->realbus->reset(priv->realbus);
|
||||
}
|
||||
|
||||
static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
|
||||
{
|
||||
struct lx2160a_qds_mdio *pmdio;
|
||||
struct mii_dev *bus;
|
||||
/*should be within MDIO_NAME_LEN*/
|
||||
char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
|
||||
|
||||
if (realbusnum == EMI2) {
|
||||
if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
|
||||
printf("invalid ioslot %d\n", ioslot);
|
||||
return NULL;
|
||||
}
|
||||
} else if (realbusnum == EMI1) {
|
||||
if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
|
||||
printf("invalid ioslot %d\n", ioslot);
|
||||
return NULL;
|
||||
}
|
||||
} else {
|
||||
printf("not supported real mdio bus %d\n", realbusnum);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (ioslot == EMI1_RGMII1)
|
||||
strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
|
||||
else if (ioslot == EMI1_RGMII2)
|
||||
strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
|
||||
else
|
||||
sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
|
||||
realbusnum, ioslot);
|
||||
bus = miiphy_get_dev_by_name(dummy_mdio_name);
|
||||
|
||||
if (bus)
|
||||
return bus;
|
||||
|
||||
bus = mdio_alloc();
|
||||
if (!bus) {
|
||||
printf("Failed to allocate %s bus\n", dummy_mdio_name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
pmdio = malloc(sizeof(*pmdio));
|
||||
if (!pmdio) {
|
||||
printf("Failed to allocate %s private data\n", dummy_mdio_name);
|
||||
free(bus);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
switch (realbusnum) {
|
||||
case EMI1:
|
||||
pmdio->realbus =
|
||||
miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
|
||||
break;
|
||||
case EMI2:
|
||||
pmdio->realbus =
|
||||
miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
|
||||
break;
|
||||
}
|
||||
|
||||
if (!pmdio->realbus) {
|
||||
printf("No real mdio bus num %d found\n", realbusnum);
|
||||
free(bus);
|
||||
free(pmdio);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
pmdio->realbusnum = realbusnum;
|
||||
pmdio->ioslot = ioslot;
|
||||
bus->read = lx2160a_qds_mdio_read;
|
||||
bus->write = lx2160a_qds_mdio_write;
|
||||
bus->reset = lx2160a_qds_mdio_reset;
|
||||
strcpy(bus->name, dummy_mdio_name);
|
||||
bus->priv = pmdio;
|
||||
|
||||
if (!mdio_register(bus))
|
||||
return bus;
|
||||
|
||||
printf("No bus with name %s\n", dummy_mdio_name);
|
||||
free(bus);
|
||||
free(pmdio);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void do_phy_config(const struct phy_config *phy_config)
|
||||
{
|
||||
struct mii_dev *bus;
|
||||
int i, phy_num, phy_address;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (!phy_config[i].dpmacid)
|
||||
continue;
|
||||
|
||||
for (phy_num = 0;
|
||||
phy_num < ARRAY_SIZE(phy_config[i].phy_address);
|
||||
phy_num++) {
|
||||
phy_address = phy_config[i].phy_address[phy_num];
|
||||
if (phy_address == -1)
|
||||
break;
|
||||
wriop_set_phy_address(phy_config[i].dpmacid,
|
||||
phy_num, phy_address);
|
||||
}
|
||||
/*Register the muxing front-ends to the MDIO buses*/
|
||||
bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
|
||||
phy_config[i].ioslot);
|
||||
if (!bus)
|
||||
printf("could not get bus for mdio %d ioslot %d\n",
|
||||
phy_config[i].mdio_bus,
|
||||
phy_config[i].ioslot);
|
||||
else
|
||||
wriop_set_mdio(phy_config[i].dpmacid, bus);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
|
||||
char *env_dpmac)
|
||||
{
|
||||
const char *ret;
|
||||
size_t len;
|
||||
u8 realbusnum, ioslot;
|
||||
struct mii_dev *bus;
|
||||
int phy_num;
|
||||
char *phystr = "phy00";
|
||||
|
||||
/*search phy in dpmac arg*/
|
||||
for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
|
||||
sprintf(phystr, "phy%d", phy_num + 1);
|
||||
ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
|
||||
if (!ret) {
|
||||
/*look for phy instead of phy1*/
|
||||
if (!phy_num)
|
||||
ret = hwconfig_subarg_f(arg_dpmacid, "phy",
|
||||
&len, env_dpmac);
|
||||
if (!ret)
|
||||
continue;
|
||||
}
|
||||
|
||||
if (len != 4 || strncmp(ret, "0x", 2))
|
||||
printf("invalid phy format in %s variable.\n"
|
||||
"specify phy%d for %s in hex format e.g. 0x12\n",
|
||||
env_dpmac, phy_num + 1, arg_dpmacid);
|
||||
else
|
||||
wriop_set_phy_address(dpmac, phy_num,
|
||||
simple_strtoul(ret, NULL, 16));
|
||||
}
|
||||
|
||||
/*search mdio in dpmac arg*/
|
||||
ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
|
||||
if (ret)
|
||||
realbusnum = *ret - '0';
|
||||
else
|
||||
realbusnum = EMI_NONE;
|
||||
|
||||
if (realbusnum) {
|
||||
/*search io in dpmac arg*/
|
||||
ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
|
||||
if (ret)
|
||||
ioslot = *ret - '0';
|
||||
else
|
||||
ioslot = IO_SLOT_NONE;
|
||||
/*Register the muxing front-ends to the MDIO buses*/
|
||||
bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
|
||||
if (!bus)
|
||||
printf("could not get bus for mdio %d ioslot %d\n",
|
||||
realbusnum, ioslot);
|
||||
else
|
||||
wriop_set_mdio(dpmac, bus);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
struct memac_mdio_info mdio_info;
|
||||
struct memac_mdio_controller *regs;
|
||||
int i;
|
||||
const char *ret;
|
||||
char *env_dpmac;
|
||||
char dpmacid[] = "dpmac00", srds[] = "00_00_00";
|
||||
size_t len;
|
||||
struct mii_dev *bus;
|
||||
const struct phy_config *phy_config;
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 srds_s1, srds_s2, srds_s3;
|
||||
|
||||
srds_s1 = in_le32(&gur->rcwsr[28]) &
|
||||
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
|
||||
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
srds_s2 = in_le32(&gur->rcwsr[28]) &
|
||||
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
|
||||
srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
|
||||
|
||||
srds_s3 = in_le32(&gur->rcwsr[28]) &
|
||||
FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
|
||||
srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
|
||||
|
||||
sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
|
||||
|
||||
regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
|
||||
mdio_info.regs = regs;
|
||||
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
|
||||
|
||||
/*Register the EMI 1*/
|
||||
fm_memac_mdio_init(bis, &mdio_info);
|
||||
|
||||
regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
|
||||
mdio_info.regs = regs;
|
||||
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
|
||||
|
||||
/*Register the EMI 2*/
|
||||
fm_memac_mdio_init(bis, &mdio_info);
|
||||
|
||||
/* "dpmac" environment variable can be used after
|
||||
* defining "dpmac_override" in hwconfig environment variable.
|
||||
*/
|
||||
if (hwconfig("dpmac_override")) {
|
||||
env_dpmac = env_get("dpmac");
|
||||
if (env_dpmac) {
|
||||
ret = hwconfig_arg_f("srds", &len, env_dpmac);
|
||||
if (ret) {
|
||||
if (strncmp(ret, srds, strlen(srds))) {
|
||||
printf("SERDES configuration changed.\n"
|
||||
"previous: %.*s, current: %s.\n"
|
||||
"update dpmac variable.\n",
|
||||
(int)len, ret, srds);
|
||||
}
|
||||
} else {
|
||||
printf("SERDES configuration not found.\n"
|
||||
"Please add srds:%s in dpmac variable\n",
|
||||
srds);
|
||||
}
|
||||
|
||||
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
|
||||
/* Look for dpmac1 to dpmac24(current max) arg
|
||||
* in dpmac environment variable
|
||||
*/
|
||||
sprintf(dpmacid, "dpmac%d", i);
|
||||
ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
|
||||
if (ret)
|
||||
do_dpmac_config(i, dpmacid, env_dpmac);
|
||||
}
|
||||
} else {
|
||||
printf("Warning: environment dpmac not found.\n"
|
||||
"DPAA network interfaces may not work\n");
|
||||
}
|
||||
} else {
|
||||
/*Look for phy config for serdes1 in phy config table*/
|
||||
phy_config = get_phy_config(srds_s1, serdes1_phy_config,
|
||||
ARRAY_SIZE(serdes1_phy_config));
|
||||
if (!phy_config) {
|
||||
printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
|
||||
__func__, srds_s1);
|
||||
} else {
|
||||
do_phy_config(phy_config);
|
||||
}
|
||||
phy_config = get_phy_config(srds_s2, serdes2_phy_config,
|
||||
ARRAY_SIZE(serdes2_phy_config));
|
||||
if (!phy_config) {
|
||||
printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
|
||||
__func__, srds_s2);
|
||||
} else {
|
||||
do_phy_config(phy_config);
|
||||
}
|
||||
phy_config = get_phy_config(srds_s3, serdes3_phy_config,
|
||||
ARRAY_SIZE(serdes3_phy_config));
|
||||
if (!phy_config) {
|
||||
printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
|
||||
__func__, srds_s3);
|
||||
} else {
|
||||
do_phy_config(phy_config);
|
||||
}
|
||||
}
|
||||
|
||||
if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
|
||||
wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
|
||||
bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
|
||||
if (!bus)
|
||||
printf("could not get bus for RGMII1\n");
|
||||
else
|
||||
wriop_set_mdio(WRIOP1_DPMAC17, bus);
|
||||
}
|
||||
|
||||
if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
|
||||
wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
|
||||
bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
|
||||
if (!bus)
|
||||
printf("could not get bus for RGMII2\n");
|
||||
else
|
||||
wriop_set_mdio(WRIOP1_DPMAC18, bus);
|
||||
}
|
||||
|
||||
cpu_eth_init(bis);
|
||||
#endif /* CONFIG_FMAN_ENET */
|
||||
|
||||
#ifdef CONFIG_PHY_AQUANTIA
|
||||
/*
|
||||
* Export functions to be used by AQ firmware
|
||||
* upload application
|
||||
*/
|
||||
gd->jt->strcpy = strcpy;
|
||||
gd->jt->mdelay = mdelay;
|
||||
gd->jt->mdio_get_current_dev = mdio_get_current_dev;
|
||||
gd->jt->phy_find_by_mask = phy_find_by_mask;
|
||||
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
|
||||
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
|
||||
#endif
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_RESET_PHY_R)
|
||||
void reset_phy(void)
|
||||
{
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
mc_env_boot();
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
|
||||
{
|
||||
int offset;
|
||||
int ret;
|
||||
char dpmac_str[] = "dpmacs@00";
|
||||
const char *phy_string;
|
||||
|
||||
offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
|
||||
|
||||
if (offset < 0)
|
||||
offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
|
||||
|
||||
if (offset < 0) {
|
||||
printf("dpmacs node not found in device tree\n");
|
||||
return offset;
|
||||
}
|
||||
|
||||
sprintf(dpmac_str, "dpmac@%x", dpmac_id);
|
||||
debug("dpmac_str = %s\n", dpmac_str);
|
||||
|
||||
offset = fdt_subnode_offset(fdt, offset, dpmac_str);
|
||||
if (offset < 0) {
|
||||
printf("%s node not found in device tree\n", dpmac_str);
|
||||
return offset;
|
||||
}
|
||||
|
||||
ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
|
||||
if (ret)
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
|
||||
phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
|
||||
ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
|
||||
phy_string);
|
||||
if (ret)
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
|
||||
{
|
||||
char mdio_ioslot_str[] = "mdio@00";
|
||||
char mdio_mux_str[] = "mdio-mux-0";
|
||||
struct lx2160a_qds_mdio *priv;
|
||||
int offset, mux_val;
|
||||
|
||||
/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
|
||||
if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
|
||||
strlen("LX2160A_QDS_MDIO")))
|
||||
return -1;
|
||||
|
||||
/*Get the real MDIO bus num and ioslot info from bus's priv data*/
|
||||
priv = mii_dev->priv;
|
||||
|
||||
debug("real_bus_num = %d, ioslot = %d\n",
|
||||
priv->realbusnum, priv->ioslot);
|
||||
|
||||
sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum);
|
||||
offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str);
|
||||
if (offset < 0) {
|
||||
printf("%s node not found under node %s in device tree\n",
|
||||
mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL));
|
||||
return offset;
|
||||
}
|
||||
|
||||
mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
|
||||
sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
|
||||
|
||||
offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
|
||||
if (offset < 0) {
|
||||
printf("%s node not found in device tree\n", mdio_ioslot_str);
|
||||
return offset;
|
||||
}
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
|
||||
struct phy_device *phy_dev, int phandle)
|
||||
{
|
||||
char phy_node_name[] = "ethernet-phy@00";
|
||||
char phy_id_compatible_str[] = "ethernet-phy-id0000.0000";
|
||||
int ret;
|
||||
|
||||
sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
|
||||
debug("phy_node_name = %s\n", phy_node_name);
|
||||
|
||||
*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
|
||||
if (*subnodeoffset <= 0) {
|
||||
printf("Could not add subnode %s\n", phy_node_name);
|
||||
return *subnodeoffset;
|
||||
}
|
||||
|
||||
sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x",
|
||||
phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
|
||||
debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
|
||||
|
||||
ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
|
||||
phy_id_compatible_str);
|
||||
if (ret) {
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (phy_dev->is_c45) {
|
||||
ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
|
||||
"ethernet-phy-ieee802.3-c45");
|
||||
if (ret) {
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
} else {
|
||||
ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
|
||||
"ethernet-phy-ieee802.3-c22");
|
||||
if (ret) {
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
|
||||
if (ret) {
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
|
||||
if (ret) {
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
if (ret)
|
||||
fdt_del_node(fdt, *subnodeoffset);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int fdt_fixup_board_phy(void *fdt)
|
||||
{
|
||||
int fpga_offset, offset, subnodeoffset;
|
||||
struct mii_dev *mii_dev;
|
||||
struct list_head *mii_devs, *entry;
|
||||
int ret, dpmac_id, phandle, i;
|
||||
struct phy_device *phy_dev;
|
||||
char ethname[ETH_NAME_LEN];
|
||||
phy_interface_t phy_iface;
|
||||
|
||||
ret = 0;
|
||||
/* we know FPGA is connected to i2c0, therefore search path directly,
|
||||
* instead of compatible property, as it saves time
|
||||
*/
|
||||
fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
|
||||
|
||||
if (fpga_offset < 0)
|
||||
fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
|
||||
|
||||
if (fpga_offset < 0) {
|
||||
printf("i2c@2000000/fpga node not found in device tree\n");
|
||||
return fpga_offset;
|
||||
}
|
||||
|
||||
phandle = fdt_alloc_phandle(fdt);
|
||||
mii_devs = mdio_get_list_head();
|
||||
|
||||
list_for_each(entry, mii_devs) {
|
||||
mii_dev = list_entry(entry, struct mii_dev, link);
|
||||
debug("mii_dev name : %s\n", mii_dev->name);
|
||||
offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
|
||||
if (offset < 0)
|
||||
continue;
|
||||
|
||||
// Look for phy devices attached to MDIO bus muxing front end
|
||||
// and create their entries with compatible being the device id
|
||||
for (i = 0; i < PHY_MAX_ADDR; i++) {
|
||||
phy_dev = mii_dev->phymap[i];
|
||||
if (!phy_dev)
|
||||
continue;
|
||||
|
||||
// TODO: use sscanf instead of loop
|
||||
dpmac_id = WRIOP1_DPMAC1;
|
||||
while (dpmac_id < NUM_WRIOP_PORTS) {
|
||||
phy_iface = wriop_get_enet_if(dpmac_id);
|
||||
snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
|
||||
dpmac_id,
|
||||
phy_string_for_interface(phy_iface));
|
||||
if (strcmp(ethname, phy_dev->dev->name) == 0)
|
||||
break;
|
||||
dpmac_id++;
|
||||
}
|
||||
if (dpmac_id == NUM_WRIOP_PORTS)
|
||||
continue;
|
||||
|
||||
ret = fdt_create_phy_node(fdt, offset, i,
|
||||
&subnodeoffset,
|
||||
phy_dev, phandle);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
ret = fdt_fixup_dpmac_phy_handle(fdt,
|
||||
dpmac_id, phandle);
|
||||
if (ret) {
|
||||
fdt_del_node(fdt, subnodeoffset);
|
||||
break;
|
||||
}
|
||||
phandle++;
|
||||
}
|
||||
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif // CONFIG_FSL_MC_ENET
|
||||
|
||||
|
|
@ -30,6 +30,18 @@
|
|||
#include "../common/emc2305.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
|
||||
#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
|
||||
#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
|
||||
#define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
|
||||
#define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
|
||||
#define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
|
||||
#define SDHC1_BASE_PMUX_DSPI 2
|
||||
#define SDHC2_BASE_PMUX_DSPI 2
|
||||
#define IIC5_PMUX_SPI3 3
|
||||
#endif /* CONFIG_TARGET_LX2160AQDS */
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct pl01x_serial_platdata serial0 = {
|
||||
|
|
@ -96,12 +108,80 @@ int board_early_init_f(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_TARGET_LX2160AQDS)
|
||||
void esdhc_dspi_status_fixup(void *blob)
|
||||
{
|
||||
const char esdhc0_path[] = "/soc/esdhc@2140000";
|
||||
const char esdhc1_path[] = "/soc/esdhc@2150000";
|
||||
const char dspi0_path[] = "/soc/dspi@2100000";
|
||||
const char dspi1_path[] = "/soc/dspi@2110000";
|
||||
const char dspi2_path[] = "/soc/dspi@2120000";
|
||||
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 sdhc1_base_pmux;
|
||||
u32 sdhc2_base_pmux;
|
||||
u32 iic5_pmux;
|
||||
|
||||
/* Check RCW field sdhc1_base_pmux to enable/disable
|
||||
* esdhc0/dspi0 DT node
|
||||
*/
|
||||
sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
|
||||
& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
|
||||
sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
|
||||
|
||||
if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
|
||||
do_fixup_by_path(blob, dspi0_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
} else {
|
||||
do_fixup_by_path(blob, esdhc0_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
do_fixup_by_path(blob, dspi0_path, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
}
|
||||
|
||||
/* Check RCW field sdhc2_base_pmux to enable/disable
|
||||
* esdhc1/dspi1 DT node
|
||||
*/
|
||||
sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
|
||||
& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
|
||||
sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
|
||||
|
||||
if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
|
||||
do_fixup_by_path(blob, dspi1_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
} else {
|
||||
do_fixup_by_path(blob, esdhc1_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
do_fixup_by_path(blob, dspi1_path, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
}
|
||||
|
||||
/* Check RCW field IIC5 to enable dspi2 DT node */
|
||||
iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
|
||||
& FSL_CHASSIS3_IIC5_PMUX_MASK;
|
||||
iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
|
||||
|
||||
if (iic5_pmux == IIC5_PMUX_SPI3) {
|
||||
do_fixup_by_path(blob, dspi2_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
int esdhc_status_fixup(void *blob, const char *compat)
|
||||
{
|
||||
#if defined(CONFIG_TARGET_LX2160AQDS)
|
||||
/* Enable esdhc and dspi DT nodes based on RCW fields */
|
||||
esdhc_dspi_status_fixup(blob);
|
||||
#else
|
||||
/* Enable both esdhc DT nodes for LX2160ARDB */
|
||||
do_fixup_by_compat(blob, compat, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -125,9 +205,20 @@ int checkboard(void)
|
|||
enum boot_src src = get_boot_src();
|
||||
char buf[64];
|
||||
u8 sw;
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
int clock;
|
||||
static const char *const freq[] = {"100", "125", "156.25",
|
||||
"161.13", "322.26", "", "", "",
|
||||
"", "", "", "", "", "", "",
|
||||
"100 separate SSCG"};
|
||||
#endif
|
||||
|
||||
cpu_name(buf);
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
printf("Board: %s-QDS, ", buf);
|
||||
#else
|
||||
printf("Board: %s-RDB, ", buf);
|
||||
#endif
|
||||
|
||||
sw = QIXIS_READ(arch);
|
||||
printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
|
||||
|
|
@ -154,22 +245,206 @@ int checkboard(void)
|
|||
break;
|
||||
}
|
||||
}
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
printf("FPGA: v%d (%s), build %d",
|
||||
(int)QIXIS_READ(scver), qixis_read_tag(buf),
|
||||
(int)qixis_read_minor());
|
||||
/* the timestamp string contains "\n" at the end */
|
||||
printf(" on %s", qixis_read_time(buf));
|
||||
|
||||
puts("SERDES1 Reference : ");
|
||||
sw = QIXIS_READ(brdcfg[2]);
|
||||
clock = sw >> 4;
|
||||
printf("Clock1 = %sMHz ", freq[clock]);
|
||||
clock = sw & 0x0f;
|
||||
printf("Clock2 = %sMHz", freq[clock]);
|
||||
|
||||
sw = QIXIS_READ(brdcfg[3]);
|
||||
puts("\nSERDES2 Reference : ");
|
||||
clock = sw >> 4;
|
||||
printf("Clock1 = %sMHz ", freq[clock]);
|
||||
clock = sw & 0x0f;
|
||||
printf("Clock2 = %sMHz", freq[clock]);
|
||||
|
||||
sw = QIXIS_READ(brdcfg[12]);
|
||||
puts("\nSERDES3 Reference : ");
|
||||
clock = sw >> 4;
|
||||
printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
|
||||
#else
|
||||
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
|
||||
|
||||
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
|
||||
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
|
||||
puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
/*
|
||||
* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
|
||||
*/
|
||||
u8 qixis_esdhc_detect_quirk(void)
|
||||
{
|
||||
/* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
|
||||
* SDHC1 Card ID:
|
||||
* Specifies the type of card installed in the SDHC1 adapter slot.
|
||||
* 000= (reserved)
|
||||
* 001= eMMC V4.5 adapter is installed.
|
||||
* 010= SD/MMC 3.3V adapter is installed.
|
||||
* 011= eMMC V4.4 adapter is installed.
|
||||
* 100= eMMC V5.0 adapter is installed.
|
||||
* 101= MMC card/Legacy (3.3V) adapter is installed.
|
||||
* 110= SDCard V2/V3 adapter installed.
|
||||
* 111= no adapter is installed.
|
||||
*/
|
||||
return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
|
||||
QIXIS_ESDHC_NO_ADAPTER);
|
||||
}
|
||||
|
||||
int config_board_mux(void)
|
||||
{
|
||||
u8 reg11, reg5, reg13;
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 sdhc1_base_pmux;
|
||||
u32 sdhc2_base_pmux;
|
||||
u32 iic5_pmux;
|
||||
|
||||
/* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
|
||||
* Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
|
||||
* Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
|
||||
* Qixis and remote systems are isolated from the I2C1 bus.
|
||||
* Processor connections are still available.
|
||||
* SPI2 CS2_B controls EN25S64 SPI memory device.
|
||||
* SPI3 CS2_B controls EN25S64 SPI memory device.
|
||||
* EC2 connects to PHY #2 using RGMII protocol.
|
||||
* CLK_OUT connects to FPGA for clock measurement.
|
||||
*/
|
||||
|
||||
reg5 = QIXIS_READ(brdcfg[5]);
|
||||
reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
|
||||
QIXIS_WRITE(brdcfg[5], reg5);
|
||||
|
||||
/* Check RCW field sdhc1_base_pmux
|
||||
* esdhc0 : sdhc1_base_pmux = 0
|
||||
* dspi0 : sdhc1_base_pmux = 2
|
||||
*/
|
||||
sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
|
||||
& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
|
||||
sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
|
||||
|
||||
if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
} else {
|
||||
/* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
|
||||
* {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
|
||||
* {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
|
||||
*/
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
}
|
||||
|
||||
/* Check RCW field sdhc2_base_pmux
|
||||
* esdhc1 : sdhc2_base_pmux = 0 (default)
|
||||
* dspi1 : sdhc2_base_pmux = 2
|
||||
*/
|
||||
sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
|
||||
& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
|
||||
sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
|
||||
|
||||
if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
|
||||
reg13 = QIXIS_READ(brdcfg[13]);
|
||||
reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
|
||||
QIXIS_WRITE(brdcfg[13], reg13);
|
||||
} else {
|
||||
reg13 = QIXIS_READ(brdcfg[13]);
|
||||
reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
|
||||
QIXIS_WRITE(brdcfg[13], reg13);
|
||||
}
|
||||
|
||||
/* Check RCW field IIC5 to enable dspi2 DT nodei
|
||||
* dspi2: IIC5 = 3
|
||||
*/
|
||||
iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
|
||||
& FSL_CHASSIS3_IIC5_PMUX_MASK;
|
||||
iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
|
||||
|
||||
if (iic5_pmux == IIC5_PMUX_SPI3) {
|
||||
/* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
|
||||
/* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
|
||||
* {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
|
||||
* {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
|
||||
*/
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
} else {
|
||||
/* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
|
||||
/* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
|
||||
* {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
|
||||
* {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
|
||||
*/
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int config_board_mux(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
unsigned long get_board_sys_clk(void)
|
||||
{
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
|
||||
|
||||
switch (sysclk_conf & 0x03) {
|
||||
case QIXIS_SYSCLK_100:
|
||||
return 100000000;
|
||||
case QIXIS_SYSCLK_125:
|
||||
return 125000000;
|
||||
case QIXIS_SYSCLK_133:
|
||||
return 133333333;
|
||||
}
|
||||
return 100000000;
|
||||
#else
|
||||
return 100000000;
|
||||
#endif
|
||||
}
|
||||
|
||||
unsigned long get_board_ddr_clk(void)
|
||||
{
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
|
||||
|
||||
switch ((ddrclk_conf & 0x30) >> 4) {
|
||||
case QIXIS_DDRCLK_100:
|
||||
return 100000000;
|
||||
case QIXIS_DDRCLK_125:
|
||||
return 125000000;
|
||||
case QIXIS_DDRCLK_133:
|
||||
return 133333333;
|
||||
}
|
||||
return 100000000;
|
||||
#else
|
||||
return 100000000;
|
||||
#endif
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
|
|
@ -202,6 +477,8 @@ void detail_board_ddr_info(void)
|
|||
#if defined(CONFIG_ARCH_MISC_INIT)
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
config_board_mux();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
58
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
Normal file
58
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LX2160AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_AQUANTIA=y
|
||||
CONFIG_PHY_CORTINA=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_SOFTWARE_EXP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
53
configs/lx2160aqds_tfa_defconfig
Normal file
53
configs/lx2160aqds_tfa_defconfig
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LX2160AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_AQUANTIA=y
|
||||
CONFIG_PHY_CORTINA=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
140
include/configs/lx2160aqds.h
Normal file
140
include/configs/lx2160aqds.h
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __LX2_QDS_H
|
||||
#define __LX2_QDS_H
|
||||
|
||||
#include "lx2160a_common.h"
|
||||
|
||||
/* Qixis */
|
||||
#define QIXIS_XMAP_MASK 0x07
|
||||
#define QIXIS_XMAP_SHIFT 5
|
||||
#define QIXIS_RST_CTL_RESET_EN 0x30
|
||||
#define QIXIS_LBMAP_DFLTBANK 0x00
|
||||
#define QIXIS_LBMAP_ALTBANK 0x20
|
||||
#define QIXIS_LBMAP_QSPI 0x00
|
||||
#define QIXIS_RCW_SRC_QSPI 0xff
|
||||
#define QIXIS_RST_CTL_RESET 0x31
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
||||
#define QIXIS_LBMAP_MASK 0x0f
|
||||
#define QIXIS_LBMAP_SD
|
||||
#define QIXIS_RCW_SRC_SD 0x08
|
||||
#define NON_EXTENDED_DUTCFG
|
||||
#define QIXIS_SDID_MASK 0x07
|
||||
#define QIXIS_ESDHC_NO_ADAPTER 0x7
|
||||
|
||||
/* SYSCLK */
|
||||
#define QIXIS_SYSCLK_100 0x0
|
||||
#define QIXIS_SYSCLK_125 0x1
|
||||
#define QIXIS_SYSCLK_133 0x2
|
||||
|
||||
/* DDRCLK */
|
||||
#define QIXIS_DDRCLK_100 0x0
|
||||
#define QIXIS_DDRCLK_125 0x1
|
||||
#define QIXIS_DDRCLK_133 0x2
|
||||
|
||||
#define BRDCFG4_EMI1SEL_MASK 0xF8
|
||||
#define BRDCFG4_EMI1SEL_SHIFT 3
|
||||
#define BRDCFG4_EMI2SEL_MASK 0x07
|
||||
#define BRDCFG4_EMI2SEL_SHIFT 0
|
||||
|
||||
/* VID */
|
||||
|
||||
#define I2C_MUX_CH_VOL_MONITOR 0xA
|
||||
/* Voltage monitor on channel 2*/
|
||||
#define I2C_VOL_MONITOR_ADDR 0x63
|
||||
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
|
||||
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
|
||||
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
|
||||
#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
|
||||
#define CONFIG_VID
|
||||
|
||||
/* The lowest and highest voltage allowed*/
|
||||
#define VDD_MV_MIN 775
|
||||
#define VDD_MV_MAX 925
|
||||
|
||||
/* PM Bus commands code for LTC3882*/
|
||||
#define PMBUS_CMD_PAGE 0x0
|
||||
#define PMBUS_CMD_READ_VOUT 0x8B
|
||||
#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
|
||||
#define PMBUS_CMD_VOUT_COMMAND 0x21
|
||||
#define PWM_CHANNEL0 0x0
|
||||
|
||||
#define CONFIG_VOL_MONITOR_LTC3882_SET
|
||||
#define CONFIG_VOL_MONITOR_LTC3882_READ
|
||||
|
||||
/* RTC */
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 0
|
||||
#define I2C_MUX_CH_RTC 0xB
|
||||
|
||||
/*
|
||||
* MMC
|
||||
*/
|
||||
#ifdef CONFIG_MMC
|
||||
#ifndef __ASSEMBLY__
|
||||
u8 qixis_esdhc_detect_quirk(void);
|
||||
#endif
|
||||
#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
|
||||
#endif
|
||||
|
||||
/* MAC/PHY configuration */
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
|
||||
|
||||
#define AQ_PHY_ADDR1 0x00
|
||||
#define AQ_PHY_ADDR2 0x01
|
||||
#define AQ_PHY_ADDR3 0x02
|
||||
#define AQ_PHY_ADDR4 0x03
|
||||
|
||||
#define CORTINA_NO_FW_UPLOAD
|
||||
#define CORTINA_PHY_ADDR1 0x0
|
||||
|
||||
#define INPHI_PHY_ADDR1 0x0
|
||||
#define INPHI_PHY_ADDR2 0x1
|
||||
|
||||
#define RGMII_PHY_ADDR1 0x01
|
||||
#define RGMII_PHY_ADDR2 0x02
|
||||
|
||||
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
|
||||
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
|
||||
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
|
||||
|
||||
#endif
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
EXTRA_ENV_SETTINGS \
|
||||
"lx2160aqds_vdd_mv=800\0" \
|
||||
"BOARD=lx2160aqds\0" \
|
||||
"xspi_bootcmd=echo Trying load from flexspi..;" \
|
||||
"sf probe 0:0 && sf read $load_addr " \
|
||||
"$kernel_start $kernel_size ; env exists secureboot &&" \
|
||||
"sf read $kernelheader_addr_r $kernelheader_start " \
|
||||
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
|
||||
" bootm $load_addr#$BOARD\0" \
|
||||
"sd_bootcmd=echo Trying load from sd card..;" \
|
||||
"mmcinfo; mmc read $load_addr " \
|
||||
"$kernel_addr_sd $kernel_size_sd ;" \
|
||||
"env exists secureboot && mmc read $kernelheader_addr_r "\
|
||||
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
|
||||
" && esbc_validate ${kernelheader_addr_r};" \
|
||||
"bootm $load_addr#$BOARD\0"
|
||||
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#endif /* __LX2_QDS_H */
|
||||
Loading…
Reference in a new issue