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usb: UniPhier: add UniPhier on-chip xHCI host driver support
Support xHCI host driver used on Panasonic UniPhier platform. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
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parent
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commit
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6 changed files with 98 additions and 1 deletions
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@ -73,7 +73,8 @@ Supported devices
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- UART (on-chip)
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- UART (on-chip)
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- NAND
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- NAND
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- USB (2.0)
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- USB 2.0 (EHCI)
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- USB 3.0 (xHCI)
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- LAN (on-board SMSC9118)
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- LAN (on-board SMSC9118)
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- I2C
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- I2C
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- EEPROM (connected to the on-board I2C bus)
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- EEPROM (connected to the on-board I2C bus)
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@ -17,6 +17,14 @@ config USB_XHCI
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if USB_XHCI_HCD
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if USB_XHCI_HCD
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config USB_XHCI_UNIPHIER
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bool "Support for Panasonic UniPhier on-chip xHCI USB controller"
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depends on ARCH_UNIPHIER
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default y
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---help---
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Enables support for the on-chip xHCI controller on Panasonic
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UniPhier SoCs.
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endif
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endif
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config USB_EHCI_HCD
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config USB_EHCI_HCD
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@ -48,6 +48,7 @@ obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
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obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
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obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
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obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
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obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
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obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
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obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
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obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
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# designware
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# designware
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obj-$(CONFIG_USB_DWC2) += dwc2.o
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obj-$(CONFIG_USB_DWC2) += dwc2.o
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85
drivers/usb/host/xhci-uniphier.c
Normal file
85
drivers/usb/host/xhci-uniphier.c
Normal file
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@ -0,0 +1,85 @@
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/*
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* Copyright (C) 2015 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/err.h>
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#include <usb.h>
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#include <fdtdec.h>
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#include "xhci.h"
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static int get_uniphier_xhci_base(int index, struct xhci_hccr **base)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int node_list[2];
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fdt_addr_t addr;
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int count;
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count = fdtdec_find_aliases_for_id(gd->fdt_blob, "usb",
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COMPAT_PANASONIC_XHCI, node_list,
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ARRAY_SIZE(node_list));
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if (index >= count)
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return -ENODEV;
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addr = fdtdec_get_addr(gd->fdt_blob, node_list[index], "reg");
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if (addr == FDT_ADDR_T_NONE)
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return -ENODEV;
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*base = (struct xhci_hccr *)addr;
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return 0;
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}
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#define USB3_RST_CTRL 0x00100040
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#define IOMMU_RST_N (1 << 5)
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#define LINK_RST_N (1 << 4)
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static void uniphier_xhci_reset(void __iomem *base, int on)
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{
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u32 tmp;
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tmp = readl(base + USB3_RST_CTRL);
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if (on)
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tmp &= ~(IOMMU_RST_N | LINK_RST_N);
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else
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tmp |= IOMMU_RST_N | LINK_RST_N;
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writel(tmp, base + USB3_RST_CTRL);
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}
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
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{
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int ret;
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struct xhci_hccr *cr;
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struct xhci_hcor *or;
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ret = get_uniphier_xhci_base(index, &cr);
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if (ret < 0)
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return ret;
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uniphier_xhci_reset(cr, 0);
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or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));
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*hccr = cr;
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*hcor = or;
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return 0;
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}
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void xhci_hcd_stop(int index)
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{
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int ret;
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struct xhci_hccr *cr;
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ret = get_uniphier_xhci_base(index, &cr);
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if (ret < 0)
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return;
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uniphier_xhci_reset(cr, 1);
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}
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@ -168,6 +168,7 @@ enum fdt_compat_id {
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COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
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COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
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COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */
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COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */
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COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
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COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
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COMPAT_PANASONIC_XHCI, /* Panasonic UniPhier xHCI */
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COMPAT_COUNT,
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COMPAT_COUNT,
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};
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};
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@ -76,6 +76,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
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COMPAT(AMS_AS3722, "ams,as3722"),
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COMPAT(AMS_AS3722, "ams,as3722"),
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COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
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COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
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COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
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COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
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COMPAT(PANASONIC_XHCI, "panasonic,uniphier-xhci"),
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};
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};
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const char *fdtdec_get_compatible(enum fdt_compat_id id)
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const char *fdtdec_get_compatible(enum fdt_compat_id id)
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