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PPC4xx:HCU4/5 cleanup ecc/sdram init
Make ecc initialisation robust, as DDR2-ECC errors may be generated while zeroing the RAM. Return 16 bytes (a cacheline) less than the available memory, as the board and/or PPC440EPx might have problems accessing the last bytes. Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
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1e6b07c649
1 changed files with 12 additions and 3 deletions
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@ -36,7 +36,7 @@
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#include <asm/mmu.h>
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#include <ppc440.h>
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void sysLedSet(u32 value);
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void hcu_led_set(u32 value);
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void dcbz_area(u32 start_address, u32 num_bytes);
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void dflush(void);
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@ -138,7 +138,7 @@ static int wait_for_dlllock(void)
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void sdram_panic(const char *reason)
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{
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printf("\n%s: reason %s", __FUNCTION__, reason);
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sysLedSet(0xff);
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hcu_led_set(0xff);
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while (1) {
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}
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/* Never return */
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@ -197,6 +197,13 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes,
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mfsdram(DDR0_00, val);
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mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
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/*
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* Clear possible errors
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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mtspr(mcsr, mfspr(mcsr));
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/* Set 'int_mask' parameter to functionnal value */
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mfsdram(DDR0_01, val);
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mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
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@ -244,7 +251,6 @@ long int initdram (int board_type)
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sdram_panic(INVALID_HW_CONFIG);
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break;
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}
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dram_size -= 16 * 1024 * 1024;
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mtsdram(DDR0_07, 0x00090100);
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/*
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* TCPD=200 cycles of clock input is required to lock the DLL.
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@ -283,6 +289,7 @@ long int initdram (int board_type)
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/*
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* Program tlb entries for this size (dynamic)
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*/
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remove_tlb(CFG_SDRAM_BASE, 256 << 20);
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program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
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/*
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@ -291,6 +298,8 @@ long int initdram (int board_type)
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*/
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program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
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/* Diminish RAM to initialize */
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dram_size = dram_size - 32 ;
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#ifdef CONFIG_DDR_ECC
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/*
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* If ECC is enabled, initialize the parity bits.
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