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treewide: Enable SPL_SEPARATE_BSS if SPL_BSS_START_ADDR is used

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If .bss does not immediately follow the end of the image, then
CONFIG_SPL_SEPARATE_BSS must be selected. Typically, the location of bss
is specified by using CONFIG_SPL_BSS_START_ADDR in a linker script. On
these arches, CONFIG_SPL_SEPARATE_BSS should be enabled. If there is an
option to use an alternate boot script (e.g. CONFIG_SPL_LDSCRIPT is just
a default), just imply. If there is not, select.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
This commit is contained in:
Sean Anderson 2022-04-12 10:59:04 -04:00 committed by Tom Rini
parent a95cd68d51
commit 1dd56db5e0
2 changed files with 8 additions and 0 deletions
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2
arch/Kconfig
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@ -85,6 +85,7 @@ config MIPS
select HAVE_ARCH_IOREMAP
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
select SPL_SEPARATE_BSS if SPL
config NDS32
bool "NDS32 architecture"
@ -112,6 +113,7 @@ config RISCV
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
select SPL_SEPARATE_BSS if SPL
imply DM_SERIAL
imply DM_ETH
imply DM_EVENT

6
arch/arm/Kconfig
View file

@ -8,6 +8,7 @@ config ARM64
bool
select PHYS_64BIT
select SYS_CACHE_SHIFT_6
imply SPL_SEPARATE_BSS
config ARM64_CRC32
bool "Enable support for CRC32 instruction"
@ -267,6 +268,7 @@ config CPU_ARM926EJS
bool
select SYS_CACHE_SHIFT_5
imply SYS_ARM_MMU
imply SPL_SEPARATE_BSS
config CPU_ARM946ES
bool
@ -277,6 +279,7 @@ config CPU_ARM1136
bool
select SYS_CACHE_SHIFT_5
imply SYS_ARM_MMU
imply SPL_SEPARATE_BSS
config CPU_ARM1176
bool
@ -624,6 +627,7 @@ config ARCH_ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select SPL_SEPARATE_BSS if SPL
config TARGET_STV0991
bool "Support stv0991"
@ -814,6 +818,7 @@ config ARCH_OMAP2PLUS
imply TI_SYSC if DM && OF_CONTROL
imply FIT
imply DM_EVENT
imply SPL_SEPARATE_BSS
config ARCH_MESON
bool "Amlogic Meson"
@ -957,6 +962,7 @@ config ARCH_MX6
select SYS_FSL_SEC_LE
imply MXC_GPIO
imply SYS_THUMB_BUILD
imply SPL_SEPARATE_BSS
if ARCH_MX6
config SPL_LDSCRIPT