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mpc512x: optionally configure DIU, LPC and NFC deviders
If a board config file defines DIU, LPC and NFC deviders, configure them in the SCFR1 register. Signed-off-by: Anatolij Gustschin <agust@denx.de>
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2 changed files with 21 additions and 0 deletions
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@ -172,6 +172,21 @@ void cpu_init_f (volatile immap_t * im)
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ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
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out_be32(&im->clk.scfr[0], ips_div);
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#ifdef SCFR1_LPC_DIV
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clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
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SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
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#endif
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#ifdef SCFR1_NFC_DIV
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clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK,
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SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT);
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#endif
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#ifdef SCFR1_DIU_DIV
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clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK,
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SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT);
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#endif
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/*
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* Enable Time Base/Decrementer
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*
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@ -238,6 +238,12 @@ typedef struct clk512x {
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#define SCFR1_LPC_DIV_MASK 0x00003800
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#define SCFR1_LPC_DIV_SHIFT 11
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#define SCFR1_NFC_DIV_MASK 0x00000700
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#define SCFR1_NFC_DIV_SHIFT 8
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#define SCFR1_DIU_DIV_MASK 0x000000FF
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#define SCFR1_DIU_DIV_SHIFT 0
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/* SCFR2 System Clock Frequency Register 2 */
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#define SCFR2_SYS_DIV 0xFC000000
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#define SCFR2_SYS_DIV_SHIFT 26
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