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ARM: uniphier: fix various sparse warnings

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Fix warnings reported by sparse:
 - ... was not declared. Should it be static?"
 - cast to restricted __be32

While fixing those, the type conflict of cci500_init() was found.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2017-06-22 16:42:04 +09:00
parent 431c66a3ba
commit 1d21e1b97c
10 changed files with 27 additions and 20 deletions
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2
arch/arm/mach-uniphier/arm64/arm-cci500.c
View file

@ -11,6 +11,8 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/sizes.h> #include <linux/sizes.h>
#include "../init.h"
#define CCI500_BASE 0x5FD00000 #define CCI500_BASE 0x5FD00000
#define CCI500_SLAVE_OFFSET 0x1000 #define CCI500_SLAVE_OFFSET 0x1000

2
arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
View file

@ -8,6 +8,8 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/sizes.h> #include <linux/sizes.h>
#include "../init.h"
#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200 #define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200
void uniphier_smp_setup(void); void uniphier_smp_setup(void);

2
arch/arm/mach-uniphier/board_init.c
View file

@ -21,7 +21,7 @@ static void uniphier_setup_xirq(void)
{ {
const void *fdt = gd->fdt_blob; const void *fdt = gd->fdt_blob;
int soc_node, aidet_node; int soc_node, aidet_node;
const u32 *val; const fdt32_t *val;
unsigned long aidet_base; unsigned long aidet_base;
u32 tmp; u32 tmp;

2
arch/arm/mach-uniphier/clk/pll-pxs3.c
View file

@ -2,6 +2,8 @@
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
#include "../init.h"
void uniphier_pxs3_pll_init(void) void uniphier_pxs3_pll_init(void)
{ {
} }

14
arch/arm/mach-uniphier/dram/umc-ld11.c
View file

@ -28,11 +28,11 @@ enum dram_size {
}; };
/* PHY */ /* PHY */
const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} }; static const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} }; static const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} }; static const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} }; static const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} }; static const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
/* Register address */ /* Register address */
#define PHY_ZQ0CR1 0x00000184 #define PHY_ZQ0CR1 0x00000184
@ -65,7 +65,7 @@ const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
#define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */ #define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */
#define PHY_DSDQOE_MASK 0x00000FFF #define PHY_DSDQOE_MASK 0x00000FFF
static void ddrphy_maskwritel(u32 data, u32 mask, void *addr) static void ddrphy_maskwritel(u32 data, u32 mask, void __iomem *addr)
{ {
u32 value; u32 value;
@ -73,7 +73,7 @@ static void ddrphy_maskwritel(u32 data, u32 mask, void *addr)
writel(value, addr); writel(value, addr);
} }
static u32 ddrphy_maskreadl(u32 mask, void *addr) static u32 ddrphy_maskreadl(u32 mask, void __iomem *addr)
{ {
return readl(addr) & mask; return readl(addr) & mask;
} }

2
arch/arm/mach-uniphier/dram/umc-pxs2.c
View file

@ -436,7 +436,7 @@ static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
} }
/* enable/disable auto refresh */ /* enable/disable auto refresh */
void umc_refresh_ctrl(void __iomem *dc_base, int enable) static void umc_refresh_ctrl(void __iomem *dc_base, int enable)
{ {
u32 tmp; u32 tmp;

1
arch/arm/mach-uniphier/dram_init.c
View file

@ -7,6 +7,7 @@
*/ */
#include <common.h> #include <common.h>
#include <fdt_support.h>
#include <fdtdec.h> #include <fdtdec.h>
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/sizes.h> #include <linux/sizes.h>

2
arch/arm/mach-uniphier/init.h
View file

@ -126,7 +126,7 @@ int uniphier_have_internal_stm(void);
int uniphier_boot_from_backend(void); int uniphier_boot_from_backend(void);
int uniphier_pin_init(const char *pinconfig_name); int uniphier_pin_init(const char *pinconfig_name);
void uniphier_smp_kick_all_cpus(void); void uniphier_smp_kick_all_cpus(void);
void cci500_init(int nr_slaves); void cci500_init(unsigned int nr_slaves);
#undef pr_warn #undef pr_warn
#define pr_warn(fmt, args...) printf(fmt, ##args) #define pr_warn(fmt, args...) printf(fmt, ##args)

2
drivers/clk/uniphier/clk-uniphier-core.c
View file

@ -121,7 +121,7 @@ static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
return best_rate; return best_rate;
} }
const struct clk_ops uniphier_clk_ops = { static const struct clk_ops uniphier_clk_ops = {
.enable = uniphier_clk_enable, .enable = uniphier_clk_enable,
.get_rate = uniphier_clk_get_rate, .get_rate = uniphier_clk_get_rate,
.set_rate = uniphier_clk_set_rate, .set_rate = uniphier_clk_set_rate,

18
drivers/reset/reset-uniphier.c
View file

@ -56,12 +56,12 @@ struct uniphier_reset_data {
#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \ #define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17) UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
UNIPHIER_RESET_END, UNIPHIER_RESET_END,
}; };
const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */
UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
@ -69,7 +69,7 @@ const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
UNIPHIER_RESET_END, UNIPHIER_RESET_END,
}; };
const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */
UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */ UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
@ -77,7 +77,7 @@ const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
UNIPHIER_RESET_END, UNIPHIER_RESET_END,
}; };
const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */ UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
@ -91,12 +91,12 @@ const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
UNIPHIER_RESET_END, UNIPHIER_RESET_END,
}; };
const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */ UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */
UNIPHIER_RESET_END, UNIPHIER_RESET_END,
}; };
const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */ UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */
UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */ UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
@ -125,7 +125,7 @@ const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
#define UNIPHIER_MIO_RESET_DMAC(id) \ #define UNIPHIER_MIO_RESET_DMAC(id) \
UNIPHIER_RESETX((id), 0x110, 17) UNIPHIER_RESETX((id), 0x110, 17)
const struct uniphier_reset_data uniphier_mio_reset_data[] = { static const struct uniphier_reset_data uniphier_mio_reset_data[] = {
UNIPHIER_MIO_RESET_SD(0, 0), UNIPHIER_MIO_RESET_SD(0, 0),
UNIPHIER_MIO_RESET_SD(1, 1), UNIPHIER_MIO_RESET_SD(1, 1),
UNIPHIER_MIO_RESET_SD(2, 2), UNIPHIER_MIO_RESET_SD(2, 2),
@ -155,7 +155,7 @@ const struct uniphier_reset_data uniphier_mio_reset_data[] = {
#define UNIPHIER_PERI_RESET_FI2C(id, ch) \ #define UNIPHIER_PERI_RESET_FI2C(id, ch) \
UNIPHIER_RESETX((id), 0x114, 24 + (ch)) UNIPHIER_RESETX((id), 0x114, 24 + (ch))
const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
UNIPHIER_PERI_RESET_UART(0, 0), UNIPHIER_PERI_RESET_UART(0, 0),
UNIPHIER_PERI_RESET_UART(1, 1), UNIPHIER_PERI_RESET_UART(1, 1),
UNIPHIER_PERI_RESET_UART(2, 2), UNIPHIER_PERI_RESET_UART(2, 2),
@ -168,7 +168,7 @@ const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
UNIPHIER_RESET_END, UNIPHIER_RESET_END,
}; };
const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
UNIPHIER_PERI_RESET_UART(0, 0), UNIPHIER_PERI_RESET_UART(0, 0),
UNIPHIER_PERI_RESET_UART(1, 1), UNIPHIER_PERI_RESET_UART(1, 1),
UNIPHIER_PERI_RESET_UART(2, 2), UNIPHIER_PERI_RESET_UART(2, 2),