Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-28 23:51:33 +00:00
Code Issues Projects Releases Packages Wiki Activity

powerpc/85xx: Add support for 4th PCI controller on corenet_ds

Browse source 
We configure the controller but dont have virtual address space thus any
devices on the 4th controller are not accessible in u-boot.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2010-07-09 09:12:18 -05:00
parent c2b3b6408b
commit 1bf8e9fd74
2 changed files with 35 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

28
board/freescale/corenet_ds/pci.c
View file

@ -40,10 +40,14 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
#ifdef CONFIG_PCIE4
static struct pci_controller pcie4_hose;
#endif
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct fsl_pci_info pci_info[3];
struct fsl_pci_info pci_info[4];
u32 devdisr;
int first_free_busno = 0;
int num = 0;
@ -119,6 +123,28 @@ void pci_init_board(void)
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE4
pcie_configured = is_serdes_configured(PCIE4);
if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) {
set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M,
LAW_TRGT_IF_PCIE_4);
set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K,
LAW_TRGT_IF_PCIE_4);
SET_STD_PCIE_INFO(pci_info[num], 4);
pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
printf(" PCIE4 connected to as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie4_hose, first_free_busno);
} else {
printf (" PCIE4: disabled\n");
}
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
#endif
}
void pci_of_setup(void *blob, bd_t *bd)

8
include/configs/corenet_ds.h
View file

@ -399,6 +399,14 @@
#endif
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000