From 1b6228f28d9336620fb508ed198ad8be1eb7aa9c Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 28 Dec 2023 08:30:24 +0100 Subject: [PATCH] cpu: riscv: set correct SMBIOS processor family value The SMBIOS specification requires to set the processor family in the type 4 (Processor Information) table to specific values depending only on the bitness of the system (0x200 for RV32 and 0x201 for RV64). With this patch dmidecode shows Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: Not Specified Type: Central Processor Family: RV64 for qemu-riscv64_smode_defconfig. Signed-off-by: Heinrich Schuchardt --- drivers/cpu/riscv_cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index d6484d7f4b..034b9b49c0 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -98,6 +98,10 @@ static int riscv_cpu_bind(struct udevice *dev) /* save the hart id */ plat->cpu_id = dev_read_addr(dev); + if (IS_ENABLED(CONFIG_64BIT)) + plat->family = 0x201; + else + plat->family = 0x200; /* first examine the property in current cpu node */ ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); /* if not found, then look at the parent /cpus node */