mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-16 05:58:49 +00:00
at91sam9263ek: add nor flash support
this will allow you to store use it for the env and to boot directly U-Boot from Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
parent
3294923297
commit
1b3b7c640d
6 changed files with 437 additions and 9 deletions
9
Makefile
9
Makefile
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@ -2754,6 +2754,8 @@ at91sam9261ek_config : unconfig
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fi;
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@$(MKCONFIG) -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91
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at91sam9263ek_norflash_config \
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at91sam9263ek_norflash_boot_config \
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at91sam9263ek_nandflash_config \
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at91sam9263ek_dataflash_config \
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at91sam9263ek_dataflash_cs0_config \
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@ -2762,10 +2764,17 @@ at91sam9263ek_config : unconfig
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@if [ "$(findstring _nandflash,$@)" ] ; then \
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echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
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$(XECHO) "... with environment variable in NAND FLASH" ; \
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elif [ "$(findstring norflash,$@)" ] ; then \
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echo "#define CONFIG_SYS_USE_NORFLASH 1" >>$(obj)include/config.h ; \
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$(XECHO) "... with environment variable in NOR FLASH" ; \
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else \
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echo "#define CONFIG_SYS_USE_DATAFLASH 1" >>$(obj)include/config.h ; \
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$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
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fi;
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@if [ "$(findstring norflash_boot,$@)" ] ; then \
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echo "#define CONFIG_SYS_USE_BOOT_NORFLASH 1" >>$(obj)include/config.h ; \
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$(XECHO) "... and boot from NOR FLASH" ; \
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fi;
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@$(MKCONFIG) -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91
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at91sam9rlek_nandflash_config \
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@ -32,10 +32,13 @@ LIB = $(obj)lib$(BOARD).a
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COBJS-y += at91sam9263ek.o
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COBJS-y += led.o
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COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
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ifndef CONFIG_SKIP_LOWLEVEL_INIT
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SOBJS-y += lowlevel_init.o
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endif
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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@ -196,9 +196,16 @@ static void at91sam9263ek_lcd_hw_init(void)
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#include <nand.h>
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#include <version.h>
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#ifndef CONFIG_SYS_NO_FLASH
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extern flash_info_t flash_info[];
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#endif
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void lcd_show_board_info(void)
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{
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ulong dram_size, nand_size;
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#ifndef CONFIG_SYS_NO_FLASH
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ulong flash_size;
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#endif
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int i;
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char temp[32];
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@ -215,9 +222,19 @@ void lcd_show_board_info(void)
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nand_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += nand_info[i].size;
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lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
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#ifndef CONFIG_SYS_NO_FLASH
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flash_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
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flash_size += flash_info[i].size;
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#endif
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lcd_printf (" %ld MB SDRAM, %ld MB NAND",
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dram_size >> 20,
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nand_size >> 20 );
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#ifndef CONFIG_SYS_NO_FLASH
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lcd_printf (",\n %ld MB NOR",
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flash_size >> 20);
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#endif
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lcd_puts ("\n");
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}
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#endif /* CONFIG_LCD_INFO */
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#endif
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264
board/atmel/at91sam9263ek/lowlevel_init.S
Normal file
264
board/atmel/at91sam9263ek/lowlevel_init.S
Normal file
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@ -0,0 +1,264 @@
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/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
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* Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_wdt.h>
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#include <asm/arch/at91sam9_sdramc.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91sam9263_matrix.h>
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_TEXT_BASE:
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.word TEXT_BASE
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.globl lowlevel_init
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.type lowlevel_init,function
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lowlevel_init:
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mov r5, pc /* r5 = POS1 + 4 current */
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POS1:
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ldr r0, =POS1 /* r0 = POS1 compile */
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ldr r2, _TEXT_BASE
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sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
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sub r5, r5, r0 /* r0 = TEXT_BASE-1 */
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sub r5, r5, #4 /* r1 = text base - current */
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/* memory control configuration 1 */
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ldr r0, =SMRDATA
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ldr r2, =SMRDATA1
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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sub r2, r2, r1
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add r0, r0, r5
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add r2, r2, r5
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0:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne 0b
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/* ----------------------------------------------------------------------------
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* PMC Init Step 1.
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* ----------------------------------------------------------------------------
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* - Check if the PLL is already initialized
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* ----------------------------------------------------------------------------
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*/
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ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
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ldr r0, [r1]
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and r0, r0, #3
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cmp r0, #0
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bne PLL_setup_end
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/* ---------------------------------------------------------------------------
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* - Enable the Main Oscillator
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* ---------------------------------------------------------------------------
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*/
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ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
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ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
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ldr r0, =CONFIG_SYS_MOR_VAL
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str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */
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/* Reading the PMC Status to detect when the Main Oscillator is enabled */
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mov r4, #AT91_PMC_MOSCS
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MOSCS_Loop:
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ldr r3, [r2]
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and r3, r4, r3
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cmp r3, #AT91_PMC_MOSCS
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bne MOSCS_Loop
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/* ----------------------------------------------------------------------------
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* PMC Init Step 2.
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* ----------------------------------------------------------------------------
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* Setup PLLA
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* ----------------------------------------------------------------------------
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*/
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ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
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ldr r0, =CONFIG_SYS_PLLAR_VAL
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str r0, [r1]
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/* Reading the PMC Status register to detect when the PLLA is locked */
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mov r4, #AT91_PMC_LOCKA
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MOSCS_Loop1:
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ldr r3, [r2]
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and r3, r4, r3
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cmp r3, #AT91_PMC_LOCKA
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bne MOSCS_Loop1
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/* ----------------------------------------------------------------------------
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* PMC Init Step 3.
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* ----------------------------------------------------------------------------
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* - Switch on the Main Oscillator 16.367 MHz
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* ----------------------------------------------------------------------------
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*/
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ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
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/* -Master Clock Controller register PMC_MCKR */
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ldr r0, =CONFIG_SYS_MCKR1_VAL
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str r0, [r1]
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/* Reading the PMC Status to detect when the Master clock is ready */
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mov r4, #AT91_PMC_MCKRDY
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MCKRDY_Loop:
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ldr r3, [r2]
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and r3, r4, r3
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cmp r3, #AT91_PMC_MCKRDY
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bne MCKRDY_Loop
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ldr r0, =CONFIG_SYS_MCKR2_VAL
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str r0, [r1]
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/* Reading the PMC Status to detect when the Master clock is ready */
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mov r4, #AT91_PMC_MCKRDY
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MCKRDY_Loop1:
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ldr r3, [r2]
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and r3, r4, r3
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cmp r3, #AT91_PMC_MCKRDY
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bne MCKRDY_Loop1
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PLL_setup_end:
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/* ----------------------------------------------------------------------------
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* - memory control configuration 2
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* ----------------------------------------------------------------------------
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*/
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ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
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ldr r1, [r0]
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cmp r1, #0
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bne SDRAM_setup_end
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ldr r0, =SMRDATA1
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ldr r2, =SMRDATA2
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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sub r2, r2, r1
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add r0, r0, r5
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add r2, r2, r5
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2:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne 2b
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SDRAM_setup_end:
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/* everything is fine now */
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mov pc, lr
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.ltorg
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SMRDATA:
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.word (AT91_BASE_SYS + AT91_WDT_MR)
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.word CONFIG_SYS_WDTC_WDMR_VAL
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.word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
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.word CONFIG_SYS_PIOD_PDR_VAL1
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.word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
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.word CONFIG_SYS_PIOD_PPUDR_VAL
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.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
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.word CONFIG_SYS_PIOD_PPUDR_VAL
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.word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
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.word CONFIG_SYS_MATRIX_EBI0CSA_VAL
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/* flash */
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.word (AT91_BASE_SYS + AT91_SMC_MODE(0))
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.word CONFIG_SYS_SMC0_MODE0_VAL
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.word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
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.word CONFIG_SYS_SMC0_CYCLE0_VAL
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.word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
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.word CONFIG_SYS_SMC0_PULSE0_VAL
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.word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
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.word CONFIG_SYS_SMC0_SETUP0_VAL
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SMRDATA1:
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.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
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.word CONFIG_SYS_SDRC_MR_VAL1
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.word (AT91_BASE_SYS + AT91_SDRAMC_TR)
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.word CONFIG_SYS_SDRC_TR_VAL1
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.word (AT91_BASE_SYS + AT91_SDRAMC_CR)
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.word CONFIG_SYS_SDRC_CR_VAL
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.word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
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.word CONFIG_SYS_SDRC_MDR_VAL
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.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
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.word CONFIG_SYS_SDRC_MR_VAL2
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL1
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.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
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.word CONFIG_SYS_SDRC_MR_VAL3
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL2
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL3
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL4
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL5
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL6
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL7
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL8
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL9
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.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
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.word CONFIG_SYS_SDRC_MR_VAL4
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL10
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.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
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.word CONFIG_SYS_SDRC_MR_VAL5
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL11
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.word (AT91_BASE_SYS + AT91_SDRAMC_TR)
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.word CONFIG_SYS_SDRC_TR_VAL2
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.word AT91_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL12
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/* User reset enable*/
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.word (AT91_BASE_SYS + AT91_RSTC_MR)
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.word CONFIG_SYS_RSTC_RMR_VAL
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#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
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/* MATRIX_MCFG - REMAP all masters */
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.word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)
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.word 0x1FF
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#endif
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SMRDATA2:
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.word 0
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@ -62,11 +62,16 @@ Environment variables
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U-Boot environment variables can be stored at different places:
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- Dataflash on SPI chip select 0 (dataflash card)
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- Nand flash.
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- Nor falsh (not populate by default)
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You can choose your storage location at config step (here for at91sam9260ek) :
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make at91sam9263ek_config - use data flash (spi cs0) (default)
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make at91sam9263ek_nandflash_config - use nand flash
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make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0)
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make at91sam9263ek_norflash_config - use nor falsh
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You can choose to boot directly from U-Boot at config step
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make at91sam9263ek_norflash_boot_config - boot from nor falsh
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------------------------------------------------------------------------------
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@ -41,8 +41,10 @@
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SKIP_RELOCATE_UBOOT
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#endif
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/*
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* Hardware drivers
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@ -113,15 +115,143 @@
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#define DATAFLASH_TCHS (0x1 << 24)
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/* NOR flash, if populated */
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#if 1
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#define CONFIG_SYS_NO_FLASH 1
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#else
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#ifdef CONFIG_SYS_USE_NORFLASH
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define PHYS_FLASH_1 0x10000000
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define PHYS_FLASH_1 0x10000000
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MONITOR_SEC 1:0-3
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000)
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
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/* Address and size of Primary Environment Sector */
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#define CONFIG_ENV_SIZE 0x2000
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#define xstr(s) str(s)
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#define str(s) #s
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
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"update=" \
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"protect off ${monitor_base} +${filesize};" \
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"erase ${monitor_base} +${filesize};" \
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"cp.b ${load_addr} ${monitor_base} ${filesize};" \
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"protect on ${monitor_base} +${filesize}\0"
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define MASTER_PLL_MUL 171
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#define MASTER_PLL_DIV 14
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|
||||
/* clocks */
|
||||
#define CONFIG_SYS_MOR_VAL \
|
||||
(AT91_PMC_MOSCEN | \
|
||||
(255 << 8)) /* Main Oscillator Start-up Time */
|
||||
#define CONFIG_SYS_PLLAR_VAL \
|
||||
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
|
||||
AT91_PMC_OUT | \
|
||||
AT91_PMC_PLLCOUNT | /* PLL Counter */ \
|
||||
(2 << 28) | /* PLL Clock Frequency Range */ \
|
||||
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
|
||||
|
||||
/* PCK/2 = MCK Master Clock from PLLA */
|
||||
#define CONFIG_SYS_MCKR1_VAL \
|
||||
(AT91_PMC_CSS_SLOW | \
|
||||
AT91_PMC_PRES_1 | \
|
||||
AT91SAM9_PMC_MDIV_2 | \
|
||||
AT91_PMC_PDIV_1)
|
||||
/* PCK/2 = MCK Master Clock from PLLA */
|
||||
#define CONFIG_SYS_MCKR2_VAL \
|
||||
(AT91_PMC_CSS_PLLA | \
|
||||
AT91_PMC_PRES_1 | \
|
||||
AT91SAM9_PMC_MDIV_2 | \
|
||||
AT91_PMC_PDIV_1)
|
||||
|
||||
/* define PDC[31:16] as DATA[31:16] */
|
||||
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
|
||||
/* no pull-up for D[31:16] */
|
||||
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
|
||||
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
|
||||
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
|
||||
(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
|
||||
AT91_MATRIX_EBI0_CS1A_SDRAMC)
|
||||
|
||||
/* SDRAM */
|
||||
/* SDRAMC_MR Mode register */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL1 0
|
||||
/* SDRAMC_TR - Refresh Timer register */
|
||||
#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
|
||||
/* SDRAMC_CR - Configuration register*/
|
||||
#define CONFIG_SYS_SDRC_CR_VAL \
|
||||
(AT91_SDRAMC_NC_9 | \
|
||||
AT91_SDRAMC_NR_13 | \
|
||||
AT91_SDRAMC_NB_4 | \
|
||||
AT91_SDRAMC_CAS_3 | \
|
||||
AT91_SDRAMC_DBW_32 | \
|
||||
(1 << 8) | /* Write Recovery Delay */ \
|
||||
(7 << 12) | /* Row Cycle Delay */ \
|
||||
(2 << 16) | /* Row Precharge Delay */ \
|
||||
(2 << 20) | /* Row to Column Delay */ \
|
||||
(5 << 24) | /* Active to Precharge Delay */ \
|
||||
(1 << 28)) /* Exit Self Refresh to Active Delay */
|
||||
|
||||
/* Memory Device Register -> SDRAM */
|
||||
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
|
||||
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
|
||||
#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
|
||||
#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
|
||||
#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
|
||||
#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
|
||||
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
|
||||
#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
|
||||
|
||||
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
|
||||
#define CONFIG_SYS_SMC0_SETUP0_VAL \
|
||||
(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
|
||||
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
|
||||
#define CONFIG_SYS_SMC0_PULSE0_VAL \
|
||||
(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
|
||||
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
|
||||
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
|
||||
(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
|
||||
#define CONFIG_SYS_SMC0_MODE0_VAL \
|
||||
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
|
||||
AT91_SMC_DBW_16 | \
|
||||
AT91_SMC_TDFMODE | \
|
||||
AT91_SMC_TDF_(6))
|
||||
|
||||
/* user reset enable */
|
||||
#define CONFIG_SYS_RSTC_RMR_VAL \
|
||||
(AT91_RSTC_KEY | \
|
||||
AT91_RSTC_PROCRST | \
|
||||
AT91_RSTC_RSTTYP_WAKEUP | \
|
||||
AT91_RSTC_RSTTYP_WATCHDOG)
|
||||
|
||||
/* Disable Watchdog */
|
||||
#define CONFIG_SYS_WDTC_WDMR_VAL \
|
||||
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
|
||||
AT91_WDT_WDV | \
|
||||
AT91_WDT_WDDIS | \
|
||||
AT91_WDT_WDD)
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define CONFIG_SYS_NO_FLASH 1
|
||||
#endif
|
||||
|
||||
/* NAND flash */
|
||||
|
|
@ -175,7 +305,7 @@
|
|||
"mtdparts=at91_nand:-(root) "\
|
||||
"rw rootfstype=jffs2"
|
||||
|
||||
#else /* CONFIG_SYS_USE_NANDFLASH */
|
||||
#elif CONFIG_SYS_USE_NANDFLASH
|
||||
|
||||
/* bootstrap + u-boot + env + linux in nandflash */
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue