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mtd: spi-nor-core: Fix address width on flash chips > 16MB

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If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.

The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.

Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c677502.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Pratyush Yadav 2021-06-26 00:47:10 +05:30 • committed by Jagan Teki
parent 38b0852b0e
commit 1af0334ab4
1 changed files with 5 additions and 3 deletions
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8
drivers/mtd/spi/spi-nor-core.c
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@ -2603,7 +2603,11 @@ int spi_nor_scan(struct spi_nor *nor)
/* already configured from SFDP */
} else if (info->addr_width) {
nor->addr_width = info->addr_width;
} else if (mtd->size > SZ_16M) {
} else {
nor->addr_width = 3;
}
if (nor->addr_width == 3 && mtd->size > SZ_16M) {
#ifndef CONFIG_SPI_FLASH_BAR
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
@ -2617,8 +2621,6 @@ int spi_nor_scan(struct spi_nor *nor)
if (ret < 0)
return ret;
#endif
} else {
nor->addr_width = 3;
}
if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {