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ram: k3-ddrss: Add support for multiple instances of DDR subsystems

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The current driver only supports single instance of DRR subsystem. Add
support for probing multiple instances of DDR subsystem.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
This commit is contained in:
Aswath Govindraju 2022-01-25 20:56:29 +05:30 • committed by Tom Rini
parent 3e3d836f92
commit 1a99bec018
1 changed files with 87 additions and 51 deletions
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138
drivers/ram/k3-ddrss/k3-ddrss.c
View file

@ -30,6 +30,9 @@
#define DDRSS_V2A_R1_MAT_REG 0x0020 #define DDRSS_V2A_R1_MAT_REG 0x0020
#define DDRSS_ECC_CTRL_REG 0x0120 #define DDRSS_ECC_CTRL_REG 0x0120
#define SINGLE_DDR_SUBSYSTEM 0x1
#define MULTI_DDR_SUBSYSTEM 0x2
struct k3_ddrss_desc { struct k3_ddrss_desc {
struct udevice *dev; struct udevice *dev;
void __iomem *ddrss_ss_cfg; void __iomem *ddrss_ss_cfg;
@ -42,14 +45,12 @@ struct k3_ddrss_desc {
u32 ddr_freq2; u32 ddr_freq2;
u32 ddr_fhs_cnt; u32 ddr_fhs_cnt;
struct udevice *vtt_supply; struct udevice *vtt_supply;
u32 instance;
lpddr4_obj *driverdt;
lpddr4_config config;
lpddr4_privatedata pd;
}; };
static lpddr4_obj *driverdt;
static lpddr4_config config;
static lpddr4_privatedata pd;
static struct k3_ddrss_desc *ddrss;
struct reginitdata { struct reginitdata {
u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT]; u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT]; u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
@ -83,15 +84,16 @@ struct reginitdata {
offset = offset * 10 + (*i - '0'); } \ offset = offset * 10 + (*i - '0'); } \
} while (0) } while (0)
static u32 k3_lpddr4_read_ddr_type(void) static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd)
{ {
u32 status = 0U; u32 status = 0U;
u32 offset = 0U; u32 offset = 0U;
u32 regval = 0U; u32 regval = 0U;
u32 dram_class = 0U; u32 dram_class = 0U;
struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset); TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval); status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
if (status > 0U) { if (status > 0U) {
printf("%s: Failed to read DRAM_CLASS\n", __func__); printf("%s: Failed to read DRAM_CLASS\n", __func__);
hang(); hang();
@ -102,23 +104,23 @@ static u32 k3_lpddr4_read_ddr_type(void)
return dram_class; return dram_class;
} }
static void k3_lpddr4_freq_update(void) static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
{ {
unsigned int req_type, counter; unsigned int req_type, counter;
for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) { for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr + if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80, CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
true, 10000, false)) { true, 10000, false)) {
printf("Timeout during frequency handshake\n"); printf("Timeout during frequency handshake\n");
hang(); hang();
} }
req_type = readl(ddrss->ddrss_ctrl_mmr + req_type = readl(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03; CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10) & 0x03;
debug("%s: received freq change req: req type = %d, req no. = %d\n", debug("%s: received freq change req: req type = %d, req no. = %d, instance = %d\n",
__func__, req_type, counter); __func__, req_type, counter, ddrss->instance);
if (req_type == 1) if (req_type == 1)
clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
@ -132,31 +134,32 @@ static void k3_lpddr4_freq_update(void)
printf("%s: Invalid freq request type\n", __func__); printf("%s: Invalid freq request type\n", __func__);
writel(0x1, ddrss->ddrss_ctrl_mmr + writel(0x1, ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS); CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr + if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80, CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS + ddrss->instance * 0x10, 0x80,
false, 10, false)) { false, 10, false)) {
printf("Timeout during frequency handshake\n"); printf("Timeout during frequency handshake\n");
hang(); hang();
} }
writel(0x0, ddrss->ddrss_ctrl_mmr + writel(0x0, ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS); CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance * 0x10);
} }
} }
static void k3_lpddr4_ack_freq_upd_req(void) static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
{ {
u32 dram_class; u32 dram_class;
struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
dram_class = k3_lpddr4_read_ddr_type(); dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dram_class) { switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4: case DENALI_CTL_0_DRAM_CLASS_DDR4:
break; break;
case DENALI_CTL_0_DRAM_CLASS_LPDDR4: case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
k3_lpddr4_freq_update(); k3_lpddr4_freq_update(ddrss);
break; break;
default: default:
printf("Unrecognized dram_class cannot update frequency!\n"); printf("Unrecognized dram_class cannot update frequency!\n");
@ -167,8 +170,9 @@ static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
{ {
u32 dram_class; u32 dram_class;
int ret; int ret;
lpddr4_privatedata *pd = &ddrss->pd;
dram_class = k3_lpddr4_read_ddr_type(); dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dram_class) { switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4: case DENALI_CTL_0_DRAM_CLASS_DDR4:
@ -196,7 +200,7 @@ static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
lpddr4_infotype infotype) lpddr4_infotype infotype)
{ {
if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
k3_lpddr4_ack_freq_upd_req(); k3_lpddr4_ack_freq_upd_req(pd);
} }
static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss) static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
@ -235,6 +239,7 @@ static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
static int k3_ddrss_ofdata_to_priv(struct udevice *dev) static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
{ {
struct k3_ddrss_desc *ddrss = dev_get_priv(dev); struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
struct k3_ddrss_data *ddrss_data = (struct k3_ddrss_data *)dev_get_driver_data(dev);
phys_addr_t reg; phys_addr_t reg;
int ret; int ret;
@ -274,6 +279,17 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
if (ret) if (ret)
dev_err(dev, "clk get failed for osc clk %d\n", ret); dev_err(dev, "clk get failed for osc clk %d\n", ret);
/* Reading instance number for multi ddr subystems */
if (ddrss_data->flags & MULTI_DDR_SUBSYSTEM) {
ret = dev_read_u32(dev, "instance", &ddrss->instance);
if (ret) {
dev_err(dev, "missing instance property");
return -EINVAL;
}
} else {
ddrss->instance = 0;
}
ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1); ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
if (ret) if (ret)
dev_err(dev, "ddr freq1 not populated %d\n", ret); dev_err(dev, "ddr freq1 not populated %d\n", ret);
@ -289,12 +305,13 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
return ret; return ret;
} }
void k3_lpddr4_probe(void) void k3_lpddr4_probe(struct k3_ddrss_desc *ddrss)
{ {
u32 status = 0U; u32 status = 0U;
u16 configsize = 0U; u16 configsize = 0U;
lpddr4_config *config = &ddrss->config;
status = driverdt->probe(&config, &configsize); status = ddrss->driverdt->probe(config, &configsize);
if ((status != 0) || (configsize != sizeof(lpddr4_privatedata)) if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
|| (configsize > SRAM_MAX)) { || (configsize > SRAM_MAX)) {
@ -305,25 +322,30 @@ void k3_lpddr4_probe(void)
} }
} }
void k3_lpddr4_init(void) void k3_lpddr4_init(struct k3_ddrss_desc *ddrss)
{ {
u32 status = 0U; u32 status = 0U;
lpddr4_config *config = &ddrss->config;
lpddr4_obj *driverdt = ddrss->driverdt;
lpddr4_privatedata *pd = &ddrss->pd;
if ((sizeof(pd) != sizeof(lpddr4_privatedata)) if ((sizeof(*pd) != sizeof(lpddr4_privatedata)) || (sizeof(*pd) > SRAM_MAX)) {
|| (sizeof(pd) > SRAM_MAX)) {
printf("%s: FAIL\n", __func__); printf("%s: FAIL\n", __func__);
hang(); hang();
} }
config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg; config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
config.infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler; config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
status = driverdt->init(&pd, &config); status = driverdt->init(pd, config);
/* linking ddr instance to lpddr4 */
pd->ddr_instance = (void *)ddrss;
if ((status > 0U) || if ((status > 0U) ||
(pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) || (pd->ctlbase != (struct lpddr4_ctlregs_s *)config->ctlbase) ||
(pd.ctlinterrupthandler != config.ctlinterrupthandler) || (pd->ctlinterrupthandler != config->ctlinterrupthandler) ||
(pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) { (pd->phyindepinterrupthandler != config->phyindepinterrupthandler)) {
printf("%s: FAIL\n", __func__); printf("%s: FAIL\n", __func__);
hang(); hang();
} else { } else {
@ -331,7 +353,8 @@ void k3_lpddr4_init(void)
} }
} }
void populate_data_array_from_dt(struct reginitdata *reginit_data) void populate_data_array_from_dt(struct k3_ddrss_desc *ddrss,
struct reginitdata *reginit_data)
{ {
int ret, i; int ret, i;
@ -363,22 +386,24 @@ void populate_data_array_from_dt(struct reginitdata *reginit_data)
reginit_data->phy_regs_offs[i] = i; reginit_data->phy_regs_offs[i] = i;
} }
void k3_lpddr4_hardware_reg_init(void) void k3_lpddr4_hardware_reg_init(struct k3_ddrss_desc *ddrss)
{ {
u32 status = 0U; u32 status = 0U;
struct reginitdata reginitdata; struct reginitdata reginitdata;
lpddr4_obj *driverdt = ddrss->driverdt;
lpddr4_privatedata *pd = &ddrss->pd;
populate_data_array_from_dt(&reginitdata); populate_data_array_from_dt(ddrss, &reginitdata);
status = driverdt->writectlconfig(&pd, reginitdata.ctl_regs, status = driverdt->writectlconfig(pd, reginitdata.ctl_regs,
reginitdata.ctl_regs_offs, reginitdata.ctl_regs_offs,
LPDDR4_INTR_CTL_REG_COUNT); LPDDR4_INTR_CTL_REG_COUNT);
if (!status) if (!status)
status = driverdt->writephyindepconfig(&pd, reginitdata.pi_regs, status = driverdt->writephyindepconfig(pd, reginitdata.pi_regs,
reginitdata.pi_regs_offs, reginitdata.pi_regs_offs,
LPDDR4_INTR_PHY_INDEP_REG_COUNT); LPDDR4_INTR_PHY_INDEP_REG_COUNT);
if (!status) if (!status)
status = driverdt->writephyconfig(&pd, reginitdata.phy_regs, status = driverdt->writephyconfig(pd, reginitdata.phy_regs,
reginitdata.phy_regs_offs, reginitdata.phy_regs_offs,
LPDDR4_INTR_PHY_REG_COUNT); LPDDR4_INTR_PHY_REG_COUNT);
if (status) { if (status) {
@ -387,27 +412,29 @@ void k3_lpddr4_hardware_reg_init(void)
} }
} }
void k3_lpddr4_start(void) void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
{ {
u32 status = 0U; u32 status = 0U;
u32 regval = 0U; u32 regval = 0U;
u32 offset = 0U; u32 offset = 0U;
lpddr4_obj *driverdt = ddrss->driverdt;
lpddr4_privatedata *pd = &ddrss->pd;
TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset); TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval); status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) { if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
printf("%s: Pre start FAIL\n", __func__); printf("%s: Pre start FAIL\n", __func__);
hang(); hang();
} }
status = driverdt->start(&pd); status = driverdt->start(pd);
if (status > 0U) { if (status > 0U) {
printf("%s: FAIL\n", __func__); printf("%s: FAIL\n", __func__);
hang(); hang();
} }
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval); status = driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) { if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
printf("%s: Post start FAIL\n", __func__); printf("%s: Post start FAIL\n", __func__);
hang(); hang();
@ -419,8 +446,7 @@ void k3_lpddr4_start(void)
static int k3_ddrss_probe(struct udevice *dev) static int k3_ddrss_probe(struct udevice *dev)
{ {
int ret; int ret;
struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
ddrss = dev_get_priv(dev);
debug("%s(dev=%p)\n", __func__, dev); debug("%s(dev=%p)\n", __func__, dev);
@ -439,16 +465,17 @@ static int k3_ddrss_probe(struct udevice *dev)
writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
#endif #endif
driverdt = lpddr4_getinstance(); ddrss->driverdt = lpddr4_getinstance();
k3_lpddr4_probe();
k3_lpddr4_init(); k3_lpddr4_probe(ddrss);
k3_lpddr4_hardware_reg_init(); k3_lpddr4_init(ddrss);
k3_lpddr4_hardware_reg_init(ddrss);
ret = k3_ddrss_init_freq(ddrss); ret = k3_ddrss_init_freq(ddrss);
if (ret) if (ret)
return ret; return ret;
k3_lpddr4_start(); k3_lpddr4_start(ddrss);
return ret; return ret;
} }
@ -462,9 +489,18 @@ static struct ram_ops k3_ddrss_ops = {
.get_info = k3_ddrss_get_info, .get_info = k3_ddrss_get_info,
}; };
static const struct k3_ddrss_data k3_data = {
.flags = SINGLE_DDR_SUBSYSTEM,
};
static const struct k3_ddrss_data j721s2_data = {
.flags = MULTI_DDR_SUBSYSTEM,
};
static const struct udevice_id k3_ddrss_ids[] = { static const struct udevice_id k3_ddrss_ids[] = {
{.compatible = "ti,am64-ddrss"}, {.compatible = "ti,am64-ddrss", .data = (ulong)&k3_data, },
{.compatible = "ti,j721e-ddrss"}, {.compatible = "ti,j721e-ddrss", .data = (ulong)&k3_data, },
{.compatible = "ti,j721s2-ddrss", .data = (ulong)&j721s2_data, },
{} {}
}; };