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86xx: Rearrange the sequence in start.S
* split the BAT initialization so that only 2 BATs (for the boot page and stack) are programmed very early on. The rest are initialized later. * Move other BAT setup, ccsrbar setup, and law setup later in the code after translation has been enabled. These changes will facilitate the moving of law and BAT initialization to C code, and will aid with 36-bit physical addressing support. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
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33dac03b1b
commit
1a41f7ce9c
1 changed files with 71 additions and 55 deletions
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@ -235,17 +235,8 @@ in_flash:
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bl enable_ext_addr
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/* setup the bats */
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bl setup_bats
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sync
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bl early_bats
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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/* setup ccsrbar */
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bl setup_ccsrbar
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#endif
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/* setup the law entries */
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bl law_entry
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sync
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/*
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* Cache must be enabled here for stack-in-cache trick.
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* This means we need to enable the BATS.
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@ -282,6 +273,19 @@ in_flash:
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GET_GOT /* initialize GOT access */
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/* setup the rest of the bats */
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bl setup_bats
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bl clear_tlbs
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sync
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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/* setup ccsrbar */
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bl setup_ccsrbar
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#endif
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bl law_entry
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sync
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/* run low-level CPU init code (from Flash) */
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bl cpu_init_f
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sync
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@ -359,6 +363,7 @@ invalidate_bats:
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/* setup_bats - set them up to some initial state */
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/* Skip any BATS setup in early_bats */
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.globl setup_bats
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setup_bats:
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@ -454,42 +459,6 @@ setup_bats:
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mtspr DBAT4U, r3
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isync
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/* IBAT 5 */
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addis r4, r0, CFG_IBAT5L@h
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ori r4, r4, CFG_IBAT5L@l
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addis r3, r0, CFG_IBAT5U@h
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ori r3, r3, CFG_IBAT5U@l
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mtspr IBAT5L, r4
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mtspr IBAT5U, r3
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isync
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/* DBAT 5 */
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addis r4, r0, CFG_DBAT5L@h
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ori r4, r4, CFG_DBAT5L@l
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addis r3, r0, CFG_DBAT5U@h
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ori r3, r3, CFG_DBAT5U@l
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mtspr DBAT5L, r4
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mtspr DBAT5U, r3
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isync
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/* IBAT 6 */
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addis r4, r0, CFG_IBAT6L@h
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ori r4, r4, CFG_IBAT6L@l
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addis r3, r0, CFG_IBAT6U@h
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ori r3, r3, CFG_IBAT6U@l
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mtspr IBAT6L, r4
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mtspr IBAT6U, r3
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isync
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/* DBAT 6 */
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addis r4, r0, CFG_DBAT6L@h
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ori r4, r4, CFG_DBAT6L@l
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addis r3, r0, CFG_DBAT6U@h
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ori r3, r3, CFG_DBAT6U@l
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mtspr DBAT6L, r4
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mtspr DBAT6U, r3
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isync
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/* IBAT 7 */
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addis r4, r0, CFG_IBAT7L@h
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ori r4, r4, CFG_IBAT7L@l
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@ -508,18 +477,65 @@ setup_bats:
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mtspr DBAT7U, r3
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isync
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1:
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addis r3, 0, 0x0000
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addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
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sync
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blr
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/*
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* early_bats:
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*
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* Set up bats needed early on - this is usually the BAT for the
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* stack-in-cache and the Flash
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*/
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.globl early_bats
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early_bats:
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/* IBAT 5 */
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lis r4, CFG_IBAT5L@h
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ori r4, r4, CFG_IBAT5L@l
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lis r3, CFG_IBAT5U@h
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ori r3, r3, CFG_IBAT5U@l
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mtspr IBAT5L, r4
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mtspr IBAT5U, r3
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isync
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tlblp:
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tlbie r3
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sync
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addi r3, r3, 0x1000
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cmp 0, 0, r3, r5
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blt tlblp
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/* DBAT 5 */
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lis r4, CFG_DBAT5L@h
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ori r4, r4, CFG_DBAT5L@l
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lis r3, CFG_DBAT5U@h
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ori r3, r3, CFG_DBAT5U@l
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mtspr DBAT5L, r4
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mtspr DBAT5U, r3
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isync
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/* IBAT 6 */
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lis r4, CFG_IBAT6L@h
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ori r4, r4, CFG_IBAT6L@l
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lis r3, CFG_IBAT6U@h
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ori r3, r3, CFG_IBAT6U@l
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mtspr IBAT6L, r4
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mtspr IBAT6U, r3
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isync
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/* DBAT 6 */
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lis r4, CFG_DBAT6L@h
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ori r4, r4, CFG_DBAT6L@l
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lis r3, CFG_DBAT6U@h
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ori r3, r3, CFG_DBAT6U@l
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mtspr DBAT6L, r4
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mtspr DBAT6U, r3
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isync
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blr
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.globl clear_tlbs
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clear_tlbs:
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addis r3, 0, 0x0000
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addis r5, 0, 0x4
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isync
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tlblp:
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tlbie r3
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sync
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addi r3, r3, 0x1000
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cmp 0, 0, r3, r5
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blt tlblp
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blr
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.globl enable_addr_trans
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