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[MIPS] <asm/mipsregs.h>: Update register / bit field definitions
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi
Shinya Kuribayashi
parent
bf462ae450
commit
1a3adac81c
1 changed files with 221 additions and 107 deletions
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@ -7,8 +7,8 @@
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* Copyright (C) 2000 Silicon Graphics, Inc.
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* Modified for further R[236]000 support by Paul M. Antoine, 1996.
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2003 Maciej W. Rozycki
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* Copyright (C) 2000, 07 MIPS Technologies, Inc.
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* Copyright (C) 2003, 2004 Maciej W. Rozycki
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*/
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#ifndef _ASM_MIPSREGS_H
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#define _ASM_MIPSREGS_H
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@ -28,6 +28,15 @@
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#define STR(x) __STR(x)
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#endif
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/*
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* Configure language
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*/
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#ifdef __ASSEMBLY__
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#define _ULCAST_
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#else
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#define _ULCAST_ (unsigned long)
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#endif
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/*
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* Coprocessor 0 register names
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*/
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@ -55,12 +64,15 @@
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#define CP0_XCONTEXT $20
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#define CP0_FRAMEMASK $21
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#define CP0_DIAGNOSTIC $22
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#define CP0_DEBUG $23
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#define CP0_DEPC $24
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#define CP0_PERFORMANCE $25
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#define CP0_ECC $26
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#define CP0_CACHEERR $27
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#define CP0_TAGLO $28
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#define CP0_TAGHI $29
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#define CP0_ERROREPC $30
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#define CP0_DESAVE $31
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/*
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* R4640/R4650 cp0 register names. These registers are listed
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@ -82,6 +94,22 @@
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#define CP0_S1_DERRADDR0 $26
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#define CP0_S1_DERRADDR1 $27
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#define CP0_S1_INTCONTROL $20
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/*
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* Coprocessor 0 Set 2 register names
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*/
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#define CP0_S2_SRSCTL $12 /* MIPSR2 */
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/*
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* Coprocessor 0 Set 3 register names
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*/
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#define CP0_S3_SRSMAP $12 /* MIPSR2 */
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/*
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* TX39 Series
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*/
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#define CP0_TX39_CACHE $7
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/*
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* Coprocessor 1 (FPU) register names
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*/
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@ -142,9 +170,10 @@
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/*
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* Values for PageMask register
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*/
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#include <linux/config.h>
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#ifdef CONFIG_CPU_VR41XX
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/* Why doesn't stupidity hurt ... */
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#define PM_1K 0x00000000
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#define PM_4K 0x00001800
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#define PM_16K 0x00007800
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@ -160,6 +189,8 @@
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#define PM_1M 0x001fe000
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#define PM_4M 0x007fe000
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#define PM_16M 0x01ffe000
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#define PM_64M 0x07ffe000
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#define PM_256M 0x1fffe000
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#endif
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@ -173,6 +204,8 @@
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#define PL_1M 20
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#define PL_4M 22
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#define PL_16M 24
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#define PL_64M 26
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#define PL_256M 28
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/*
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* Macros to access the system control coprocessor
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@ -252,26 +285,26 @@
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/*
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* R4x00 interrupt enable / cause bits
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*/
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#define IE_SW0 (1<< 8)
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#define IE_SW1 (1<< 9)
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#define IE_IRQ0 (1<<10)
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#define IE_IRQ1 (1<<11)
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#define IE_IRQ2 (1<<12)
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#define IE_IRQ3 (1<<13)
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#define IE_IRQ4 (1<<14)
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#define IE_IRQ5 (1<<15)
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#define IE_SW0 (_ULCAST_(1) << 8)
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#define IE_SW1 (_ULCAST_(1) << 9)
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#define IE_IRQ0 (_ULCAST_(1) << 10)
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#define IE_IRQ1 (_ULCAST_(1) << 11)
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#define IE_IRQ2 (_ULCAST_(1) << 12)
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#define IE_IRQ3 (_ULCAST_(1) << 13)
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#define IE_IRQ4 (_ULCAST_(1) << 14)
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#define IE_IRQ5 (_ULCAST_(1) << 15)
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/*
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* R4x00 interrupt cause bits
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*/
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#define C_SW0 (1<< 8)
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#define C_SW1 (1<< 9)
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#define C_IRQ0 (1<<10)
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#define C_IRQ1 (1<<11)
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#define C_IRQ2 (1<<12)
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#define C_IRQ3 (1<<13)
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#define C_IRQ4 (1<<14)
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#define C_IRQ5 (1<<15)
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#define C_SW0 (_ULCAST_(1) << 8)
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#define C_SW1 (_ULCAST_(1) << 9)
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#define C_IRQ0 (_ULCAST_(1) << 10)
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#define C_IRQ1 (_ULCAST_(1) << 11)
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#define C_IRQ2 (_ULCAST_(1) << 12)
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#define C_IRQ3 (_ULCAST_(1) << 13)
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#define C_IRQ4 (_ULCAST_(1) << 14)
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#define C_IRQ5 (_ULCAST_(1) << 15)
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#ifndef _LANGUAGE_ASSEMBLY
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/*
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@ -339,6 +372,13 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
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#define ST0_DE 0x00010000
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#define ST0_CE 0x00020000
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/*
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* Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
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* cacheops in userspace. This bit exists only on RM7000 and RM9000
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* processors.
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*/
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#define ST0_CO 0x08000000
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/*
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* Bitfields in the R[23]000 cp0 status register.
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*/
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@ -356,9 +396,14 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
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/*
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* Bits specific to the R4640/R4650
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*/
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#define ST0_UM (1 << 4)
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#define ST0_IL (1 << 23)
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#define ST0_DL (1 << 24)
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#define ST0_UM (_ULCAST_(1) << 4)
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#define ST0_IL (_ULCAST_(1) << 23)
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#define ST0_DL (_ULCAST_(1) << 24)
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/*
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* Enable the MIPS MDMX and DSP ASEs
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*/
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#define ST0_MX 0x01000000
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/*
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* Bitfields in the TX39 family CP0 Configuration Register 3
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@ -398,39 +443,40 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
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*/
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#define ST0_IM 0x0000ff00
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#define STATUSB_IP0 8
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#define STATUSF_IP0 (1 << 8)
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#define STATUSF_IP0 (_ULCAST_(1) << 8)
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#define STATUSB_IP1 9
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#define STATUSF_IP1 (1 << 9)
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#define STATUSF_IP1 (_ULCAST_(1) << 9)
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#define STATUSB_IP2 10
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#define STATUSF_IP2 (1 << 10)
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#define STATUSF_IP2 (_ULCAST_(1) << 10)
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#define STATUSB_IP3 11
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#define STATUSF_IP3 (1 << 11)
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#define STATUSF_IP3 (_ULCAST_(1) << 11)
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#define STATUSB_IP4 12
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#define STATUSF_IP4 (1 << 12)
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#define STATUSF_IP4 (_ULCAST_(1) << 12)
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#define STATUSB_IP5 13
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#define STATUSF_IP5 (1 << 13)
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#define STATUSF_IP5 (_ULCAST_(1) << 13)
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#define STATUSB_IP6 14
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#define STATUSF_IP6 (1 << 14)
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#define STATUSF_IP6 (_ULCAST_(1) << 14)
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#define STATUSB_IP7 15
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#define STATUSF_IP7 (1 << 15)
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#define STATUSF_IP7 (_ULCAST_(1) << 15)
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#define STATUSB_IP8 0
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#define STATUSF_IP8 (1 << 0)
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#define STATUSF_IP8 (_ULCAST_(1) << 0)
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#define STATUSB_IP9 1
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#define STATUSF_IP9 (1 << 1)
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#define STATUSF_IP9 (_ULCAST_(1) << 1)
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#define STATUSB_IP10 2
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#define STATUSF_IP10 (1 << 2)
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#define STATUSF_IP10 (_ULCAST_(1) << 2)
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#define STATUSB_IP11 3
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#define STATUSF_IP11 (1 << 3)
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#define STATUSF_IP11 (_ULCAST_(1) << 3)
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#define STATUSB_IP12 4
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#define STATUSF_IP12 (1 << 4)
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#define STATUSF_IP12 (_ULCAST_(1) << 4)
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#define STATUSB_IP13 5
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#define STATUSF_IP13 (1 << 5)
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#define STATUSF_IP13 (_ULCAST_(1) << 5)
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#define STATUSB_IP14 6
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#define STATUSF_IP14 (1 << 6)
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#define STATUSF_IP14 (_ULCAST_(1) << 6)
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#define STATUSB_IP15 7
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#define STATUSF_IP15 (1 << 7)
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#define STATUSF_IP15 (_ULCAST_(1) << 7)
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#define ST0_CH 0x00040000
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#define ST0_SR 0x00100000
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#define ST0_TS 0x00200000
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#define ST0_BEV 0x00400000
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#define ST0_RE 0x02000000
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#define ST0_FR 0x04000000
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@ -447,35 +493,36 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
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* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
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*/
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#define CAUSEB_EXCCODE 2
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#define CAUSEF_EXCCODE (31 << 2)
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#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
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#define CAUSEB_IP 8
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#define CAUSEF_IP (255 << 8)
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#define CAUSEF_IP (_ULCAST_(255) << 8)
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#define CAUSEB_IP0 8
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#define CAUSEF_IP0 (1 << 8)
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#define CAUSEF_IP0 (_ULCAST_(1) << 8)
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#define CAUSEB_IP1 9
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#define CAUSEF_IP1 (1 << 9)
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#define CAUSEF_IP1 (_ULCAST_(1) << 9)
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#define CAUSEB_IP2 10
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#define CAUSEF_IP2 (1 << 10)
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#define CAUSEF_IP2 (_ULCAST_(1) << 10)
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#define CAUSEB_IP3 11
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#define CAUSEF_IP3 (1 << 11)
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#define CAUSEF_IP3 (_ULCAST_(1) << 11)
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#define CAUSEB_IP4 12
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#define CAUSEF_IP4 (1 << 12)
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#define CAUSEF_IP4 (_ULCAST_(1) << 12)
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#define CAUSEB_IP5 13
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#define CAUSEF_IP5 (1 << 13)
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#define CAUSEF_IP5 (_ULCAST_(1) << 13)
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#define CAUSEB_IP6 14
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#define CAUSEF_IP6 (1 << 14)
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#define CAUSEF_IP6 (_ULCAST_(1) << 14)
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#define CAUSEB_IP7 15
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#define CAUSEF_IP7 (1 << 15)
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#define CAUSEF_IP7 (_ULCAST_(1) << 15)
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#define CAUSEB_IV 23
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#define CAUSEF_IV (1 << 23)
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#define CAUSEF_IV (_ULCAST_(1) << 23)
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#define CAUSEB_CE 28
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#define CAUSEF_CE (3 << 28)
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#define CAUSEF_CE (_ULCAST_(3) << 28)
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#define CAUSEB_BD 31
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#define CAUSEF_BD (1 << 31)
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#define CAUSEF_BD (_ULCAST_(1) << 31)
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/*
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* Bits in the coprozessor 0 config register.
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* Bits in the coprocessor 0 config register.
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*/
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/* Generic bits. */
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#define CONF_CM_CACHABLE_NO_WA 0
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#define CONF_CM_CACHABLE_WA 1
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#define CONF_CM_UNCACHED 2
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@ -485,66 +532,133 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
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#define CONF_CM_CACHABLE_CUW 6
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#define CONF_CM_CACHABLE_ACCELERATED 7
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#define CONF_CM_CMASK 7
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#define CONF_DB (1 << 4)
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#define CONF_IB (1 << 5)
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#define CONF_SC (1 << 17)
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#define CONF_AC (1 << 23)
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#define CONF_HALT (1 << 25)
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#define CONF_BE (_ULCAST_(1) << 15)
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/* Bits common to various processors. */
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#define CONF_CU (_ULCAST_(1) << 3)
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#define CONF_DB (_ULCAST_(1) << 4)
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#define CONF_IB (_ULCAST_(1) << 5)
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#define CONF_DC (_ULCAST_(7) << 6)
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#define CONF_IC (_ULCAST_(7) << 9)
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#define CONF_EB (_ULCAST_(1) << 13)
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#define CONF_EM (_ULCAST_(1) << 14)
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#define CONF_SM (_ULCAST_(1) << 16)
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#define CONF_SC (_ULCAST_(1) << 17)
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#define CONF_EW (_ULCAST_(3) << 18)
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#define CONF_EP (_ULCAST_(15)<< 24)
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#define CONF_EC (_ULCAST_(7) << 28)
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#define CONF_CM (_ULCAST_(1) << 31)
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/* Bits specific to the R4xx0. */
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#define R4K_CONF_SW (_ULCAST_(1) << 20)
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#define R4K_CONF_SS (_ULCAST_(1) << 21)
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#define R4K_CONF_SB (_ULCAST_(3) << 22)
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/* Bits specific to the R5000. */
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#define R5K_CONF_SE (_ULCAST_(1) << 12)
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#define R5K_CONF_SS (_ULCAST_(3) << 20)
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/* Bits specific to the RM7000. */
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#define RM7K_CONF_SE (_ULCAST_(1) << 3)
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#define RM7K_CONF_TE (_ULCAST_(1) << 12)
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#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
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#define RM7K_CONF_TC (_ULCAST_(1) << 17)
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#define RM7K_CONF_SI (_ULCAST_(3) << 20)
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#define RM7K_CONF_SC (_ULCAST_(1) << 31)
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/* Bits specific to the R10000. */
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#define R10K_CONF_DN (_ULCAST_(3) << 3)
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#define R10K_CONF_CT (_ULCAST_(1) << 5)
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#define R10K_CONF_PE (_ULCAST_(1) << 6)
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#define R10K_CONF_PM (_ULCAST_(3) << 7)
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#define R10K_CONF_EC (_ULCAST_(15)<< 9)
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#define R10K_CONF_SB (_ULCAST_(1) << 13)
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#define R10K_CONF_SK (_ULCAST_(1) << 14)
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#define R10K_CONF_SS (_ULCAST_(7) << 16)
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#define R10K_CONF_SC (_ULCAST_(7) << 19)
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#define R10K_CONF_DC (_ULCAST_(7) << 26)
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#define R10K_CONF_IC (_ULCAST_(7) << 29)
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/* Bits specific to the VR41xx. */
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#define VR41_CONF_CS (_ULCAST_(1) << 12)
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#define VR41_CONF_P4K (_ULCAST_(1) << 13)
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#define VR41_CONF_BP (_ULCAST_(1) << 16)
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#define VR41_CONF_M16 (_ULCAST_(1) << 20)
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#define VR41_CONF_AD (_ULCAST_(1) << 23)
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/* Bits specific to the R30xx. */
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#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
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#define R30XX_CONF_REV (_ULCAST_(1) << 22)
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#define R30XX_CONF_AC (_ULCAST_(1) << 23)
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#define R30XX_CONF_RF (_ULCAST_(1) << 24)
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#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
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#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
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#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
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#define R30XX_CONF_SB (_ULCAST_(1) << 30)
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#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
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/* Bits specific to the TX49. */
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#define TX49_CONF_DC (_ULCAST_(1) << 16)
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#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
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#define TX49_CONF_HALT (_ULCAST_(1) << 18)
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#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
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/* Bits specific to the MIPS32/64 PRA. */
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#define MIPS_CONF_MT (_ULCAST_(7) << 7)
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#define MIPS_CONF_AR (_ULCAST_(7) << 10)
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#define MIPS_CONF_AT (_ULCAST_(3) << 13)
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#define MIPS_CONF_M (_ULCAST_(1) << 31)
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/*
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* R10000 performance counter definitions.
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*
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* FIXME: The R10000 performance counter opens a nice way to implement CPU
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* time accounting with a precission of one cycle. I don't have
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* R10000 silicon but just a manual, so ...
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* Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
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*/
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#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
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#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
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#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
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#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
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#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
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#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
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#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
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#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
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#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
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#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
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#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
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#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
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#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
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#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
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#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
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#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
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#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
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#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
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#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
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#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
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#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
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#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
|
||||
|
||||
#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
|
||||
#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
|
||||
#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
|
||||
#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
|
||||
#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
|
||||
#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
|
||||
#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
|
||||
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
|
||||
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
|
||||
|
||||
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
|
||||
|
||||
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
|
||||
|
||||
/*
|
||||
* Events counted by counter #0
|
||||
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
|
||||
*/
|
||||
#define CE0_CYCLES 0
|
||||
#define CE0_INSN_ISSUED 1
|
||||
#define CE0_LPSC_ISSUED 2
|
||||
#define CE0_S_ISSUED 3
|
||||
#define CE0_SC_ISSUED 4
|
||||
#define CE0_SC_FAILED 5
|
||||
#define CE0_BRANCH_DECODED 6
|
||||
#define CE0_QW_WB_SECONDARY 7
|
||||
#define CE0_CORRECTED_ECC_ERRORS 8
|
||||
#define CE0_ICACHE_MISSES 9
|
||||
#define CE0_SCACHE_I_MISSES 10
|
||||
#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
|
||||
#define CE0_EXT_INTERVENTIONS_REQ 12
|
||||
#define CE0_EXT_INVALIDATE_REQ 13
|
||||
#define CE0_VIRTUAL_COHERENCY_COND 14
|
||||
#define CE0_INSN_GRADUATED 15
|
||||
|
||||
/*
|
||||
* Events counted by counter #1
|
||||
*/
|
||||
#define CE1_CYCLES 0
|
||||
#define CE1_INSN_GRADUATED 1
|
||||
#define CE1_LPSC_GRADUATED 2
|
||||
#define CE1_S_GRADUATED 3
|
||||
#define CE1_SC_GRADUATED 4
|
||||
#define CE1_FP_INSN_GRADUATED 5
|
||||
#define CE1_QW_WB_PRIMARY 6
|
||||
#define CE1_TLB_REFILL 7
|
||||
#define CE1_BRANCH_MISSPREDICTED 8
|
||||
#define CE1_DCACHE_MISS 9
|
||||
#define CE1_SCACHE_D_MISSES 10
|
||||
#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
|
||||
#define CE1_EXT_INTERVENTION_HITS 12
|
||||
#define CE1_EXT_INVALIDATE_REQ 13
|
||||
#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
|
||||
#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
|
||||
|
||||
/*
|
||||
* These flags define in which priviledge mode the counters count events
|
||||
*/
|
||||
#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
|
||||
#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
|
||||
#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
|
||||
#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
|
||||
#define MIPS_FPIR_S (_ULCAST_(1) << 16)
|
||||
#define MIPS_FPIR_D (_ULCAST_(1) << 17)
|
||||
#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
|
||||
#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
|
||||
#define MIPS_FPIR_W (_ULCAST_(1) << 20)
|
||||
#define MIPS_FPIR_L (_ULCAST_(1) << 21)
|
||||
#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
|
||||
|
||||
#endif /* _ASM_MIPSREGS_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue