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Merge branch 'master' of /home/wd/git/u-boot/custodians

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* 'master' of /home/wd/git/u-boot/custodians:
  SMDKV310: Fix incorrect conditional compilation for MIU linear mapping
  SMDKV310: CPU fequency and mmc_pre_ratio modified
  armv7: Add support for ST-Ericsson U8500 href platform
  I2C: Add driver for ST-Ericsson U8500 i2c
  armv7: Add ST-Ericsson u8500 arch
  Kirkwood: boards cleanup for deprecated CONFIG_CMD_AUTOSCRIPT
  ARMV7: Vexpress: Add missing MMC header
  arm/km: update mgcoge3un board support
  mvgbe: enable configurability of PORT_SERIAL_CONTROL_VALUE
  arm/km: rename mgcoge2un to mgcoge3un
  arm/km: add second serial interface for kirkwood
  arm/km: disable ls (through jffs2 support)
  arm/km: introduce bootcount env variable and clean km_arm
  arm/km: move CONFIG_EXTRA_ENV_SETTINGS from board to km_arm file
  arm/km: remove CONFIG_SYS_KWD_CONFIG from keymile-common.h
  ARMV7: MMC SPL Boot support for SMDKV310 board
  ARMV7: Add support for Samsung SMDKV310 Board
  S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1)
  S5P: add set_mmc_clk for external clock control
  S5PC2XX: Support the cpu revision
  S5P:SROM config code moved to s5p-common directory
  Add _end for the end of u-boot image for SMDK6400
  MMC S5P: Fix typo
  S5P: GPIO Macro Values Corrected.
  SMDK2410: various cleanup/code style fixes
  SMDK2410: use the CFI driver (and remove the old one)
  SMDK2410: remove unneeded config.mk
  SMDK2410: activate ARM relocation feature
  BeagleBoard: fixed typo in typecast
  mvsata: issue hard reset on initialization
  VCMA9: use ARM relocation feature to fix build error
  MX31: drop warnings due to missing prototype for mxc_watchdog_reset()
  MX5: drop config.mk from efikamx board
  MX31: Make get_reset_cause() static and drop unreachable code
  MX53: Remove CONFIG_SYS_BOOTMAPSZ from mx53 config files.
  MX53: Handle silicon revision 2.1 case
  mx5: board: code clean up for checkboard code
  MX51: vision2: Fix build for vision2 board.
  MX51: vision: Let video mode struct be independant of watchdog.
  MX53: Add initial support for MX53SMD board.
  MX53: support for freescale MX53LOCO board
  mx5: Fix CONFIG_OF_LIBFDT redefined warning
  mx5: Remove unnecessary CONFIG_SYS_BOOTMAPSZ definition
  mx31pdk: Clean up mx31pdk.h file
This commit is contained in:
Wolfgang Denk 2011-06-01 22:04:29 +02:00
commit 1a0787d3c4
88 changed files with 6446 additions and 871 deletions
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12
MAINTAINERS
View file

@ -430,13 +430,10 @@ Heiko Schocher <hs@denx.de>
kmsupx5 MPC8321
mgcoge MPC8247
mgcoge3ne MPC8247
mgcoge2un ARM926EJS (Kirkwood SoC)
mucmc52 MPC5200
muas3001 MPC8270
municse MPC5200
sc3 PPC405GP
suen3 ARM926EJS (Kirkwood SoC)
suen8 ARM926EJS (Kirkwood SoC)
suvd3 MPC8321
tuda1 MPC8321
tuxa1 MPC8321
@ -574,6 +571,7 @@ Stefano Babic <sbabic@denx.de>
Jason Liu <r64343@freescale.com>
mx53evk i.MX53
mx53loco i.MX53
Enric Balletbo i Serra <eballetbo@iseebcn.com>
@ -638,6 +636,7 @@ Kristoffer Ericson <kristoffer.ericson@gmail.com>
Fabio Estevam <fabio.estevam@freescale.com>
mx31pdk i.MX31
mx53smd i.MX53
Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
@ -698,6 +697,10 @@ Minkyu Kang <mk7.kang@samsung.com>
s5p_goni ARM ARMV7 (S5PC110 SoC)
s5pc210_universal ARM ARMV7 (S5PC210 SoC)
Chander Kashyap <k.chander@samsung.com>
SMDKV310 ARM ARMV7 (S5PC210 SoC)
Frederik Kriewitz <frederik@kriewitz.eu>
devkit8000 ARM ARMV7 (OMAP3530 SoC)
@ -810,6 +813,9 @@ Jens Scharsig <esw@bus-elektronik.de>
Heiko Schocher <hs@denx.de>
magnesium i.MX27
mgcoge3un ARM926EJS (Kirkwood SoC)
suen3 ARM926EJS (Kirkwood SoC)
suen8 ARM926EJS (Kirkwood SoC)
Robert Schwebel <r.schwebel@pengutronix.de>

11
Makefile
View file

@ -322,6 +322,10 @@ ALL += $(obj)u-boot-onenand.bin
ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
endif
ifeq ($(CONFIG_MMC_U_BOOT),y)
ALL += $(obj)mmc_spl/u-boot-mmc-spl.bin
endif
all: $(ALL)
$(obj)u-boot.hex: $(obj)u-boot
@ -413,6 +417,11 @@ onenand_ipl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(obj)u-boot-onenand.bin: onenand_ipl $(obj)u-boot.bin
cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
mmc_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C mmc_spl/board/$(BOARDDIR) all
$(obj)mmc_spl/u-boot-mmc-spl.bin: mmc_spl
$(VERSION_FILE):
@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
printf '#define PLAIN_VERSION "%s%s"\n' \
@ -1123,6 +1132,7 @@ clean:
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
@rm -f $(obj)mmc_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,u-boot-spl.bin,u-boot-mmc-spl.bin}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@ -1147,6 +1157,7 @@ clobber: clean
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)mmc_spl ] || find $(obj)mmc_spl -name "*" -type l -print | xargs rm -f
ifeq ($(OBJTREE),$(SRCTREE))
mrproper \

6
arch/arm/cpu/arm1136/mx31/generic.c
View file

@ -133,7 +133,7 @@ u32 get_cpu_rev(void)
return srev | 0x8000;
}
char *get_reset_cause(void)
static char *get_reset_cause(void)
{
/* read RCSR register from CCM module */
struct clock_control_regs *ccm =
@ -144,16 +144,12 @@ char *get_reset_cause(void)
switch (cause) {
case 0x0000:
return "POR";
break;
case 0x0001:
return "RST";
break;
case 0x0002:
return "WDOG";
break;
case 0x0006:
return "JTAG";
break;
default:
return "unknown reset";
}

10
arch/arm/cpu/armv7/mx5/soc.c
View file

@ -65,14 +65,10 @@ u32 get_cpu_rev(void)
break;
}
#else
switch (reg) {
case 0x20:
system_rev |= CHIP_REV_2_0;
break;
default:
if (reg < 0x20)
system_rev |= CHIP_REV_1_0;
break;
}
else
system_rev |= reg;
#endif
return system_rev;
}

3
arch/arm/cpu/armv7/s5p-common/Makefile
View file

@ -27,7 +27,8 @@ LIB = $(obj)libs5p-common.o
COBJS-y += cpu_info.o
COBJS-y += timer.o
COBJS-$(CONFIG_PWM) += pwm.o
COBJS-y += sromc.o
COBJS-$(CONFIG_PWM) += pwm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))

2
arch/arm/cpu/armv7/s5p-common/cpu_info.c
View file

@ -26,6 +26,8 @@
/* Default is s5pc100 */
unsigned int s5p_cpu_id = 0xC100;
/* Default is EVT1 */
unsigned int s5p_cpu_rev = 1;
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)

22
arch/arm/cpu/armv7/s5pc1xx/sromc.c → arch/arm/cpu/armv7/s5p-common/sromc.c
View file

@ -23,27 +23,27 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/smc.h>
#include <asm/arch/sromc.h>
/*
* s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
* band width control and bank control registers
* srom_bank - SROM Bank 0 to 5
* smc_bw_conf - SMC Band witdh reg configuration value
* smc_bc_conf - SMC Bank Control reg configuration value
* s5p_config_sromc() - select the proper SROMC Bank and configure the
* band width control and bank control registers
* srom_bank - SROM
* srom_bw_conf - SMC Band witdh reg configuration value
* srom_bc_conf - SMC Bank Control reg configuration value
*/
void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
{
u32 tmp;
struct s5pc1xx_smc *srom =
(struct s5pc1xx_smc *)samsung_get_base_sromc();
struct s5p_sromc *srom =
(struct s5p_sromc *)samsung_get_base_sromc();
/* Configure SMC_BW register to handle proper SROMC bank */
tmp = srom->bw;
tmp &= ~(0xF << (srom_bank * 4));
tmp |= smc_bw_conf;
tmp |= srom_bw_conf;
srom->bw = tmp;
/* Configure SMC_BC register */
srom->bc[srom_bank] = smc_bc_conf;
srom->bc[srom_bank] = srom_bc_conf;
}

1
arch/arm/cpu/armv7/s5pc1xx/Makefile
View file

@ -32,7 +32,6 @@ SOBJS = cache.o
SOBJS += reset.o
COBJS += clock.o
COBJS += sromc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

5
arch/arm/cpu/armv7/s5pc1xx/clock.c
View file

@ -336,3 +336,8 @@ unsigned long get_uart_clk(int dev_index)
{
return s5pc1xx_get_uart_clk(dev_index);
}
void set_mmc_clk(int dev_index, unsigned int div)
{
/* Do NOTHING */
}

76
arch/arm/cpu/armv7/s5pc2xx/clock.c
View file

@ -124,29 +124,35 @@ static unsigned long s5pc210_get_pwm_clk(void)
unsigned int sel;
unsigned int ratio;
/*
* CLK_SRC_PERIL0
* PWM_SEL [27:24]
*/
sel = readl(&clk->src_peril0);
sel = (sel >> 24) & 0xf;
if (s5p_get_cpu_rev() == 0) {
/*
* CLK_SRC_PERIL0
* PWM_SEL [27:24]
*/
sel = readl(&clk->src_peril0);
sel = (sel >> 24) & 0xf;
if (sel == 0x6)
if (sel == 0x6)
sclk = get_pll_clk(MPLL);
else if (sel == 0x7)
sclk = get_pll_clk(EPLL);
else if (sel == 0x8)
sclk = get_pll_clk(VPLL);
else
return 0;
/*
* CLK_DIV_PERIL3
* PWM_RATIO [3:0]
*/
ratio = readl(&clk->div_peril3);
ratio = ratio & 0xf;
} else if (s5p_get_cpu_rev() == 1) {
sclk = get_pll_clk(MPLL);
else if (sel == 0x7)
sclk = get_pll_clk(EPLL);
else if (sel == 0x8)
sclk = get_pll_clk(VPLL);
else
ratio = 8;
} else
return 0;
/*
* CLK_DIV_PERIL3
* PWM_RATIO [3:0]
*/
ratio = readl(&clk->div_peril3);
ratio = ratio & 0xf;
pclk = sclk / (ratio + 1);
return pclk;
@ -199,6 +205,33 @@ static unsigned long s5pc210_get_uart_clk(int dev_index)
return uclk;
}
/* s5pc210: set the mmc clock */
static void s5pc210_set_mmc_clk(int dev_index, unsigned int div)
{
struct s5pc210_clock *clk =
(struct s5pc210_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val;
/*
* CLK_DIV_FSYS1
* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
* CLK_DIV_FSYS2
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
*/
if (dev_index < 2) {
addr = (unsigned int)&clk->div_fsys1;
} else {
addr = (unsigned int)&clk->div_fsys2;
dev_index -= 2;
}
val = readl(addr);
val &= ~(0xff << ((dev_index << 4) + 8));
val |= (div & 0xff) << ((dev_index << 4) + 8);
writel(val, addr);
}
unsigned long get_pll_clk(int pllreg)
{
return s5pc210_get_pll_clk(pllreg);
@ -218,3 +251,8 @@ unsigned long get_uart_clk(int dev_index)
{
return s5pc210_get_uart_clk(dev_index);
}
void set_mmc_clk(int dev_index, unsigned int div)
{
s5pc210_set_mmc_clk(dev_index, div);
}

29
board/ttcontrol/vision2/config.mk → arch/arm/cpu/armv7/u8500/Makefile
View file

@ -1,5 +1,6 @@
#
# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
@ -20,6 +21,26 @@
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0x97800000
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg
ALL += $(obj)u-boot.imx
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS = timer.o clock.o
SOBJS = lowlevel.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

56
arch/arm/cpu/armv7/u8500/clock.c Normal file
View file

@ -0,0 +1,56 @@
/*
* (C) Copyright 2009 ST-Ericsson
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
struct clkrst {
unsigned int pcken;
unsigned int pckdis;
unsigned int kcken;
unsigned int kckdis;
};
static unsigned int clkrst_base[] = {
U8500_CLKRST1_BASE,
U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE,
0,
U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE,
U8500_CLKRST7_BASE, /* ED only */
};
/* Turn on peripheral clock at PRCC level */
void u8500_clock_enable(int periph, int cluster, int kern)
{
struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1];
if (kern != -1)
writel(1 << kern, &clkrst->kcken);
if (cluster != -1)
writel(1 << cluster, &clkrst->pcken);
}

35
arch/arm/cpu/armv7/u8500/lowlevel.S Normal file
View file

@ -0,0 +1,35 @@
/*
* (C) Copyright 2011 ST-Ericsson
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
.globl lowlevel_init
lowlevel_init:
mov pc, lr
.align 5
.globl reset_cpu
reset_cpu:
ldr r0, =CFG_PRCMU_BASE
ldr r1, =0x1
str r1, [r0, #0x228]
_loop_forever:
b _loop_forever

154
arch/arm/cpu/armv7/u8500/timer.c Normal file
View file

@ -0,0 +1,154 @@
/*
* Copyright (C) 2010 Linaro Limited
* John Rigby <john.rigby@linaro.org>
*
* Based on original from Linux kernel source and
* internal ST-Ericsson U-Boot source.
* (C) Copyright 2009 Alessandro Rubini
* (C) Copyright 2010 ST-Ericsson
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* The MTU device has some interrupt control registers
* followed by 4 timers.
*/
/* The timers */
struct u8500_mtu_timer {
u32 lr; /* Load value */
u32 cv; /* Current value */
u32 cr; /* Control reg */
u32 bglr; /* ??? */
};
/* The MTU that contains the timers */
struct u8500_mtu {
u32 imsc; /* Interrupt mask set/clear */
u32 ris; /* Raw interrupt status */
u32 mis; /* Masked interrupt status */
u32 icr; /* Interrupt clear register */
struct u8500_mtu_timer pt[4];
};
/* bits for the control register */
#define MTU_CR_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR */
#define MTU_CR_32BITS 0x02
#define MTU_CR_PRESCALE_1 0x00
#define MTU_CR_PRESCALE_16 0x04
#define MTU_CR_PRESCALE_256 0x08
#define MTU_CR_PRESCALE_MASK 0x0c
#define MTU_CR_PERIODIC 0x40 /* if 0 = free-running */
#define MTU_CR_ENA 0x80
/*
* The MTU is clocked at 133 MHz by default. (V1 and later)
*/
#define TIMER_CLOCK (133 * 1000 * 1000 / 16)
#define COUNT_TO_USEC(x) ((x) * 16 / 133)
#define USEC_TO_COUNT(x) ((x) * 133 / 16)
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
#define TIMER_LOAD_VAL 0xffffffff
/*
* MTU timer to use (from 0 to 3).
*/
#define MTU_TIMER 2
static struct u8500_mtu_timer *timer_base =
&((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER];
/* macro to read the 32 bit timer: since it decrements, we invert read value */
#define READ_TIMER() (~readl(&timer_base->cv))
/* Configure a free-running, auto-wrap counter with /16 prescaler */
int timer_init(void)
{
writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS,
&timer_base->cr);
return 0;
}
ulong get_timer_masked(void)
{
/* current tick value */
ulong now = TICKS_TO_HZ(READ_TIMER());
if (now >= gd->lastinc) /* normal (non rollover) */
gd->tbl += (now - gd->lastinc);
else /* rollover */
gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now;
gd->lastinc = now;
return gd->tbl;
}
/* Delay x useconds */
void __udelay(ulong usec)
{
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
ulong now, last = READ_TIMER();
while (tmo > 0) {
now = READ_TIMER();
if (now > last) /* normal (non rollover) */
tmo -= now - last;
else /* rollover */
tmo -= TIMER_LOAD_VAL - last + now;
last = now;
}
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
void set_timer(ulong t)
{
gd->tbl = t;
}
/*
* Emulation of Power architecture long long timebase.
*
* TODO: Support gd->tbu for real long long timebase.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* Emulation of Power architecture timebase.
* NB: Low resolution compared to Power tbclk.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

1
arch/arm/include/asm/arch-mx31/clock.h
View file

@ -32,5 +32,6 @@ extern void mx31_set_pad(enum iomux_pins pin, u32 config);
void mx31_uart1_hw_init(void);
void mx31_spi2_hw_init(void);
void mxc_hw_watchdog_enable(void);
void mxc_hw_watchdog_reset(void);
#endif /* __ASM_ARCH_CLOCK_H */

1
arch/arm/include/asm/arch-s5pc1xx/clk.h
View file

@ -33,5 +33,6 @@ unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
#endif

4
arch/arm/include/asm/arch-s5pc1xx/gpio.h
View file

@ -149,8 +149,8 @@ void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* Drive Strength level */
#define GPIO_DRV_1X 0x0
#define GPIO_DRV_2X 0x1
#define GPIO_DRV_3X 0x2
#define GPIO_DRV_3X 0x1
#define GPIO_DRV_2X 0x2
#define GPIO_DRV_4X 0x3
#define GPIO_DRV_FAST 0x0
#define GPIO_DRV_SLOW 0x1

1
arch/arm/include/asm/arch-s5pc1xx/mmc.h
View file

@ -64,6 +64,7 @@ struct mmc_host {
struct s5p_mmc *reg;
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
int dev_index;
};
int s5p_mmc_init(int dev_index, int bus_width);

8
arch/arm/include/asm/arch-s5pc1xx/smc.h → arch/arm/include/asm/arch-s5pc1xx/sromc.h
View file

@ -23,8 +23,8 @@
* Only SROMC is defined as of now
*/
#ifndef __ASM_ARCH_SMC_H_
#define __ASM_ARCH_SMC_H_
#ifndef __ASM_ARCH_SROMC_H_
#define __ASM_ARCH_SROMC_H_
#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
@ -41,13 +41,13 @@
#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
#ifndef __ASSEMBLY__
struct s5pc1xx_smc {
struct s5p_sromc {
unsigned int bw;
unsigned int bc[6];
};
#endif /* __ASSEMBLY__ */
/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
#endif /* __ASM_ARCH_SMC_H_ */

1
arch/arm/include/asm/arch-s5pc2xx/clk.h
View file

@ -32,5 +32,6 @@ unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
#endif

12
arch/arm/include/asm/arch-s5pc2xx/cpu.h
View file

@ -51,6 +51,12 @@
#include <asm/io.h>
/* CPU detection macros */
extern unsigned int s5p_cpu_id;
extern unsigned int s5p_cpu_rev;
static inline int s5p_get_cpu_rev(void)
{
return s5p_cpu_rev;
}
static inline void s5p_set_cpu_id(void)
{
@ -61,8 +67,12 @@ static inline void s5p_set_cpu_id(void)
* 0xC200: S5PC210 EVT0
* 0xC210: S5PC210 EVT1
*/
if (s5p_cpu_id == 0xC200)
if (s5p_cpu_id == 0xC200) {
s5p_cpu_id |= 0x10;
s5p_cpu_rev = 0;
} else if (s5p_cpu_id == 0xC210) {
s5p_cpu_rev = 1;
}
}
#define IS_SAMSUNG_TYPE(type, id) \

7
arch/arm/include/asm/arch-s5pc2xx/gpio.h
View file

@ -99,14 +99,13 @@ void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* Pull mode */
#define GPIO_PULL_NONE 0x0
#define GPIO_PULL_DOWN 0x1
#define GPIO_PULL_UP 0x2
#define GPIO_PULL_UP 0x3
/* Drive Strength level */
#define GPIO_DRV_1X 0x0
#define GPIO_DRV_2X 0x1
#define GPIO_DRV_3X 0x2
#define GPIO_DRV_3X 0x1
#define GPIO_DRV_2X 0x2
#define GPIO_DRV_4X 0x3
#define GPIO_DRV_FAST 0x0
#define GPIO_DRV_SLOW 0x1
#endif

1
arch/arm/include/asm/arch-s5pc2xx/mmc.h
View file

@ -64,6 +64,7 @@ struct mmc_host {
struct s5p_mmc *reg;
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
int dev_index;
};
int s5p_mmc_init(int dev_index, int bus_width);

51
arch/arm/include/asm/arch-s5pc2xx/sromc.h Normal file
View file

@ -0,0 +1,51 @@
/*
* (C) Copyright 2010 Samsung Electronics
* Naveen Krishna Ch <ch.naveen@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Note: This file contains the register description for SROMC
*
*/
#ifndef __ASM_ARCH_SROMC_H_
#define __ASM_ARCH_SROMC_H_
#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
/* 1-> Byte base address*/
#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
#ifndef __ASSEMBLY__
struct s5p_sromc {
unsigned int bw;
unsigned int bc[4];
};
#endif /* __ASSEMBLY__ */
/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
#endif /* __ASM_ARCH_SROMC_H_ */

72
arch/arm/include/asm/arch-u8500/clock.h Normal file
View file

@ -0,0 +1,72 @@
/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_CLOCK
#define __ASM_ARCH_CLOCK
struct prcmu {
unsigned int armclkfix_mgt;
unsigned int armclk_mgt;
unsigned int svammdspclk_mgt;
unsigned int siammdspclk_mgt;
unsigned int reserved;
unsigned int sgaclk_mgt;
unsigned int uartclk_mgt;
unsigned int msp02clk_mgt;
unsigned int i2cclk_mgt;
unsigned int sdmmcclk_mgt;
unsigned int slimclk_mgt;
unsigned int per1clk_mgt;
unsigned int per2clk_mgt;
unsigned int per3clk_mgt;
unsigned int per5clk_mgt;
unsigned int per6clk_mgt;
unsigned int per7clk_mgt;
unsigned int lcdclk_mgt;
unsigned int reserved1;
unsigned int bmlclk_mgt;
unsigned int hsitxclk_mgt;
unsigned int hsirxclk_mgt;
unsigned int hdmiclk_mgt;
unsigned int apeatclk_mgt;
unsigned int apetraceclk_mgt;
unsigned int mcdeclk_mgt;
unsigned int ipi2cclk_mgt;
unsigned int dsialtclk_mgt;
unsigned int spare2clk_mgt;
unsigned int dmaclk_mgt;
unsigned int b2r2clk_mgt;
unsigned int tvclk_mgt;
unsigned int unused[82];
unsigned int tcr;
unsigned int unused1[23];
unsigned int ape_softrst;
};
extern void u8500_clock_enable(int periph, int kern, int cluster);
static inline void u8500_prcmu_enable(unsigned int *reg)
{
writel(readl(reg) | (1 << 8), reg);
}
#endif /* __ASM_ARCH_CLOCK */

247
arch/arm/include/asm/arch-u8500/gpio.h Normal file
View file

@ -0,0 +1,247 @@
/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _UX500_GPIO_h
#define _UX500_GPIO_h
#include <asm/types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/u8500.h>
#define GPIO_TOTAL_PINS 268
#define GPIO_PINS_PER_BLOCK 32
#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
struct gpio_register {
u32 gpio_dat; /* data register *//*0x000 */
u32 gpio_dats; /* data Set register *//*0x004 */
u32 gpio_datc; /* data Clear register *//*0x008 */
u32 gpio_pdis; /* Pull disable register *//*0x00C */
u32 gpio_dir; /* data direction register *//*0x010 */
u32 gpio_dirs; /* data dir Set register *//*0x014 */
u32 gpio_dirc; /* data dir Clear register *//*0x018 */
u32 gpio_slpm; /* Sleep mode register *//*0x01C */
u32 gpio_afsa; /* AltFun A Select reg *//*0x020 */
u32 gpio_afsb; /* AltFun B Select reg *//*0x024 */
u32 gpio_lowemi;/* low EMI Select reg *//*0x028 */
u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/
u32 gpio_rimsc; /* rising edge intr set/clear *//*0x040 */
u32 gpio_fimsc; /* falling edge intr set/clear register *//*0x044 */
u32 gpio_mis; /* masked interrupt status register *//*0x048 */
u32 gpio_ic; /* Interrupt Clear register *//*0x04C */
u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register *//*0x050 */
u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register *//*0x054 */
u32 gpio_wks; /* Wakeup Status register *//*0x058 */
};
/* Error values returned by functions */
enum gpio_error {
GPIO_OK = 0,
GPIO_UNSUPPORTED_HW = -2,
GPIO_UNSUPPORTED_FEATURE = -3,
GPIO_INVALID_PARAMETER = -4,
GPIO_REQUEST_NOT_APPLICABLE = -5,
GPIO_REQUEST_PENDING = -6,
GPIO_NOT_CONFIGURED = -7,
GPIO_INTERNAL_ERROR = -8,
GPIO_INTERNAL_EVENT = 1,
GPIO_REMAINING_EVENT = 2,
GPIO_NO_MORE_PENDING_EVENT = 3,
GPIO_INVALID_CLIENT = -25,
GPIO_INVALID_PIN = -26,
GPIO_PIN_BUSY = -27,
GPIO_PIN_NOT_ALLOCATED = -28,
GPIO_WRONG_CLIENT = -29,
GPIO_UNSUPPORTED_ALTFUNC = -30,
};
/*GPIO DEVICE ID */
enum gpio_device_id {
GPIO_DEVICE_ID_0,
GPIO_DEVICE_ID_1,
GPIO_DEVICE_ID_2,
GPIO_DEVICE_ID_3,
GPIO_DEVICE_ID_INVALID
};
/*
* Alternate Function:
* refered in altfun_table to pointout particular altfun to be enabled
* when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
*/
enum gpio_alt_function {
GPIO_ALT_UART_0_MODEM,
GPIO_ALT_UART_0_NO_MODEM,
GPIO_ALT_UART_1,
GPIO_ALT_UART_2,
GPIO_ALT_I2C_0,
GPIO_ALT_I2C_1,
GPIO_ALT_I2C_2,
GPIO_ALT_I2C_3,
GPIO_ALT_MSP_0,
GPIO_ALT_MSP_1,
GPIO_ALT_MSP_2,
GPIO_ALT_MSP_3,
GPIO_ALT_MSP_4,
GPIO_ALT_MSP_5,
GPIO_ALT_SSP_0,
GPIO_ALT_SSP_1,
GPIO_ALT_MM_CARD0,
GPIO_ALT_SD_CARD0,
GPIO_ALT_DMA_0,
GPIO_ALT_DMA_1,
GPIO_ALT_HSI0,
GPIO_ALT_CCIR656_INPUT,
GPIO_ALT_CCIR656_OUTPUT,
GPIO_ALT_LCD_PANEL,
GPIO_ALT_MDIF,
GPIO_ALT_SDRAM,
GPIO_ALT_HAMAC_AUDIO_DBG,
GPIO_ALT_HAMAC_VIDEO_DBG,
GPIO_ALT_CLOCK_RESET,
GPIO_ALT_TSP,
GPIO_ALT_IRDA,
GPIO_ALT_USB_MINIMUM,
GPIO_ALT_USB_I2C,
GPIO_ALT_OWM,
GPIO_ALT_PWL,
GPIO_ALT_FSMC,
GPIO_ALT_COMP_FLASH,
GPIO_ALT_SRAM_NOR_FLASH,
GPIO_ALT_FSMC_ADDLINE_0_TO_15,
GPIO_ALT_SCROLL_KEY,
GPIO_ALT_MSHC,
GPIO_ALT_HPI,
GPIO_ALT_USB_OTG,
GPIO_ALT_SDIO,
GPIO_ALT_HSMMC,
GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
GPIO_ALT_HSI1,
GPIO_ALT_NOR,
GPIO_ALT_NAND,
GPIO_ALT_KEYPAD,
GPIO_ALT_VPIP,
GPIO_ALT_CAM,
GPIO_ALT_CCP1,
GPIO_ALT_EMMC,
GPIO_ALT_POP_EMMC,
GPIO_ALT_FUNMAX /* Add new alt func before this */
};
/* Defines pin assignment(Software mode or Alternate mode) */
enum gpio_mode {
GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */
GPIO_ALTF_A, /* Pin connected to altfunc 1 (HW periph 1) */
GPIO_ALTF_B, /* Pin connected to altfunc 2 (HW periph 2) */
GPIO_ALTF_C, /* Pin connected to altfunc 3 (HW periph 3) */
GPIO_ALTF_FIND, /* Pin connected to altfunc 3 (HW periph 3) */
GPIO_ALTF_DISABLE /* Pin connected to altfunc 3 (HW periph 3) */
};
/* Defines GPIO pin direction */
enum gpio_direction {
GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_DIR_INPUT, /* GPIO set as input */
GPIO_DIR_OUTPUT /* GPIO set as output */
};
/* Interrupt trigger mode */
enum gpio_trig {
GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_TRIG_DISABLE, /* Trigger no IT */
GPIO_TRIG_RISING_EDGE, /* Trigger an IT on rising edge */
GPIO_TRIG_FALLING_EDGE, /* Trigger an IT on falling edge */
GPIO_TRIG_BOTH_EDGES, /* Trigger an IT on rising and falling edge */
GPIO_TRIG_HIGH_LEVEL, /* Trigger an IT on high level */
GPIO_TRIG_LOW_LEVEL /* Trigger an IT on low level */
};
/* Configuration parameters for one GPIO pin.*/
struct gpio_config {
enum gpio_mode mode;
enum gpio_direction direction;
enum gpio_trig trig;
char *dev_name; /* Who owns the gpio pin */
};
/* GPIO pin data*/
enum gpio_data {
GPIO_DATA_LOW,
GPIO_DATA_HIGH
};
/* GPIO behaviour in sleep mode */
enum gpio_sleep_mode {
GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull
up/down enabled when in sleep
mode. */
GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by
GPIO IP. So mode, direction
and data values for GPIO pin
in sleep mode are determined
by configuration set to GPIO
pin before entering to sleep
mode. */
};
/* GPIO ability to wake the system up from sleep mode.*/
enum gpio_wake {
GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_WAKE_DISABLE, /* No wake of system from sleep mode. */
GPIO_WAKE_LOW_LEVEL, /* Wake the system up on a LOW level. */
GPIO_WAKE_HIGH_LEVEL, /* Wake the system up on a HIGH level. */
GPIO_WAKE_RISING_EDGE, /* Wake the system up on a RISING edge. */
GPIO_WAKE_FALLING_EDGE, /* Wake the system up on a FALLING edge. */
GPIO_WAKE_BOTH_EDGES /* Wake the system up on both RISE and FALL. */
};
/* Configuration parameters for one GPIO pin in sleep mode.*/
struct gpio_sleep_config {
enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */
enum gpio_wake wake; /* GPIO ability to wake up system. */
};
extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config);
extern int gpio_resetpinconfig(int pin_id, char *dev_name);
extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name);
extern int gpio_readpin(int pin_id, enum gpio_data *value);
extern int gpio_altfuncenable(enum gpio_alt_function altfunc,
char *dev_name);
extern int gpio_altfuncdisable(enum gpio_alt_function altfunc,
char *dev_name);
struct gpio_altfun_data {
u16 altfun;
u16 start;
u16 end;
u16 cont;
u8 type;
};
#endif

83
arch/arm/include/asm/arch-u8500/hardware.h Normal file
View file

@ -0,0 +1,83 @@
/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/* Peripheral clusters */
#define U8500_PER3_BASE 0x80000000
#define U8500_PER2_BASE 0x80110000
#define U8500_PER1_BASE 0x80120000
#define U8500_PER4_BASE 0x80150000
#define U8500_PER6_BASE 0xa03c0000
#define U8500_PER7_BASE 0xa03d0000
#define U8500_PER5_BASE 0xa03e0000
/* GPIO */
#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80)
#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000)
#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80)
#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100)
#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180)
#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000)
#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80)
#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000)
/* Per7 */
#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
/* Per6 */
#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000)
#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000)
#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
/* Per5 */
#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
/* Per4 */
#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
/* Per3 */
#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
/* Per2 */
#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
/* Per1 */
#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
/* Last page of Boot ROM */
#define U8500_BOOTROM_BASE 0x9001f000
#define U8500_BOOTROM_ASIC_ID_OFFSET 0x0ff4
#endif /* __ASM_ARCH_HARDWARE_H */

27
arch/arm/include/asm/arch-u8500/sys_proto.h Normal file
View file

@ -0,0 +1,27 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
void gpio_init(void);
#endif /* _SYS_PROTO_H_ */

47
arch/arm/include/asm/arch-u8500/u8500.h Normal file
View file

@ -0,0 +1,47 @@
/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __U8500_H
#define __U8500_H
/*
* base register values for U8500
*/
#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock
Management Unit */
#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */
#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
/*
* U8500 GPIO register base for 9 banks
*/
#define U8500_GPIO_0_BASE 0x8012E000
#define U8500_GPIO_1_BASE 0x8012E080
#define U8500_GPIO_2_BASE 0x8000E000
#define U8500_GPIO_3_BASE 0x8000E080
#define U8500_GPIO_4_BASE 0x8000E100
#define U8500_GPIO_5_BASE 0x8000E180
#define U8500_GPIO_6_BASE 0x8011E000
#define U8500_GPIO_7_BASE 0x8011E080
#define U8500_GPIO_8_BASE 0xA03FE000
#endif /* __U8500_H */

1
board/armltd/vexpress/ca9x4_ct_vxp.c
View file

@ -38,6 +38,7 @@
#include <asm/arch/systimer.h>
#include <asm/arch/sysctrl.h>
#include <asm/arch/wdt.h>
#include "../drivers/mmc/arm_pl180_mmci.h"
static ulong timestamp;
static ulong lastdec;

42
board/efikamx/efikamx.c
View file

@ -643,47 +643,7 @@ int board_late_init(void)
int checkboard(void)
{
u32 system_rev = get_cpu_rev();
u32 cause;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
puts("Board: Efika MX ");
switch (system_rev & 0xff) {
case CHIP_REV_3_0:
puts("3.0 [");
break;
case CHIP_REV_2_5:
puts("2.5 [");
break;
case CHIP_REV_2_0:
puts("2.0 [");
break;
case CHIP_REV_1_1:
puts("1.1 [");
break;
case CHIP_REV_1_0:
default:
puts("1.0 [");
break;
}
cause = src_regs->srsr;
switch (cause) {
case 0x0001:
puts("POR");
break;
case 0x0009:
puts("RST");
break;
case 0x0010:
case 0x0011:
puts("WDOG");
break;
default:
printf("unknown 0x%x", cause);
}
puts("]\n");
puts("Board: Efika MX\n");
return 0;
}

36
board/freescale/mx51evk/mx51evk.c
View file

@ -431,41 +431,7 @@ int board_late_init(void)
int checkboard(void)
{
puts("Board: MX51EVK ");
puts("Board: MX51EVK\n");
switch (system_rev & 0xff) {
case CHIP_REV_3_0:
puts("3.0 [");
break;
case CHIP_REV_2_5:
puts("2.5 [");
break;
case CHIP_REV_2_0:
puts("2.0 [");
break;
case CHIP_REV_1_1:
puts("1.1 [");
break;
case CHIP_REV_1_0:
default:
puts("1.0 [");
break;
}
switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
case 0x0001:
puts("POR");
break;
case 0x0009:
puts("RST");
break;
case 0x0010:
case 0x0011:
puts("WDOG");
break;
default:
puts("unknown");
}
puts("]\n");
return 0;
}

21
board/freescale/mx53evk/mx53evk.c
View file

@ -372,26 +372,7 @@ int board_late_init(void)
int checkboard(void)
{
u32 cause;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
puts("Board: MX53EVK\n");
puts("Board: MX53EVK [");
cause = src_regs->srsr;
switch (cause) {
case 0x0001:
printf("POR");
break;
case 0x0009:
printf("RST");
break;
case 0x0010:
case 0x0011:
printf("WDOG");
break;
default:
printf("unknown");
}
printf("]\n");
return 0;
}

47
board/freescale/mx53loco/Makefile Normal file
View file

@ -0,0 +1,47 @@
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
# Jason Liu <r64343@freescale.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := mx53loco.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

96
board/freescale/mx53loco/imximage.cfg Normal file
View file

@ -0,0 +1,96 @@
# Copyright (C) 2011 Freescale Semiconductor, Inc.
# Jason Liu <r64343@freescale.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# image version
IMAGE_VERSION 2
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
BOOT_FROM sd
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
DATA 4 0x53fa8564 0x00300040
DATA 4 0x53fa8568 0x00300040
DATA 4 0x53fa8570 0x00300000
DATA 4 0x53fa8574 0x00300000
DATA 4 0x53fa8578 0x00300000
DATA 4 0x53fa857c 0x00300040
DATA 4 0x53fa8580 0x00300040
DATA 4 0x53fa8584 0x00300000
DATA 4 0x53fa8588 0x00300000
DATA 4 0x53fa8590 0x00300040
DATA 4 0x53fa8594 0x00300000
DATA 4 0x53fa86f0 0x00300000
DATA 4 0x53fa86f4 0x00000000
DATA 4 0x53fa86fc 0x00000000
DATA 4 0x53fa8714 0x00000000
DATA 4 0x53fa8718 0x00300000
DATA 4 0x53fa871c 0x00300000
DATA 4 0x53fa8720 0x00300000
DATA 4 0x53fa8724 0x04000000
DATA 4 0x53fa8728 0x00300000
DATA 4 0x53fa872c 0x00300000
DATA 4 0x63fd9088 0x35343535
DATA 4 0x63fd9090 0x4d444c44
DATA 4 0x63fd907c 0x01370138
DATA 4 0x63fd9080 0x013b013c
DATA 4 0x63fd9018 0x00011740
DATA 4 0x63fd9000 0xc3190000
DATA 4 0x63fd900c 0x9f5152e3
DATA 4 0x63fd9010 0xb68e8a63
DATA 4 0x63fd9014 0x01ff00db
DATA 4 0x63fd902c 0x000026d2
DATA 4 0x63fd9030 0x009f0e21
DATA 4 0x63fd9008 0x12273030
DATA 4 0x63fd9004 0x0002002d
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x092080b0
DATA 4 0x63fd901c 0x04008040
DATA 4 0x63fd901c 0x0000803a
DATA 4 0x63fd901c 0x0000803b
DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x09208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00001800
DATA 4 0x63fd9040 0x04b80003
DATA 4 0x63fd9058 0x00022227
DATA 4 0x63fd901c 0x00000000

302
board/freescale/mx53loco/mx53loco.c Normal file
View file

@ -0,0 +1,302 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <mxc_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
u32 get_board_rev(void)
{
return get_cpu_rev();
}
int dram_init(void)
{
u32 size1, size2;
size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->ram_size = size1 + size2;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
static void setup_iomux_uart(void)
{
/* UART1 RXD */
mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_ENABLE);
mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
/* UART1 TXD */
mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
static void setup_iomux_fec(void)
{
/*FEC_MDIO*/
mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
/*FEC_MDC*/
mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
/* FEC RXD1 */
mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC RXD0 */
mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC TXD1 */
mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
/* FEC TXD0 */
mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
/* FEC TX_EN */
mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
/* FEC TX_CLK */
mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC RX_ER */
mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC CRS */
mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR, 1},
{MMC_SDHC3_BASE_ADDR, 1},
};
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
*cd = mxc_gpio_get(77); /*GPIO3_13*/
else
*cd = mxc_gpio_get(75); /*GPIO3_11*/
return 0;
}
int board_mmc_init(bd_t *bis)
{
u32 index;
s32 status = 0;
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA0,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA1,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA2,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA3,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_EIM_DA13,
IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
PAD_CTL_DRV_HIGH);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
break;
case 1:
mxc_request_iomux(MX53_PIN_ATA_RESET_B,
IOMUX_CONFIG_ALT2);
mxc_request_iomux(MX53_PIN_ATA_IORDY,
IOMUX_CONFIG_ALT2);
mxc_request_iomux(MX53_PIN_ATA_DATA8,
IOMUX_CONFIG_ALT4);
mxc_request_iomux(MX53_PIN_ATA_DATA9,
IOMUX_CONFIG_ALT4);
mxc_request_iomux(MX53_PIN_ATA_DATA10,
IOMUX_CONFIG_ALT4);
mxc_request_iomux(MX53_PIN_ATA_DATA11,
IOMUX_CONFIG_ALT4);
mxc_request_iomux(MX53_PIN_ATA_DATA0,
IOMUX_CONFIG_ALT4);
mxc_request_iomux(MX53_PIN_ATA_DATA1,
IOMUX_CONFIG_ALT4);
mxc_request_iomux(MX53_PIN_ATA_DATA2,
IOMUX_CONFIG_ALT4);
mxc_request_iomux(MX53_PIN_ATA_DATA3,
IOMUX_CONFIG_ALT4);
mxc_request_iomux(MX53_PIN_EIM_DA11,
IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
PAD_CTL_DRV_HIGH);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
break;
default:
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return status;
}
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
}
return status;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
return 0;
}
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_MX53_LOCO;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int checkboard(void)
{
puts("Board: MX53 LOCO\n");
return 0;
}

48
board/freescale/mx53smd/Makefile Normal file
View file

@ -0,0 +1,48 @@
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := mx53smd.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

96
board/freescale/mx53smd/imximage.cfg Normal file
View file

@ -0,0 +1,96 @@
#
# (C) Copyright 2009
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# image version
IMAGE_VERSION 2
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
BOOT_FROM sd
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000
DATA 4 0x53fa8564 0x00300040
DATA 4 0x53fa8568 0x00300040
DATA 4 0x53fa8570 0x00300000
DATA 4 0x53fa8574 0x00300000
DATA 4 0x53fa8578 0x00300000
DATA 4 0x53fa857c 0x00300040
DATA 4 0x53fa8580 0x00300040
DATA 4 0x53fa8584 0x00300000
DATA 4 0x53fa8588 0x00300000
DATA 4 0x53fa8590 0x00300040
DATA 4 0x53fa8594 0x00300000
DATA 4 0x53fa86f0 0x00300000
DATA 4 0x53fa86f4 0x00000000
DATA 4 0x53fa86fc 0x00000000
DATA 4 0x53fa8714 0x00000000
DATA 4 0x53fa8718 0x00300000
DATA 4 0x53fa871c 0x00300000
DATA 4 0x53fa8720 0x00300000
DATA 4 0x53fa8724 0x04000000
DATA 4 0x53fa8728 0x00300000
DATA 4 0x53fa872c 0x00300000
DATA 4 0x63fd9088 0x35343535
DATA 4 0x63fd9090 0x4d444c44
DATA 4 0x63fd907c 0x01370138
DATA 4 0x63fd9080 0x013b013c
DATA 4 0x63fd9018 0x00011740
DATA 4 0x63fd9000 0xc3190000
DATA 4 0x63fd900c 0x9f5152e3
DATA 4 0x63fd9010 0xb68e8a63
DATA 4 0x63fd9014 0x01ff00db
DATA 4 0x63fd902c 0x000026d2
DATA 4 0x63fd9030 0x009f0e21
DATA 4 0x63fd9008 0x12273030
DATA 4 0x63fd9004 0x0002002d
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x092080b0
DATA 4 0x63fd901c 0x04008040
DATA 4 0x63fd901c 0x0000803a
DATA 4 0x63fd901c 0x0000803b
DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x09208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00001800
DATA 4 0x63fd9040 0x04b80003
DATA 4 0x63fd9058 0x00022227
DATA 4 0x63fd901C 0x00000000

229
board/freescale/mx53smd/mx53smd.c Normal file
View file

@ -0,0 +1,229 @@
/*
* (C) Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/errno.h>
#include <netdev.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <mxc_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
u32 get_board_rev(void)
{
return get_cpu_rev();
}
int dram_init(void)
{
u32 size1, size2;
size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
gd->ram_size = size1 + size2;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
static void setup_iomux_uart(void)
{
/* UART1 RXD */
mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_ENABLE);
mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
/* UART1 TXD */
mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
static void setup_iomux_fec(void)
{
/*FEC_MDIO*/
mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
/*FEC_MDC*/
mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
/* FEC RXD1 */
mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC RXD0 */
mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC TXD1 */
mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
/* FEC TXD0 */
mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
/* FEC TX_EN */
mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
/* FEC TX_CLK */
mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC RX_ER */
mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
/* FEC CRS */
mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{MMC_SDHC1_BASE_ADDR, 1},
};
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
*cd = mxc_gpio_get(77); /*GPIO3_13*/
return 0;
}
int board_mmc_init(bd_t *bis)
{
u32 index;
s32 status = 0;
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA0,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA1,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA2,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA3,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_EIM_DA13,
IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
PAD_CTL_DRV_HIGH);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
break;
default:
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(1)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return status;
}
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
}
return status;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
return 0;
}
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_MX53_SMD;
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int checkboard(void)
{
puts("Board: MX53SMD\n");
return 0;
}

108
board/keymile/km_arm/km_arm.c
View file

@ -41,6 +41,16 @@
DECLARE_GLOBAL_DATA_PTR;
/*
* BOCO FPGA definitions
*/
#define BOCO 0x10
#define REG_CTRL_H 0x02
#define MASK_WRL_UNITRUN 0x01
#define MASK_RBX_PGY_PRESENT 0x40
#define REG_IRQ_CIRQ2 0x2d
#define MASK_RBI_DEFECT_16 0x01
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
MPP0_NF_IO2,
@ -102,68 +112,119 @@ u32 kwmpp_config[] = {
0
};
#if defined(CONFIG_MGCOGE3UN)
/*
* Wait for startup OK from mgcoge3ne
*/
int startup_allowed(void)
{
unsigned char buf;
/*
* Read CIRQ16 bit (bit 0)
*/
if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
printf("%s: Error reading Boco\n", __func__);
else
if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
return 1;
return 0;
}
/*
* mgcoge3un has always ethernet present. Its connected to the 6061 switch
* and provides ICNev and piggy4 connections.
*/
int ethernet_present(void)
{
return 1;
}
#else
int ethernet_present(void)
{
uchar buf;
int ret = 0;
if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
printf("%s: Error reading Boco\n", __func__);
return -1;
}
if ((buf & 0x40) == 0x40)
if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
ret = 1;
return ret;
}
#endif
int initialize_unit_leds(void)
{
/*
* init the unit LEDs
* per default they all are
* Init the unit LEDs per default they all are
* ok apart from bootstat
* LED connected through BOCO
* BOCO lies at the address 0x10
* LEDs are in the block CTRL_H (addr 0x02)
* BOOTSTAT LED is the first 0x01
*/
#define BOCO 0x10
#define CTRL_H 0x02
#define APPLEDMASK 0x01
uchar buf;
if (i2c_read(BOCO, CTRL_H, 1, &buf, 1) != 0) {
if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
printf("%s: Error reading Boco\n", __func__);
return -1;
}
buf |= APPLEDMASK;
if (i2c_write(BOCO, CTRL_H, 1, &buf, 1) != 0) {
buf |= MASK_WRL_UNITRUN;
if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
printf("%s: Error writing Boco\n", __func__);
return -1;
}
return 0;
}
#if defined(CONFIG_BOOTCOUNT_LIMIT)
void set_bootcount_addr(void)
{
uchar buf[32];
unsigned int bootcountaddr;
bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
sprintf((char *)buf, "0x%x", bootcountaddr);
setenv("bootcountaddr", (char *)buf);
}
#endif
int misc_init_r(void)
{
char *str;
int mach_type;
puts("Piggy:");
if (ethernet_present() == 0)
puts (" not");
puts(" present\n");
str = getenv("mach_type");
if (str != NULL) {
mach_type = simple_strtoul(str, NULL, 10);
printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
gd->bd->bi_arch_number = mach_type;
}
#if defined(CONFIG_MGCOGE3UN)
char *wait_for_ne;
wait_for_ne = getenv("waitforne");
if (wait_for_ne != NULL) {
if (strcmp(wait_for_ne, "true") == 0) {
int cnt = 0;
puts("NE go: ");
while (startup_allowed() == 0) {
udelay(200000);
cnt++;
if (cnt == 5)
puts("wait\b\b\b\b");
if (cnt == 10) {
cnt = 0;
puts(" \b\b\b\b");
}
}
puts("OK\n");
}
}
#endif
initialize_unit_leds();
set_km_env();
#if defined(CONFIG_BOOTCOUNT_LIMIT)
set_bootcount_addr();
#endif
return 0;
}
@ -182,7 +243,6 @@ int board_early_init_f(void)
writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
tmp = readl(KW_GPIO0_BASE + 4);
writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
printf("KM: setting NAND mode\n");
#if defined(CONFIG_SOFT_I2C)
/* init the GPIO for I2C Bitbang driver */
@ -212,12 +272,6 @@ int board_init(void)
return 0;
}
int last_stage_init(void)
{
set_km_env();
return 0;
}
#if defined(CONFIG_CMD_SF)
int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{

197
board/keymile/km_arm/kwbimage-memphis.cfg Normal file
View file

@ -0,0 +1,197 @@
#
# (C) Copyright 2010
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
#
# (C) Copyright 2011
# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
# Refer docs/README.kwimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM spi # Boot from SPI flash
DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
# bit 3-0: MPPSel0 2, NF_IO[2]
# bit 7-4: MPPSel1 2, NF_IO[3]
# bit 12-8: MPPSel2 2, NF_IO[4]
# bit 15-12: MPPSel3 2, NF_IO[5]
# bit 19-16: MPPSel4 1, NF_IO[6]
# bit 23-20: MPPSel5 1, NF_IO[7]
# bit 27-24: MPPSel6 1, SYSRST_O
# bit 31-28: MPPSel7 0, GPO[7]
DATA 0xFFD10004 0x03303300
DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
# bit 3-0: MPPSel16 0, GPIO[16]
# bit 7-4: MPPSel17 0, GPIO[17]
# bit 12-8: MPPSel18 1, NF_IO[0]
# bit 15-12: MPPSel19 1, NF_IO[1]
# bit 19-16: MPPSel20 0, GPIO[20]
# bit 23-20: MPPSel21 0, GPIO[21]
# bit 27-24: MPPSel22 0, GPIO[22]
# bit 31-28: MPPSel23 0, GPIO[23]
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
#Dram initalization
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
# bit13-0: 0x4E0 (DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
# bit 3-0: 0 reserved
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x00000001 # DDR Address Control
# bit1-0: 01, Cs0width=x16
# bit3-2: 00, Cs0size=2Gb
# bit5-4: 00, Cs2width=nonexistent
# bit7-6: 00, Cs1size =nonexistent
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000652 # DDR Mode
DATA 0xFFD01420 0x00000006 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 1, DDR drive strenght reduced
# bit2: 1, DDR ODT control lsd disabled
# bit5-3: 000, required
# bit6: 0, DDR ODT control msb disabled
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 0
# bit8 : 1 , add a sample stage
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
# bit3-0 : 0000, required
# bit7-4 : 0010, M_ODT assertion 2 cycles after read
# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read
# bit15-12: 0100, internal ODT assertion 4 cycles after read
# bit19-16: 1000, internal ODT de-assertion 8 cycles after read
# bit31-20: 0 , required
DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High
# bit3-0 : 0001, M_ODT assertion same cycle as write
# bit7-4 : 0101, M_ODT de-assertion x cycles after write
# bit11-8 : 0100, internal ODT assertion x cycles after write
# bit15-12: 1000, internal ODT de-assertion x cycles after write
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x0F, Size (i.e. 256MB)
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
# bit3-2: 00, ODT1 controlled by register
# bit31-4: zero, required
DATA 0xFFD0149C 0x0000F801 # CPU ODT Control
# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm
# bit14 :1, STARTBURST ODT enabled
# bit15 :1, Use ODT Block
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
# bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

2
board/samsung/smdk2410/Makefile
View file

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := smdk2410.o flash.o
COBJS := smdk2410.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)

25
board/samsung/smdk2410/config.mk
View file

@ -1,25 +0,0 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
#
# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
#
# see http://www.samsung.com/ for more information on SAMSUNG
#
#
# SMDK2410 has 1 bank of 64 MB DRAM
#
# 3000'0000 to 3400'0000
#
# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
# optionally with a ramdisk at 3080'0000
#
# we load ourself to 33F8'0000
#
# download area is 3300'0000
#
CONFIG_SYS_TEXT_BASE = 0x33F80000

433
board/samsung/smdk2410/flash.c
View file

@ -1,433 +0,0 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
ulong myflush (void);
#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
#define CMD_READ_ARRAY 0x000000F0
#define CMD_UNLOCK1 0x000000AA
#define CMD_UNLOCK2 0x00000055
#define CMD_ERASE_SETUP 0x00000080
#define CMD_ERASE_CONFIRM 0x00000030
#define CMD_PROGRAM 0x000000A0
#define CMD_UNLOCK_BYPASS 0x00000020
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1)))
#define BIT_ERASE_DONE 0x00000080
#define BIT_RDY_MASK 0x00000080
#define BIT_PROGRAM_ERROR 0x00000020
#define BIT_TIMEOUT 0x80000000 /* our flag */
#define READY 1
#define ERR 2
#define TMO 4
/*-----------------------------------------------------------------------
*/
ulong flash_init (void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id =
#if defined(CONFIG_AMD_LV400)
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_LV400B & FLASH_TYPEMASK);
#elif defined(CONFIG_AMD_LV800)
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_LV800B & FLASH_TYPEMASK);
#else
#error "Unknown flash configured"
#endif
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
if (i == 0)
flashbase = PHYS_FLASH_1;
else
panic ("configured too many flash banks!\n");
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j <= 3) {
/* 1st one is 16 KB */
if (j == 0) {
flash_info[i].start[j] =
flashbase + 0;
}
/* 2nd and 3rd are both 8 KB */
if ((j == 1) || (j == 2)) {
flash_info[i].start[j] =
flashbase + 0x4000 + (j -
1) *
0x2000;
}
/* 4th 32 KB */
if (j == 3) {
flash_info[i].start[j] =
flashbase + 0x8000;
}
} else {
flash_info[i].start[j] =
flashbase + (j - 3) * MAIN_SECT_SIZE;
}
}
size += flash_info[i].size;
}
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case (AMD_MANUFACT & FLASH_VENDMASK):
printf ("AMD: ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (AMD_ID_LV400B & FLASH_TYPEMASK):
printf ("1x Amd29LV400BB (4Mbit)\n");
break;
case (AMD_ID_LV800B & FLASH_TYPEMASK):
printf ("1x Amd29LV800BB (8Mbit)\n");
break;
default:
printf ("Unknown Chip Type\n");
goto Done;
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
Done:;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
ushort result;
int iflag, cflag, prot, sect;
int rc = ERR_OK;
int chip;
/* first look for protection bits */
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last)) {
return ERR_INVAL;
}
if ((info->flash_id & FLASH_VENDMASK) !=
(AMD_MANUFACT & FLASH_VENDMASK)) {
return ERR_UNKNOWN_FLASH_VENDOR;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
return ERR_PROTECTED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
printf ("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
if (info->protect[sect] == 0) { /* not protected */
vu_short *addr = (vu_short *) (info->start[sect]);
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
*addr = CMD_ERASE_CONFIRM;
/* wait until flash is ready */
chip = 0;
do {
result = *addr;
/* check timeout */
if (get_timer_masked () >
CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
chip = TMO;
break;
}
if (!chip
&& (result & 0xFFFF) & BIT_ERASE_DONE)
chip = READY;
if (!chip
&& (result & 0xFFFF) & BIT_PROGRAM_ERROR)
chip = ERR;
} while (!chip);
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
if (chip == ERR) {
rc = ERR_PROG_ERROR;
goto outahere;
}
if (chip == TMO) {
rc = ERR_TIMOUT;
goto outahere;
}
printf ("ok.\n");
} else { /* it was protected */
printf ("protected!\n");
}
}
if (ctrlc ())
printf ("User Interrupt!\n");
outahere:
/* allow flash to settle - wait 10 ms */
udelay_masked (10000);
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash
*/
static int write_hword (flash_info_t * info, ulong dest, ushort data)
{
vu_short *addr = (vu_short *) dest;
ushort result;
int rc = ERR_OK;
int cflag, iflag;
int chip;
/*
* Check if Flash is (sufficiently) erased
*/
result = *addr;
if ((result & data) != data)
return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
*addr = CMD_PROGRAM;
*addr = data;
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
/* wait until flash is ready */
chip = 0;
do {
result = *addr;
/* check timeout */
if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
chip = ERR | TMO;
break;
}
if (!chip && ((result & 0x80) == (data & 0x80)))
chip = READY;
if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
result = *addr;
if ((result & 0x80) == (data & 0x80))
chip = READY;
else
chip = ERR;
}
} while (!chip);
*addr = CMD_READ_ARRAY;
if (chip == ERR || *addr != data)
rc = ERR_PROG_ERROR;
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash.
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
int l;
int i, rc;
ushort data;
wp = (addr & ~1); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
for (; i < 2 && cnt > 0; ++i) {
data = (data >> 8) | (*src++ << 8);
--cnt;
++cp;
}
for (; cnt == 0 && i < 2; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
if ((rc = write_hword (info, wp, data)) != 0) {
return (rc);
}
wp += 2;
}
/*
* handle word aligned part
*/
while (cnt >= 2) {
data = *((vu_short *) src);
if ((rc = write_hword (info, wp, data)) != 0) {
return (rc);
}
src += 2;
wp += 2;
cnt -= 2;
}
if (cnt == 0) {
return ERR_OK;
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
data = (data >> 8) | (*src++ << 8);
--cnt;
}
for (; i < 2; ++i, ++cp) {
data = (data >> 8) | (*(uchar *) cp << 8);
}
return write_hword (info, wp, data);
}

73
board/samsung/smdk2410/smdk2410.c
View file

@ -3,7 +3,7 @@
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* (C) Copyright 2002, 2010
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* See file CREDITS for list of people who contributed to this
@ -27,6 +27,7 @@
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;
@ -55,7 +56,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define U_M_SDIV 0x2
#endif
static inline void delay (unsigned long loops)
static inline void pll_delay(unsigned long loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
@ -66,44 +67,51 @@ static inline void delay (unsigned long loops)
* Miscellaneous platform dependent initialisations
*/
int board_init (void)
int board_early_init_f(void)
{
struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->locktime = 0xFFFFFF;
writel(0xFFFFFF, &clk_power->locktime);
/* configure MPLL */
clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
&clk_power->mpllcon);
/* some delay between MPLL and UPLL */
delay (4000);
pll_delay(4000);
/* configure UPLL */
clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
&clk_power->upllcon);
/* some delay between MPLL and UPLL */
delay (8000);
pll_delay(8000);
/* set up the I/O ports */
gpio->gpacon = 0x007FFFFF;
gpio->gpbcon = 0x00044555;
gpio->gpbup = 0x000007FF;
gpio->gpccon = 0xAAAAAAAA;
gpio->gpcup = 0x0000FFFF;
gpio->gpdcon = 0xAAAAAAAA;
gpio->gpdup = 0x0000FFFF;
gpio->gpecon = 0xAAAAAAAA;
gpio->gpeup = 0x0000FFFF;
gpio->gpfcon = 0x000055AA;
gpio->gpfup = 0x000000FF;
gpio->gpgcon = 0xFF95FFBA;
gpio->gpgup = 0x0000FFFF;
gpio->gphcon = 0x002AFAAA;
gpio->gphup = 0x000007FF;
writel(0x007FFFFF, &gpio->gpacon);
writel(0x00044555, &gpio->gpbcon);
writel(0x000007FF, &gpio->gpbup);
writel(0xAAAAAAAA, &gpio->gpccon);
writel(0x0000FFFF, &gpio->gpcup);
writel(0xAAAAAAAA, &gpio->gpdcon);
writel(0x0000FFFF, &gpio->gpdup);
writel(0xAAAAAAAA, &gpio->gpecon);
writel(0x0000FFFF, &gpio->gpeup);
writel(0x000055AA, &gpio->gpfcon);
writel(0x000000FF, &gpio->gpfup);
writel(0xFF95FFBA, &gpio->gpgcon);
writel(0x0000FFFF, &gpio->gpgup);
writel(0x002AFAAA, &gpio->gphcon);
writel(0x000007FF, &gpio->gphup);
return 0;
}
int board_init(void)
{
/* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
@ -116,11 +124,10 @@ int board_init (void)
return 0;
}
int dram_init (void)
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
@ -134,3 +141,15 @@ int board_eth_init(bd_t *bis)
return rc;
}
#endif
/*
* Hardcoded flash setup:
* Flash 0 is a non-CFI AMD AM29LV800BB flash.
*/
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
info->portwidth = FLASH_CFI_16BIT;
info->chipwidth = FLASH_CFI_BY16;
info->interface = FLASH_CFI_X16;
return 1;
}

4
board/samsung/smdkc100/smdkc100.c
View file

@ -24,7 +24,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/smc.h>
#include <asm/arch/sromc.h>
#include <asm/arch/gpio.h>
#include <netdev.h>
@ -50,7 +50,7 @@ static void smc9115_pre_init(void)
| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
/* Select and configure the SROMC bank */
s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
}
int board_init(void)

29
board/efikamx/config.mk → board/samsung/smdkv310/Makefile
View file

@ -1,5 +1,5 @@
#
# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
# Copyright (C) 2011 Samsung Electronics
#
# See file CREDITS for list of people who contributed to this
# project.
@ -20,6 +20,27 @@
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0x97800000
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
ALL += $(obj)u-boot.imx
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
SOBJS := mem_setup.o
SOBJS += lowlevel_init.o
COBJS += smdkv310.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

470
board/samsung/smdkv310/lowlevel_init.S Normal file
View file

@ -0,0 +1,470 @@
/*
* Lowlevel setup for SMDKV310 board based on S5PC210
*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/cpu.h>
/*
* Register usages:
*
* r5 has zero always
* r7 has GPIO part1 base 0x11400000
* r6 has GPIO part2 base 0x11000000
*/
#define MEM_DLLl_ON
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl lowlevel_init
lowlevel_init:
push {lr}
/* r5 has always zero */
mov r5, #0
ldr r7, =S5PC210_GPIO_PART1_BASE
ldr r6, =S5PC210_GPIO_PART2_BASE
/* check reset status */
ldr r0, =(S5PC210_POWER_BASE + 0x81C) @ INFORM7
ldr r1, [r0]
/* AFTR wakeup reset */
ldr r2, =S5P_CHECK_DIDLE
cmp r1, r2
beq exit_wakeup
/* Sleep wakeup reset */
ldr r2, =S5P_CHECK_SLEEP
cmp r1, r2
beq wakeup_reset
/*
* If U-boot is already running in ram, no need to relocate U-Boot.
* Memory controller must be configured before relocating U-Boot
* in ram.
*/
ldr r0, =0x00ffffff /* r0 <- Mask Bits*/
bic r1, pc, r0 /* pc <- current addr of code */
/* r1 <- unmasked bits of pc */
ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
cmp r1, r2 /* compare r1, r2 */
beq 1f /* r0 == r1 then skip sdram init */
/* init system clock */
bl system_clock_init
/* Memory initialize */
bl mem_ctrl_asm_init
1:
/* for UART */
bl uart_asm_init
bl tzpc_init
pop {pc}
wakeup_reset:
bl system_clock_init
bl mem_ctrl_asm_init
bl tzpc_init
exit_wakeup:
/* Load return address and jump to kernel */
ldr r0, =(S5PC210_POWER_BASE + 0x800) @ INFORM0
/* r1 = physical address of s5pc210_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel*/
mov pc, r1
nop
nop
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
system_clock_init:
push {lr}
ldr r0, =S5PC210_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =0x0101
ldr r2, =0x14200 @CLK_SRC_CPU
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x10000
2: subs r1, r1, #1
bne 2b
ldr r1, =0x00
ldr r2, =0x0C210 @CLK_SRC_TOP0
str r1, [r0, r2]
ldr r1, =0x00
ldr r2, =0x0C214 @CLK_SRC_TOP1_OFFSET
str r1, [r0, r2]
/* DMC */
ldr r1, =0x00
ldr r2, =0x10200 @CLK_SRC_DMC_OFFSET
str r1, [r0, r2]
/*CLK_SRC_LEFTBUS */
ldr r1, =0x00
ldr r2, =0x04200 @CLK_SRC_LEFTBUS_OFFSET
str r1, [r0, r2]
/*CLK_SRC_RIGHTBUS */
ldr r1, =0x00
ldr r2, =0x08200 @CLK_SRC_RIGHTBUS_OFFSET
str r1, [r0, r2]
/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
ldr r1, =0x066666
ldr r2, =0x0C240 @ CLK_SRC_FSYS
str r1, [r0, r2]
/* UART[0:4], PWM: SCLKMPLL(6) */
ldr r1, =0x06666666
ldr r2, =0x0C250 @CLK_SRC_PERIL0_OFFSET
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x10000
3: subs r1, r1, #1
bne 3b
/*
* CLK_DIV_CPU0:
*
* PCLK_DBG_RATIO[20] 0x1
* ATB_RATIO[16] 0x3
* PERIPH_RATIO[12] 0x3
* COREM1_RATIO[8] 0x7
* COREM0_RATIO[4] 0x3
*/
ldr r1, =0x0133730
ldr r2, =0x14500 @CLK_DIV_CPU0_OFFSET
str r1, [r0, r2]
/* CLK_DIV_CPU1: COPY_RATIO [0] 0x3 */
ldr r1, =0x03
ldr r2, =0x14504 @CLK_DIV_CPU1_OFFSET
str r1, [r0, r2]
/*
* CLK_DIV_DMC0:
*
* CORE_TIMERS_RATIO[28] 0x1
* COPY2_RATIO[24] 0x3
* DMCP_RATIO[20] 0x1
* DMCD_RATIO[16] 0x1
* DMC_RATIO[12] 0x1
* DPHY_RATIO[8] 0x1
* ACP_PCLK_RATIO[4] 0x1
* ACP_RATIO[0] 0x3
*/
ldr r1, =0x13111113
ldr r2, =0x010500 @CLK_DIV_DMC0_OFFSET
str r1, [r0, r2]
/*
* CLK_DIV_DMC1:
*
* DPM_RATIO[24] 0x1
* DVSEM_RATIO[16] 0x1
* PWI_RATIO[8] 0x1
*/
ldr r1, =0x01010100
ldr r2, =0x010504 @CLK_DIV_DMC1_OFFSET
str r1, [r0, r2]
/*
* CLK_DIV_LEFRBUS:
*
* GPL_RATIO[4] 0x1
* GDL_RATIO[0] 0x3
*/
ldr r1, =0x013
ldr r2, =0x04500 @CLK_DIV_LEFTBUS_OFFSET
str r1, [r0, r2]
/*
* CLK_DIV_RIGHTBUS:
*
* GPR_RATIO[4] 0x1
* GDR_RATIO[0] 0x3
*/
ldr r1, =0x013
ldr r2, =0x08500 @CLK_DIV_RIGHTBUS_OFFSET
str r1, [r0, r2]
/*
* CLK_DIV_TOP:
*
* ONENAND_RATIO[16] 0x0
* ACLK_133_RATIO[12] 0x5
* ACLK_160_RATIO[8] 0x4
* ACLK_100_RATIO[4] 0x7
* ACLK_200_RATIO[0] 0x3
*/
ldr r1, =0x05473
ldr r2, =0x0C510 @CLK_DIV_TOP_OFFSET
str r1, [r0, r2]
/* MMC[0:1] */
ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
ldr r2, =0x0C544 @ CLK_DIV_FSYS1
str r1, [r0, r2]
/* MMC[2:3] */
ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
ldr r2, =0x0C548 @ CLK_DIV_FSYS2
str r1, [r0, r2]
/* MMC4 */
ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
ldr r2, =0x0C54C @ CLK_DIV_FSYS3
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x10000
4: subs r1, r1, #1
bne 4b
/*
* CLK_DIV_PERIL0:
*
* UART5_RATIO[20] 8
* UART4_RATIO[16] 8
* UART3_RATIO[12] 8
* UART2_RATIO[8] 8
* UART1_RATIO[4] 8
* UART0_RATIO[0] 8
*/
ldr r1, =0x774777
ldr r2, =0x0C550 @CLK_DIV_PERIL0_OFFSET
str r1, [r0, r2]
/* SLIMBUS: ???, PWM */
ldr r1, =0x8
ldr r2, =0x0C55C @ CLK_DIV_PERIL3
str r1, [r0, r2]
/* Set PLL locktime */
ldr r1, =0x01C20
ldr r2, =0x014000 @APLL_LOCK_OFFSET
str r1, [r0, r2]
ldr r1, =0x01C20
ldr r2, =0x014008 @MPLL_LOCK_OFFSET
str r1, [r0, r2]
ldr r1, =0x01C20
ldr r2, =0x0C010 @EPLL_LOCK_OFFSET
str r1, [r0, r2]
ldr r1, =0x01C20
ldr r2, =0x0C020 @VPLL_LOCK_OFFSET
str r1, [r0, r2]
/*
* APLL_CON1:
*
* APLL_AFC_ENB[31] 0x1
* APLL_AFC[0] 0xC
*/
ldr r1, =0x8000000C
ldr r2, =0x014104 @APLL_CON1_OFFSET
str r1, [r0, r2]
/*
* APLL_CON0:
*
* APLL_MDIV[16] 0xFA
* APLL_PDIV[8] 0x6
* APLL_SDIV[0] 0x1
*/
ldr r1, =0x80FA0601
ldr r2, =0x014100 @APLL_CON0_OFFSET
str r1, [r0, r2]
/*
* MPLL_CON1:
*
* MPLL_AFC_ENB[31] 0x1
* MPLL_AFC[0] 0x1C
*/
ldr r1, =0x0000001C
ldr r2, =0x01410C @MPLL_CON1_OFFSET
str r1, [r0, r2]
/*
* MPLL_CON0:
*
* MPLL_MDIV[16] 0xC8
* MPLL_PDIV[8] 0x6
* MPLL_SDIV[0] 0x1
*/
ldr r1, =0x80C80601
ldr r2, =0x014108 @MPLL_CON0_OFFSET
str r1, [r0, r2]
/* EPLL */
ldr r1, =0x0
ldr r2, =0x0C114 @EPLL_CON1_OFFSET
str r1, [r0, r2]
/*
* EPLL_CON0:
*
* EPLL_MDIV[16] 0x30
* EPLL_PDIV[8] 0x3
* EPLL_SDIV[0] 0x2
*/
ldr r1, =0x80300302
ldr r2, =0x0C110 @EPLL_CON0_OFFSET
str r1, [r0, r2]
/*
* VPLL_CON1:
*
* VPLL_MRR[24] 0x11
* VPLL_MFR[16] 0x0
* VPLL_K[0] 0x400
*/
ldr r1, =0x11000400
ldr r2, =0x0C124 @VPLL_CON1_OFFSET
str r1, [r0, r2]
/*
* VPLL_CON0:
*
* VPLL_MDIV[16] 0x35
* VPLL_PDIV[8] 0x3
* VPLL_SDIV[0] 0x2
*/
ldr r1, =0x80350302
ldr r2, =0x0C120 @VPLL_CON0_OFFSET
str r1, [r0, r2]
/* wait ?us */
mov r1, #0x30000
3: subs r1, r1, #1
bne 3b
pop {pc}
/*
* uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
* void uart_asm_init(void)
*/
.globl uart_asm_init
uart_asm_init:
/* setup UART0-UART3 GPIOs (part1) */
mov r0, r7
ldr r1, =0x22222222
str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
ldr r1, =0x00222222
str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
ldr r0, =S5PC210_UART_BASE
add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
ldr r1, =0x3C5
str r1, [r0, #0x4]
ldr r1, =0x111
str r1, [r0, #0x8]
ldr r1, =0x3
str r1, [r0, #0x0]
ldr r1, =0x35
str r1, [r0, #0x28]
ldr r1, =0x4
str r1, [r0, #0x2c]
mov pc, lr
nop
nop
nop
/* Setting TZPC[TrustZone Protection Controller] */
tzpc_init:
ldr r0, =0x10110000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10120000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10130000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10140000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10150000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10160000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
mov pc, lr

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board/samsung/smdkv310/mem_setup.S Normal file
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/*
* Memory setup for SMDKV310 board based on S5PC210
*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#define SET_MIU
#define MEM_DLL
#ifdef CONFIG_CLK_800_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_200_200
#define DRAM_CLK_200
#endif
#ifdef CONFIG_CLK_1000_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_400_200
#define DRAM_CLK_400
#endif
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
/*
* Async bridge configuration at CPU_core:
* 1: half_sync
* 0: full_sync
*/
ldr r0, =0x10010350
mov r1, #1
str r1, [r0]
#ifdef SET_MIU
ldr r0, =S5PC210_MIU_BASE @0x10600000
#ifdef CONFIG_MIU_1BIT_INTERLEAVED
ldr r1, =0x0000000c
str r1, [r0, #0x400] @MIU_INTLV_CONFIG
ldr r1, =0x40000000
str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
ldr r1, =0xbfffffff
str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
ldr r1, =0x00000001
str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
#endif
#ifdef CONFIG_MIU_2BIT_INTERLEAVED
ldr r1, =0x2000150c
str r1, [r0, #0x400] @MIU_INTLV_CONFIG
ldr r1, =0x40000000
str r1, [r0, #0x808] @MIU_INTLV_START_ADDR
ldr r1, =0xbfffffff
str r1, [r0, #0x810] @MIU_INTLV_END_ADDR
ldr r1, =0x00000001
str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
#endif
#ifdef CONFIG_MIU_LINEAR
ldr r1, =0x40000000
str r1, [r0, #0x818] @MIU_SINGLE_MAPPING0_START_ADDR
ldr r1, =0x7fffffff
str r1, [r0, #0x820] @MIU_SINGLE_MAPPING0_END_ADDR
ldr r1, =0x80000000
str r1, [r0, #0x828] @MIU_SINGLE_MAPPING1_START_ADDR
ldr r1, =0xbfffffff
str r1, [r0, #0x830] @MIU_SINGLE_MAPPING1_END_ADDR]
ldr r1, =0x00000006
str r1, [r0, #0x800] @MIU_MAPPING_UPDATE
#endif
#endif
/* DREX0 */
ldr r0, =S5PC210_DMC0_BASE @0x10400000
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xE3855703
str r1, [r0, #0x44] @DMC_PHYZQCONTROL
mov r2, #0x100000
1: subs r2, r2, #1
bne 1b
ldr r1, =0xe000008e
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0x71101008
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0x7110100A
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0x7110100B
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0x00000000
str r1, [r0, #0x20] @DMC_PHYCONTROL2
ldr r1, =0x0FFF301a
str r1, [r0, #0x00] @DMC_CONCONTROL
ldr r1, =0x00312640
str r1, [r0, #0x04] @DMC_MEMCONTROL]
#ifdef CONFIG_MIU_LINEAR
ldr r1, =0x40e01323
str r1, [r0, #0x08] @DMC_MEMCONFIG0
ldr r1, =0x60e01323
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
ldr r1, =0x20e01323
str r1, [r0, #0x08] @DMC_MEMCONFIG0
ldr r1, =0x40e01323
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
#endif
ldr r1, =0xff000000
str r1, [r0, #0x14] @DMC_PRECHCONFIG
ldr r1, =0x000000BC
str r1, [r0, #0x30] @DMC_TIMINGAREF
#ifdef DRAM_CLK_330
ldr r1, =0x3545548d
str r1, [r0, #0x34] @DMC_TIMINGROW
ldr r1, =0x45430506
str r1, [r0, #0x38] @DMC_TIMINGDATA
ldr r1, =0x4439033c
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
#endif
#ifdef DRAM_CLK_400
ldr r1, =0x4046654f
str r1, [r0, #0x34] @DMC_TIMINGROW
ldr r1, =0x56500506
str r1, [r0, #0x38] @DMC_TIMINGDATA
ldr r1, =0x5444033d
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
#endif
ldr r1, =0x07000000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
2: subs r2, r2, #1
bne 2b
ldr r1, =0x00020000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00030000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00010002
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00000328
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
3: subs r2, r2, #1
bne 3b
ldr r1, =0x0a000000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
4: subs r2, r2, #1
bne 4b
ldr r1, =0x07100000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
5: subs r2, r2, #1
bne 5b
ldr r1, =0x00120000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00130000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00110002
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00100328
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
6: subs r2, r2, #1
bne 6b
ldr r1, =0x0a100000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
7: subs r2, r2, #1
bne 7b
ldr r1, =0xe000008e
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
mov r2, #0x100000
8: subs r2, r2, #1
bne 8b
/* DREX1 */
ldr r0, =S5PC210_DMC1_BASE @0x10410000
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xE3855703
str r1, [r0, #0x44] @DMC_PHYZQCONTROL
mov r2, #0x100000
1: subs r2, r2, #1
bne 1b
ldr r1, =0xe000008e
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0x71101008
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0x7110100A
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0x7110100B
str r1, [r0, #0x18] @DMC_PHYCONTROL0
ldr r1, =0x00000000
str r1, [r0, #0x20] @DMC_PHYCONTROL2
ldr r1, =0x0FFF301a
str r1, [r0, #0x00] @DMC_CONCONTROL
ldr r1, =0x00312640
str r1, [r0, #0x04] @DMC_MEMCONTROL]
#ifdef CONFIG_MIU_LINEAR
ldr r1, =0x40e01323
str r1, [r0, #0x08] @DMC_MEMCONFIG0
ldr r1, =0x60e01323
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
#else /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
ldr r1, =0x20e01323
str r1, [r0, #0x08] @DMC_MEMCONFIG0
ldr r1, =0x40e01323
str r1, [r0, #0x0C] @DMC_MEMCONFIG1
#endif
ldr r1, =0xff000000
str r1, [r0, #0x14] @DMC_PRECHCONFIG
ldr r1, =0x000000BC
str r1, [r0, #0x30] @DMC_TIMINGAREF
#ifdef DRAM_CLK_330
ldr r1, =0x3545548d
str r1, [r0, #0x34] @DMC_TIMINGROW
ldr r1, =0x45430506
str r1, [r0, #0x38] @DMC_TIMINGDATA
ldr r1, =0x4439033c
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
#endif
#ifdef DRAM_CLK_400
ldr r1, =0x4046654f
str r1, [r0, #0x34] @DMC_TIMINGROW
ldr r1, =0x56500506
str r1, [r0, #0x38] @DMC_TIMINGDATA
ldr r1, =0x5444033d
str r1, [r0, #0x3C] @DMC_TIMINGPOWER
#endif
ldr r1, =0x07000000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
2: subs r2, r2, #1
bne 2b
ldr r1, =0x00020000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00030000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00010002
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00000328
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
3: subs r2, r2, #1
bne 3b
ldr r1, =0x0a000000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
4: subs r2, r2, #1
bne 4b
ldr r1, =0x07100000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
5: subs r2, r2, #1
bne 5b
ldr r1, =0x00120000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00130000
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00110002
str r1, [r0, #0x10] @DMC_DIRECTCMD
ldr r1, =0x00100328
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
6: subs r2, r2, #1
bne 6b
ldr r1, =0x0a100000
str r1, [r0, #0x10] @DMC_DIRECTCMD
mov r2, #0x100000
7: subs r2, r2, #1
bne 7b
ldr r1, =0xe000008e
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
mov r2, #0x100000
8: subs r2, r2, #1
bne 8b
/* turn on DREX0, DREX1 */
ldr r0, =0x10400000 @APB_DMC_0_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #0x00] @DMC_CONCONTROL
ldr r0, =0x10410000 @APB_DMC_1_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #0x00] @DMC_CONCONTROL
mov pc, lr

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board/samsung/smdkv310/smdkv310.c Normal file
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/*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
struct s5pc210_gpio_part1 *gpio1;
struct s5pc210_gpio_part2 *gpio2;
static void smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
/* gpio configuration GPK0CON */
gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
| SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
| SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F)
| SROMC_BC_PMC(0x0F);
/* Select and configure the SROMC bank */
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
}
int board_init(void)
{
gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
smc9115_pre_init();
gd->bd->bi_arch_number = MACH_TYPE_SMDKV310;
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
printf("\nBoard: SMDKV310\n");
return 0;
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
int i, err;
/*
* MMC2 SD card GPIO:
*
* GPK2[0] SD_2_CLK(2)
* GPK2[1] SD_2_CMD(2)
* GPK2[2] SD_2_CDn
* GPK2[3:6] SD_2_DATA[0:3](2)
*/
for (i = 0; i < 7; i++) {
/* GPK2[0:6] special function 2 */
gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
/* GPK2[0:6] drv 4x */
gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
/* GPK2[0:1] pull disable */
if (i == 0 || i == 1) {
gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
continue;
}
/* GPK2[2:6] pull up */
gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
}
err = s5p_mmc_init(2, 4);
return err;
}
#endif

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#
# Copyright (C) ST-Ericsson SA 2009
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
CFLAGS += -D__RELEASE -D__STN_8500
LIB = $(obj)lib$(BOARD).o
COBJS := u8500_href.o gpio.o prcmu.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/gpio.h>
static struct gpio_register *addr_gpio_register[] = {
(void *)U8500_GPIO_0_BASE,
(void *)U8500_GPIO_1_BASE,
(void *)U8500_GPIO_2_BASE,
(void *)U8500_GPIO_3_BASE,
(void *)U8500_GPIO_4_BASE,
(void *)U8500_GPIO_5_BASE,
(void *)U8500_GPIO_6_BASE,
(void *)U8500_GPIO_7_BASE,
(void *)U8500_GPIO_8_BASE,
};
struct gpio_altfun_data altfun_table[] = {
{
.altfun = GPIO_ALT_I2C_0,
.start = 147,
.end = 148,
.cont = 0,
.type = GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_I2C_1,
.start = 16,
.end = 17,
.cont = 0,
.type = GPIO_ALTF_B,
},
{
.altfun = GPIO_ALT_I2C_2,
.start = 10,
.end = 11,
.cont = 0,
.type = GPIO_ALTF_B,
},
{
.altfun = GPIO_ALT_I2C_3,
.start = 229,
.end = 230,
.cont = 0,
.type = GPIO_ALTF_C,
},
{
.altfun = GPIO_ALT_UART_0_MODEM,
.start = 0,
.end = 3,
.cont = 1,
.type = GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_UART_0_MODEM,
.start = 33,
.end = 36,
.cont = 0,
.type = GPIO_ALTF_C,
},
{
.altfun = GPIO_ALT_UART_1,
.start = 4,
.end = 7,
.cont = 0,
.type =
GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_UART_2,
.start = 18,
.end = 19,
.cont = 1,
.type = GPIO_ALTF_B,
},
{
.altfun = GPIO_ALT_UART_2,
.start = 29,
.end = 32,
.cont = 0,
.type = GPIO_ALTF_C,
},
{
.altfun = GPIO_ALT_MSP_0,
.start = 12,
.end = 17,
.cont = 1,
.type = GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_MSP_0,
.start = 21,
.end = 21,
.cont = 0,
.type = GPIO_ALTF_B,
},
{
.altfun = GPIO_ALT_MSP_1,
.start = 33,
.end = 36,
.cont = 0,
.type = GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_MSP_2,
.start = 192,
.end = 196,
.cont = 0,
.type = GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_LCD_PANEL,
.start = 64,
.end = 93,
.cont = 1,
.type = GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_LCD_PANEL,
.start = 150,
.end = 171,
.cont = 0,
.type = GPIO_ALTF_B,
},
{
.altfun = GPIO_ALT_SD_CARD0,
.start = 18,
.end = 28,
.cont = 0,
.type = GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_MM_CARD0,
.start = 18,
.end = 32,
.cont = 0,
.type = GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_USB_OTG,
.start = 256,
.end = 267,
.cont = 0,
.type = GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_EMMC,
.start = 197,
.end = 207,
.cont = 0,
.type = GPIO_ALTF_A,
},
{
.altfun = GPIO_ALT_POP_EMMC,
.start = 128,
.end = 138,
.cont = 0,
.type = GPIO_ALTF_A,
},
};
/*
* Static Function declarations
*/
enum gpio_error gpio_setpinconfig(int pin_id, struct gpio_config *config)
{
struct gpio_register *p_gpio_register =
addr_gpio_register[GPIO_BLOCK(pin_id)];
u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
enum gpio_error error = GPIO_OK;
u32 temp_reg;
switch (config->mode) {
case GPIO_ALTF_A:
temp_reg = readl(&p_gpio_register->gpio_afsa);
temp_reg |= mask;
writel(temp_reg, &p_gpio_register->gpio_afsa);
temp_reg = readl(&p_gpio_register->gpio_afsb);
temp_reg &= ~mask;
writel(temp_reg, &p_gpio_register->gpio_afsb);
break;
case GPIO_ALTF_B:
temp_reg = readl(&p_gpio_register->gpio_afsa);
temp_reg &= ~mask;
writel(temp_reg, &p_gpio_register->gpio_afsa);
temp_reg = readl(&p_gpio_register->gpio_afsb);
temp_reg |= mask;
writel(temp_reg, &p_gpio_register->gpio_afsb);
break;
case GPIO_ALTF_C:
temp_reg = readl(&p_gpio_register->gpio_afsa);
temp_reg |= mask;
writel(temp_reg, &p_gpio_register->gpio_afsa);
temp_reg = readl(&p_gpio_register->gpio_afsb);
temp_reg |= mask;
writel(temp_reg, &p_gpio_register->gpio_afsb);
break;
case GPIO_MODE_SOFTWARE:
temp_reg = readl(&p_gpio_register->gpio_afsa);
temp_reg &= ~mask;
writel(temp_reg, &p_gpio_register->gpio_afsa);
temp_reg = readl(&p_gpio_register->gpio_afsb);
temp_reg &= ~mask;
writel(temp_reg, &p_gpio_register->gpio_afsb);
switch (config->direction) {
case GPIO_DIR_INPUT:
writel(mask, &p_gpio_register->gpio_dirc);
break;
case GPIO_DIR_OUTPUT:
writel(mask, &p_gpio_register->gpio_dirs);
break;
case GPIO_DIR_LEAVE_UNCHANGED:
break;
default:
return GPIO_INVALID_PARAMETER;
}
break;
case GPIO_MODE_LEAVE_UNCHANGED:
break;
default:
return GPIO_INVALID_PARAMETER;
}
return error;
}
enum gpio_error gpio_resetgpiopin(int pin_id, char *dev_name)
{
struct gpio_register *p_gpio_register =
addr_gpio_register[GPIO_BLOCK(pin_id)];
u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
enum gpio_error error = GPIO_OK;
u32 temp_reg;
temp_reg = readl(&p_gpio_register->gpio_afsa);
temp_reg &= ~mask;
writel(temp_reg, &p_gpio_register->gpio_afsa);
temp_reg = readl(&p_gpio_register->gpio_afsb);
temp_reg &= ~mask;
writel(temp_reg, &p_gpio_register->gpio_afsb);
writel(mask, &p_gpio_register->gpio_dirc);
return error;
}
struct gpio_config altfun_pinconfig;
enum gpio_error gpio_altfunction(enum gpio_alt_function alt_func,
int which_altfunc, char *dev_name)
{
int i, j, start, end;
enum gpio_error error = -1;
for (i = 0; i < ARRAY_SIZE(altfun_table); i++) {
if (altfun_table[i].altfun != alt_func)
continue;
start = altfun_table[i].start;
end = altfun_table[i].end;
for (j = start; j <= end; j++) {
if (which_altfunc == GPIO_ALTF_FIND)
altfun_pinconfig.mode = altfun_table[i].type;
else
altfun_pinconfig.mode = which_altfunc;
altfun_pinconfig.direction = GPIO_DIR_OUTPUT;
altfun_pinconfig.dev_name = dev_name;
if (which_altfunc != GPIO_ALTF_DISABLE)
error = gpio_setpinconfig(j, &altfun_pinconfig);
else
error = gpio_resetgpiopin(j, dev_name);
if (!error)
continue;
printf("GPIO %d configuration failure (nmdk_error:%d)",
j, error);
error = GPIO_INVALID_PARAMETER;
return error;
}
if (!altfun_table[i].cont)
break;
}
return error;
}
int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name)
{
struct gpio_register *p_gpio_register =
addr_gpio_register[GPIO_BLOCK(pin_id)];
u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
switch (value) {
case GPIO_DATA_HIGH:
writel(mask, &p_gpio_register->gpio_dats);
break;
case GPIO_DATA_LOW:
writel(mask, &p_gpio_register->gpio_datc);
break;
default:
printf("Invalid value passed in %s", __FUNCTION__);
return GPIO_INVALID_PARAMETER;
}
return GPIO_OK;
}
int gpio_readpin(int pin_id, enum gpio_data *rv)
{
struct gpio_register *p_gpio_register =
addr_gpio_register[GPIO_BLOCK(pin_id)];
u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
if ((readl(&p_gpio_register->gpio_dat) & mask) != 0)
*rv = GPIO_DATA_HIGH;
else
*rv = GPIO_DATA_LOW;
return GPIO_OK;
}
int gpio_altfuncenable(enum gpio_alt_function altfunc, char *dev_name)
{
return (int)gpio_altfunction(altfunc, GPIO_ALTF_FIND, dev_name);
}
int gpio_altfuncdisable(enum gpio_alt_function altfunc, char *dev_name)
{
return (int)gpio_altfunction(altfunc, GPIO_ALTF_DISABLE, dev_name);
}

55
board/st-ericsson/u8500/prcmu-fw.h Normal file
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/*
* Copyright (C) 2009 ST-Ericsson SA
*
* Copied from the Linux version:
* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_PRCMU_FW_V1_H
#define __MACH_PRCMU_FW_V1_H
#define AP_EXECUTE 2
#define I2CREAD 1
#define I2C_WR_OK 1
#define I2C_RD_OK 2
#define I2CWRITE 0
#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE
#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */
#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */
#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */
/* Mailbox 5 Requests */
#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0)
#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1)
#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2)
#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3)
/* Mailbox 5 ACKs */
#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1)
#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2)
#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3)
#define LOW_POWER_WAKEUP 1
#define EXE_WAKEUP 0
#define REQ_MB5 5
extern int prcmu_i2c_read(u8 reg, u16 slave);
extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
#endif /* __MACH_PRCMU_FW_V1_H */

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/*
* Copyright (C) 2009 ST-Ericsson SA
*
* Adapted from the Linux version:
* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*/
/*
* NOTE: This currently does not support the I2C workaround access method.
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include "prcmu-fw.h"
/* CPU mailbox registers */
#define PRCM_MBOX_CPU_VAL (U8500_PRCMU_BASE + 0x0fc)
#define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100)
#define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104)
static int prcmu_is_ready(void)
{
int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
if (!ready)
printf("PRCMU firmware not ready\n");
return ready;
}
static int _wait_for_req_complete(int num)
{
int timeout = 1000;
/* checking any already on-going transaction */
while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--)
;
timeout = 1000;
/* Set an interrupt to XP70 */
writel(1 << num, PRCM_MBOX_CPU_SET);
while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--)
;
if (!timeout) {
printf("PRCMU operation timed out\n");
return -1;
}
return 0;
}
/**
* prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C
* @reg: - db8500 register bank to be accessed
* @slave: - db8500 register to be accessed
* Returns: ACK_MB5 value containing the status
*/
int prcmu_i2c_read(u8 reg, u16 slave)
{
uint8_t i2c_status;
uint8_t i2c_val;
if (!prcmu_is_ready())
return -1;
debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n",
reg, slave);
/* prepare the data for mailbox 5 */
writeb((reg << 1) | I2CREAD, PRCM_REQ_MB5_I2COPTYPE_REG);
writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
writeb(0, PRCM_REQ_MB5_I2CVAL);
_wait_for_req_complete(REQ_MB5);
/* retrieve values */
debug("ack-mb5:transfer status = %x\n",
readb(PRCM_ACK_MB5_STATUS));
debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
debug("ack-mb5:slave_add = %x\n",
readb(PRCM_ACK_MB5_SLAVE));
debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
i2c_status = readb(PRCM_ACK_MB5_STATUS);
i2c_val = readb(PRCM_ACK_MB5_VAL);
if (i2c_status == I2C_RD_OK)
return i2c_val;
else {
printf("prcmu_i2c_read:read return status= %d\n",
i2c_status);
return -1;
}
}
/**
* prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C
* @reg: - db8500 register bank to be accessed
* @slave: - db800 register to be written to
* @reg_data: - the data to write
* Returns: ACK_MB5 value containing the status
*/
int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
{
uint8_t i2c_status;
if (!prcmu_is_ready())
return -1;
debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n",
reg, slave);
/* prepare the data for mailbox 5 */
writeb((reg << 1) | I2CWRITE, PRCM_REQ_MB5_I2COPTYPE_REG);
writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
writeb(reg_data, PRCM_REQ_MB5_I2CVAL);
debug("\ncpu_is_u8500v11\n");
_wait_for_req_complete(REQ_MB5);
/* retrieve values */
debug("ack-mb5:transfer status = %x\n",
readb(PRCM_ACK_MB5_STATUS));
debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
debug("ack-mb5:slave_add = %x\n",
readb(PRCM_ACK_MB5_SLAVE));
debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
i2c_status = readb(PRCM_ACK_MB5_STATUS);
debug("\ni2c_status = %x\n", i2c_status);
if (i2c_status == I2C_WR_OK)
return 0;
else {
printf("ape-i2c: i2c_status : 0x%x\n", i2c_status);
return -1;
}
}

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board/st-ericsson/u8500/u8500_href.c Normal file
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/*
* Copyright (C) ST-Ericsson SA 2009
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
#include <common.h>
#include <i2c.h>
#include <asm/types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_MMC
#include "../../../drivers/mmc/arm_pl180_mmci.h"
#endif
#define NOMADIK_PER4_BASE (0x80150000)
#define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000)
#define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000)
/* Power, Reset, Clock Management Unit */
/*
* SVA: Smart Video Accelerator
* SIA: Smart Imaging Accelerator
* SGA: Smart Graphic accelerator
* B2R2: Graphic blitter
*/
#define PRCMU_BASE CFG_PRCMU_BASE /* 0x80157000 for U8500 */
#define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000)
#define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004)
#define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008)
#define PRCM_SIAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x00C)
#define PRCM_SAAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x010)
#define PRCM_SGACLK_MGT_REG (PRCMU_BASE + 0x014)
#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
#define PRCM_SLIMCLK_MGT_REG (PRCMU_BASE + 0x028)
#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
#define PRCM_DMACLK_MGT_REG (PRCMU_BASE + 0x074)
#define PRCM_B2R2CLK_MGT_REG (PRCMU_BASE + 0x078)
#define PRCM_PLLSOC0_FREQ_REG (PRCMU_BASE + 0x080)
#define PRCM_PLLSOC1_FREQ_REG (PRCMU_BASE + 0x084)
#define PRCM_PLLARM_FREQ_REG (PRCMU_BASE + 0x088)
#define PRCM_PLLDDR_FREQ_REG (PRCMU_BASE + 0x08C)
#define PRCM_ARM_CHGCLKREQ_REG (PRCMU_BASE + 0x114)
#define PRCM_TCR (PRCMU_BASE + 0x1C8)
/*
* Memory controller register
*/
#define DMC_BASE_ADDR 0x80156000
#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
int board_id; /* set in board_late_init() */
/* PLLs for clock management registers */
enum {
GATED = 0,
PLLSOC0, /* pllsw = 001, ffs() = 1 */
PLLSOC1, /* pllsw = 010, ffs() = 2 */
PLLDDR, /* pllsw = 100, ffs() = 3 */
PLLARM,
};
static struct pll_freq_regs {
int idx; /* index fror pll_name and pll_khz arrays */
uint32_t addr;
} pll_freq_regs[] = {
{PLLSOC0, PRCM_PLLSOC0_FREQ_REG},
{PLLSOC1, PRCM_PLLSOC1_FREQ_REG},
{PLLDDR, PRCM_PLLDDR_FREQ_REG},
{PLLARM, PRCM_PLLARM_FREQ_REG},
{0, 0},
};
static const char *pll_name[5] = {"GATED", "SOC0", "SOC1", "DDR", "ARM"};
static uint32_t pll_khz[5]; /* use ffs(pllsw(reg)) as index for 0..3 */
static struct clk_mgt_regs {
uint32_t addr;
uint32_t val;
const char *descr;
} clk_mgt_regs[] = {
/* register content taken from bootrom settings */
{PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */
{PRCM_ACLK_MGT_REG, 0x0125, "ACLK"}, /* ena, SOC0/5, 160 MHz */
{PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */
{PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */
{PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */
{PRCM_SGACLK_MGT_REG, 0x0024, "SGA"}, /* dis, SOC0/4, 200 MHz */
{PRCM_UARTCLK_MGT_REG, 0x0300, "UART"}, /* ena, GATED, CLK38 */
{PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"}, /* dis, GATED, CLK38 */
{PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"}, /* ena, SOC0/16, 50 MHz */
{PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */
{PRCM_PER1CLK_MGT_REG, 0x126, "PER1"}, /* ena, SOC0/6, 133 MHz */
{PRCM_PER2CLK_MGT_REG, 0x126, "PER2"}, /* ena, SOC0/6, 133 MHz */
{PRCM_PER3CLK_MGT_REG, 0x126, "PER3"}, /* ena, SOC0/6, 133 MHz */
{PRCM_PER5CLK_MGT_REG, 0x126, "PER5"}, /* ena, SOC0/6, 133 MHz */
{PRCM_PER6CLK_MGT_REG, 0x126, "PER6"}, /* ena, SOC0/6, 133 MHz */
{PRCM_PER7CLK_MGT_REG, 0x128, "PER7"}, /* ena, SOC0/8, 100 MHz */
{PRCM_DMACLK_MGT_REG, 0x125, "DMA"}, /* ena, SOC0/5, 160 MHz */
{PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"}, /* dis, SOC0/5, 160 MHz */
{0, 0, NULL},
};
static void init_regs(void);
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
printf("Boot reached stage %d\n", progress);
}
#endif
static unsigned int read_asicid(void)
{
unsigned int *address = (void *)U8500_BOOTROM_BASE
+ U8500_BOOTROM_ASIC_ID_OFFSET;
return readl(address);
}
int cpu_is_u8500v11(void)
{
return read_asicid() == 0x008500A1;
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_early_init_f(void)
{
init_regs();
return 0;
}
int board_init(void)
{
uint32_t unused_cols_rows;
unsigned int nrows;
unsigned int ncols;
gd->bd->bi_arch_number = 0x1A4;
gd->bd->bi_boot_params = 0x00000100;
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
/*
* Assumption: 2 CS active, both CS have same layout.
* 15 rows max, 11 cols max (controller spec).
* memory chip has 8 banks, I/O width 32 bit.
* The correct way would be to read MR#8: I/O width and density,
* but this requires locking against the PRCMU firmware.
* Simplified approach:
* Read number of unused rows and columns from mem controller.
* size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes
*/
unused_cols_rows = readl(DMC_CTL_97);
nrows = 15 - (unused_cols_rows & 0x07);
ncols = 11 - ((unused_cols_rows & 0x0700) >> 8);
gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4;
icache_enable();
return 0;
}
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE_1;
return 0;
}
unsigned int addr_vall_arr[] = {
0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO: Enable reqd only */
0x8011F008, 0x00001CFF, /* Clocks for HSI TODO: Enable reqd only */
0x8000F000, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
0x8000F008, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
0x80157020, 0x00000150, /* I2C 48MHz clock */
0x8012F000, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
0x8012F008, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
0xA03DF000, 0x0000000D, /* Clock for MTU Timers */
0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */
0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */
0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */
0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */
0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */
0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */
0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */
0x801571E4, 0x0000000C, /* PRCMU settings for B2R2,
PRCM_APE_RESETN_SET_REG */
0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */
0xA03FF000, 0x00000003, /* USB */
0xA03FF008, 0x00000001, /* USB */
0xA03FE00C, 0x00000000, /* USB */
0xA03FE020, 0x00000FFF, /* USB */
0xA03FE024, 0x00000000 /* USB */
};
#ifdef BOARD_LATE_INIT
#ifdef CONFIG_MMC
#define LDO_VAUX3_MASK 0x3
#define LDO_VAUX3_ENABLE 0x1
#define VAUX3_VOLTAGE_2_9V 0xd
#define AB8500_REGU_CTRL2 0x4
#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A
#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421
static int hrefplus_mmc_power_init(void)
{
int ret;
int val;
if (!cpu_is_u8500v11())
return 0;
/*
* On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
* card to work. This is done by enabling the regulators in the AB8500
* via PRCMU I2C transactions.
*
* This code is derived from the handling of AB8500_LDO_VAUX3 in
* ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
*
* Turn off and delay is required to have it work across soft reboots.
*/
ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG);
if (ret < 0)
goto out;
val = ret;
/* Turn off */
ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG,
val & ~LDO_VAUX3_MASK);
if (ret < 0)
goto out;
udelay(10 * 1000);
/* Set the voltage to 2.9V */
ret = prcmu_i2c_write(AB8500_REGU_CTRL2,
AB8500_REGU_VRF1VAUX3_SEL_REG,
VAUX3_VOLTAGE_2_9V);
if (ret < 0)
goto out;
val = val & ~LDO_VAUX3_MASK;
val = val | LDO_VAUX3_ENABLE;
/* Turn on the supply */
ret = prcmu_i2c_write(AB8500_REGU_CTRL2,
AB8500_REGU_VRF1VAUX3_REGU_REG, val);
out:
return ret;
}
#endif
/*
* called after all initialisation were done, but before the generic
* mmc_initialize().
*/
int board_late_init(void)
{
uchar byte;
/*
* Determine and set board_id environment variable
* 0: mop500, 1: href500
* Above boards have different GPIO expander chips which we can
* distinguish by the chip id.
*
* The board_id environment variable is needed for the Linux bootargs.
*/
(void) i2c_set_bus_num(0);
(void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1);
if (byte == 0x01) {
board_id = 0;
setenv("board_id", "0");
} else {
board_id = 1;
setenv("board_id", "1");
}
#ifdef CONFIG_MMC
hrefplus_mmc_power_init();
/*
* config extended GPIO pins for level shifter and
* SDMMC_ENABLE
*/
if (board_id == 0) {
/* MOP500 */
byte = 0x0c;
(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x89, 1, &byte, 1);
(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x83, 1, &byte, 1);
} else {
/* HREF */
/* set the direction of GPIO KPY9 and KPY10 */
byte = 0x06;
(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC8, 1, &byte, 1);
/* must be a multibyte access */
(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC4, 1,
(uchar []) {0x06, 0x06}, 2);
}
#endif /* CONFIG_MMC */
/*
* Create a memargs variable which points uses either the memargs256 or
* memargs512 environment variable, depending on the memory size.
* memargs is used to build the bootargs, memargs256 and memargs512 are
* stored in the environment.
*/
if (gd->bd->bi_dram[0].size == 0x10000000) {
setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}");
setenv("mem", "256M");
} else {
setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}");
setenv("mem", "512M");
}
return 0;
}
#endif /* BOARD_LATE_INIT */
static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits)
{
writel(readl(&gpio_reg->gpio_dats) | bits, &gpio_reg->gpio_dats);
writel(readl(&gpio_reg->gpio_pdis) & ~bits, &gpio_reg->gpio_pdis);
}
static void init_regs(void)
{
/* FIXME Remove magic register array settings for ED also */
struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE;
/* Enable timers */
writel(1 << 17, &prcmu->tcr);
u8500_prcmu_enable(&prcmu->per1clk_mgt);
u8500_prcmu_enable(&prcmu->per2clk_mgt);
u8500_prcmu_enable(&prcmu->per3clk_mgt);
u8500_prcmu_enable(&prcmu->per5clk_mgt);
u8500_prcmu_enable(&prcmu->per6clk_mgt);
u8500_prcmu_enable(&prcmu->per7clk_mgt);
u8500_prcmu_enable(&prcmu->uartclk_mgt);
u8500_prcmu_enable(&prcmu->i2cclk_mgt);
u8500_prcmu_enable(&prcmu->sdmmcclk_mgt);
u8500_clock_enable(1, 9, -1); /* GPIO0 */
u8500_clock_enable(2, 11, -1); /* GPIO1 */
u8500_clock_enable(3, 8, -1); /* GPIO2 */
u8500_clock_enable(5, 1, -1); /* GPIO3 */
u8500_clock_enable(3, 6, 6); /* UART2 */
gpio_altfuncenable(GPIO_ALT_I2C_0, "I2C0");
u8500_clock_enable(3, 3, 3); /* I2C0 */
early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x60000000);
gpio_altfuncenable(GPIO_ALT_UART_2, "UART2");
early_gpio_setup((struct gpio_register *)U8500_GPIO_6_BASE, 0x0000ffe0);
gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC");
early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x0000ffe0);
gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD");
u8500_clock_enable(1, 5, 5); /* SDI0 */
u8500_clock_enable(2, 4, 2); /* SDI4 */
u8500_clock_enable(6, 7, -1); /* MTU0 */
u8500_clock_enable(3, 4, 4); /* SDI2 */
early_gpio_setup((struct gpio_register *)U8500_GPIO_4_BASE, 0x000007ff);
gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC");
/*
* Enabling clocks for all devices which are AMBA devices in the
* kernel. Otherwise they will not get probe()'d because the
* peripheral ID register will not be powered.
*/
/* XXX: some of these differ between ED/V1 */
u8500_clock_enable(1, 1, 1); /* UART1 */
u8500_clock_enable(1, 0, 0); /* UART0 */
u8500_clock_enable(3, 2, 2); /* SSP1 */
u8500_clock_enable(3, 1, 1); /* SSP0 */
u8500_clock_enable(2, 8, -1); /* SPI0 */
u8500_clock_enable(2, 5, 3); /* MSP2 */
}
#ifdef CONFIG_MMC
static int u8500_mmci_board_init(void)
{
enum gpio_error error;
struct gpio_register *gpio_base_address;
gpio_base_address = (void *)(U8500_GPIO_0_BASE);
gpio_base_address->gpio_dats |= 0xFFC0000;
gpio_base_address->gpio_pdis &= ~0xFFC0000;
/* save the GPIO0 AFSELA register */
error = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC");
if (error != GPIO_OK) {
printf("u8500_mmci_board_init() gpio_altfuncenable failed\n");
return -ENODEV;
}
return 0;
}
int board_mmc_init(bd_t *bd)
{
if (u8500_mmci_board_init())
return -ENODEV;
if (arm_pl180_mmci_init())
return -ENODEV;
return 0;
}
#endif
/*
* get_pll_freq_khz - return PLL frequency in kHz
*/
static uint32_t get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg)
{
uint32_t idf, ldf, odf, seldiv, phi;
/*
* PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0
* PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1
* where:
* IDF=R(2:0) (when R=000, IDF=1d)
* LDF = 2*D(7:0) (D must be greater than or equal to 6)
* ODF = N(5:0) (when N=000000, 0DF=1d)
*/
idf = (freq_reg & 0x70000) >> 16;
ldf = (freq_reg & 0xff) * 2;
odf = (freq_reg & 0x3f00) >> 8;
seldiv = (freq_reg & 0x01000000) >> 24;
phi = (inclk_khz * ldf) / (2 * odf * idf);
if (seldiv)
phi = phi/2;
return phi;
}
int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
uint32_t inclk_khz;
uint32_t reg, phi;
uint32_t clk_khz;
unsigned int clk_sel;
struct clk_mgt_regs *clks = clk_mgt_regs;
struct pll_freq_regs *plls = pll_freq_regs;
/*
* Go through list of PLLs.
* Initialise pll out frequency array (pll_khz) and print frequency.
*/
inclk_khz = 38400; /* 38.4 MHz */
while (plls->addr) {
reg = readl(plls->addr);
phi = get_pll_freq_khz(inclk_khz, reg);
pll_khz[plls->idx] = phi;
printf("%s PLL out frequency: %d.%d Mhz\n",
pll_name[plls->idx], phi/1000, phi % 1000);
plls++;
}
/* check ARM clock source */
reg = readl(PRCM_ARM_CHGCLKREQ_REG);
printf("A9 running on %s\n",
(reg & 1) ? "external clock" : "ARM PLL");
/* go through list of clk_mgt_reg */
printf("\n%19s %9s %7s %9s enabled\n",
"name(addr)", "value", "PLL", "CLK[MHz]");
while (clks->addr) {
reg = readl(clks->addr);
/* convert bit position into array index */
clk_sel = ffs((reg >> 5) & 0x7); /* PLLSW[2:0] */
if (reg & 0x200)
clk_khz = 38400; /* CLK38 is set */
else if ((reg & 0x1f) == 0)
/* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */
clk_khz = 0;
else
clk_khz = pll_khz[clk_sel] / (reg & 0x1f);
printf("%9s(%08x): %08x, %6s, %4d.%03d, %s\n",
clks->descr, clks->addr, reg, pll_name[clk_sel],
clk_khz / 1000, clk_khz % 1000,
(reg & 0x100) ? "ena" : "dis");
clks++;
}
return 0;
}
U_BOOT_CMD(
clkinfo, 1, 1, do_clkinfo,
"print clock info",
""
);

2
board/ti/beagle/beagle.c
View file

@ -171,7 +171,7 @@ int misc_init_r(void)
{
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
struct control_prog_io *prog_io_base = (struct gpio *)OMAP34XX_CTRL_BASE;
struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
/* Enable i2c2 pullup resisters */
writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);

47
board/ttcontrol/vision2/vision2.c
View file

@ -45,9 +45,6 @@ static u32 system_rev;
extern int mx51_fb_init(struct fb_videomode *mode);
#ifdef CONFIG_HW_WATCHDOG
#include <watchdog.h>
static struct fb_videomode nec_nl6448bc26_09c = {
"NEC_NL6448BC26-09C",
60, /* Refresh */
@ -65,6 +62,8 @@ static struct fb_videomode nec_nl6448bc26_09c = {
0, /* flag */
};
#ifdef CONFIG_HW_WATCHDOG
#include <watchdog.h>
void hw_watchdog_reset(void)
{
int val;
@ -700,47 +699,7 @@ int board_late_init(void)
int checkboard(void)
{
u32 system_rev = get_cpu_rev();
u32 cause;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
puts("Board: TTControl Vision II CPU V");
switch (system_rev & 0xff) {
case CHIP_REV_3_0:
puts("3.0 [");
break;
case CHIP_REV_2_5:
puts("2.5 [");
break;
case CHIP_REV_2_0:
puts("2.0 [");
break;
case CHIP_REV_1_1:
puts("1.1 [");
break;
case CHIP_REV_1_0:
default:
puts("1.0 [");
break;
}
cause = src_regs->srsr;
switch (cause) {
case 0x0001:
puts("POR");
break;
case 0x0009:
puts("RST");
break;
case 0x0010:
case 0x0011:
puts("WDOG");
break;
default:
printf("unknown 0x%x", cause);
}
puts("]\n");
puts("Board: TTControl Vision II CPU V\n");
return 0;
}

10
boards.cfg
View file

@ -108,7 +108,7 @@ davinci_sffsdr arm arm926ejs sffsdr davinci
davinci_sonata arm arm926ejs sonata davinci davinci
suen3 arm arm926ejs km_arm keymile kirkwood
suen8 arm arm926ejs km_arm keymile kirkwood
mgcoge2un arm arm926ejs km_arm keymile kirkwood
mgcoge3un arm arm926ejs km_arm keymile kirkwood
guruplug arm arm926ejs - Marvell kirkwood
mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE
@ -126,10 +126,12 @@ omap5912osk arm arm926ejs - ti
edminiv2 arm arm926ejs - LaCie orion5x
dkb arm arm926ejs - Marvell pantheon
ca9x4_ct_vxp arm armv7 vexpress armltd
efikamx arm armv7 efikamx - mx5
efikamx arm armv7 efikamx - mx5 mx51evk:IMX_CONFIG=board/efikamx/imximage.cfg
mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
vision2 arm armv7 vision2 ttcontrol mx5
mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg
mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
cm_t35 arm armv7 cm_t35 - omap3
omap3_overo arm armv7 overo - omap3
omap3_pandora arm armv7 pandora - omap3
@ -149,8 +151,10 @@ omap4_sdp4430 arm armv7 sdp4430 ti
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx
smdkv310 arm armv7 smdkv310 samsung s5pc2xx
harmony arm armv7 harmony nvidia tegra2
seaboard arm armv7 seaboard nvidia tegra2
u8500_href arm armv7 u8500 st-ericsson u8500
actux1 arm ixp
actux2 arm ixp
actux3 arm ixp

10
drivers/block/mvsata_ide.c
View file

@ -33,7 +33,9 @@
/* SATA port registers */
struct mvsata_port_registers {
u32 reserved1[192];
u32 reserved0[10];
u32 edma_cmd;
u32 reserved1[181];
/* offset 0x300 : ATA Interface registers */
u32 sstatus;
u32 serror;
@ -76,6 +78,7 @@ struct mvsata_port_registers {
* and for SStatus DETection.
*/
#define MVSATA_EDMA_CMD_ATA_RST 0x00000004
#define MVSATA_SCONTROL_DET_MASK 0x0000000F
#define MVSATA_SCONTROL_DET_NONE 0x00000000
#define MVSATA_SCONTROL_DET_INIT 0x00000001
@ -115,6 +118,11 @@ static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
u32 status;
u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
/* Hard reset */
writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd);
udelay(25); /* taken from original marvell port */
writel(0, &port->edma_cmd);
/* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
control = readl(&port->scontrol);
control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;

1
drivers/i2c/Makefile
View file

@ -41,6 +41,7 @@ COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)

613
drivers/i2c/u8500_i2c.c Normal file
View file

@ -0,0 +1,613 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Basic U-Boot I2C interface for STn8500/DB8500
* Author: Michael Brandt <Michael.Brandt@stericsson.com> for ST-Ericsson
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Only 7-bit I2C device addresses are supported.
*/
#include <common.h>
#include <i2c.h>
#include "u8500_i2c.h"
#include <asm/io.h>
#include <asm/arch/clock.h>
#define U8500_I2C_ENDAD_COUNTER (CONFIG_SYS_HZ/100) /* I2C bus timeout */
#define U8500_I2C_FIFO_FLUSH_COUNTER 500000 /* flush "timeout" */
#define U8500_I2C_SCL_FREQ 100000 /* I2C bus clock freq */
#define U8500_I2C_INPUT_FREQ 48000000 /* Input clock freq */
#define TX_FIFO_THRESHOLD 0x4
#define RX_FIFO_THRESHOLD 0x4
#define SLAVE_SETUP_TIME 14 /* Slave data setup time, 250ns for 48MHz i2c_clk */
#define WRITE_FIELD(var, mask, shift, value) \
(var = ((var & ~(mask)) | ((value) << (shift))))
static unsigned int bus_initialized[CONFIG_SYS_U8500_I2C_BUS_MAX];
static unsigned int i2c_bus_num;
static unsigned int i2c_bus_speed[] = {
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED,
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED
};
static struct u8500_i2c_regs *i2c_dev[] = {
(struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C0_BASE,
(struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C1_BASE,
(struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C2_BASE,
(struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C3_BASE,
};
static struct {
int periph;
int pcken;
int kcken;
} i2c_clock_bits[] = {
{3, 3, 3}, /* I2C0 */
{1, 2, 2}, /* I2C1 */
{1, 6, 6}, /* I2C2 */
{2, 0, 0}, /* I2C3 */
};
static void i2c_set_bit(void *reg, u32 mask)
{
writel(readl(reg) | mask, reg);
}
static void i2c_clr_bit(void *reg, u32 mask)
{
writel(readl(reg) & ~mask, reg);
}
static void i2c_write_field(void *reg, u32 mask, uint shift, u32 value)
{
writel((readl(reg) & ~mask) | (value << shift), reg);
}
static int __i2c_set_bus_speed(unsigned int speed)
{
u32 value;
struct u8500_i2c_regs *i2c_regs;
i2c_regs = i2c_dev[i2c_bus_num];
/* Select standard (100 kbps) speed mode */
i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_SM,
U8500_I2C_CR_SHIFT_SM, 0x0);
/*
* Set the Baud Rate Counter 2 value
* Baud rate (standard) = fi2cclk / ( (BRCNT2 x 2) + Foncycle )
* Foncycle = 0 (no digital filtering)
*/
value = (u32) (U8500_I2C_INPUT_FREQ / (speed * 2));
i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT2,
U8500_I2C_BRCR_SHIFT_BRCNT2, value);
/* ensure that BRCNT value is zero */
i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT1,
U8500_I2C_BRCR_SHIFT_BRCNT1, 0);
return U8500_I2C_INPUT_FREQ/(value * 2);
}
/*
* i2c_init - initialize the i2c bus
*
* speed: bus speed (in HZ)
* slaveaddr: address of device in slave mode
*
* Slave mode is not implemented.
*/
void i2c_init(int speed, int slaveaddr)
{
struct u8500_i2c_regs *i2c_regs;
debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed);
u8500_clock_enable(i2c_clock_bits[i2c_bus_num].periph,
i2c_clock_bits[i2c_bus_num].pcken,
i2c_clock_bits[i2c_bus_num].kcken);
i2c_regs = i2c_dev[i2c_bus_num];
/* Disable the controller */
i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
/* Clear registers */
writel(0, &i2c_regs->cr);
writel(0, &i2c_regs->scr);
writel(0, &i2c_regs->hsmcr);
writel(0, &i2c_regs->tftr);
writel(0, &i2c_regs->rftr);
writel(0, &i2c_regs->dmar);
i2c_bus_speed[i2c_bus_num] = __i2c_set_bus_speed(speed);
/*
* Set our own address.
* Set slave address mode to 7 bit addressing mode
*/
i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_SAM);
i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_ADDR,
U8500_I2C_SCR_SHIFT_ADDR, slaveaddr);
/* Slave Data Set up Time */
i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_DATA_SETUP_TIME,
U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME, SLAVE_SETUP_TIME);
/* Disable the DMA sync logic */
i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_DMA_SLE,
U8500_I2C_CR_SHIFT_DMA_SLE, 0);
/* Disable interrupts */
writel(0, &i2c_regs->imscr);
/* Configure bus master mode */
i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_OM, U8500_I2C_CR_SHIFT_OM,
U8500_I2C_BUS_MASTER_MODE);
/* Set FIFO threshold values */
writel(TX_FIFO_THRESHOLD, &i2c_regs->tftr);
writel(RX_FIFO_THRESHOLD, &i2c_regs->rftr);
/* Enable the I2C Controller */
i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
bus_initialized[i2c_bus_num] = 1;
}
/*
* loop_till_bit_clear - polls on a bit till it clears
* ioreg: register where you want to check status
* mask: bit mask for the bit you wish to check
* timeout: timeout in ticks/s
*/
static int loop_till_bit_clear(void *io_reg, u32 mask, unsigned long timeout)
{
unsigned long timebase = get_timer(0);
do {
if ((readl(io_reg) & mask) == 0x0UL)
return 0;
} while (get_timer(timebase) < timeout);
debug("loop_till_bit_clear timed out\n");
return -1;
}
/*
* loop_till_bit_set - polls on a bit till it is set.
* ioreg: register where you want to check status
* mask: bit mask for the bit you wish to check
* timeout: timeout in ticks/s
*/
static int loop_till_bit_set(void *io_reg, u32 mask, unsigned long timeout)
{
unsigned long timebase = get_timer(0);
do {
if ((readl(io_reg) & mask) != 0x0UL)
return 0;
} while (get_timer(timebase) < timeout);
debug("loop_till_bit_set timed out\n");
return -1;
}
/*
* flush_fifo - flush the I2C TX and RX FIFOs
*/
static void flush_fifo(struct u8500_i2c_regs *i2c_regs)
{
int counter = U8500_I2C_FIFO_FLUSH_COUNTER;
/* Flush Tx FIFO */
i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FTX);
/* Flush Rx FIFO */
i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FRX);
while (counter--) {
if (!(readl(&i2c_regs->cr) &
(U8500_I2C_CR_FTX | U8500_I2C_CR_FRX)))
break;
}
return;
}
#ifdef DEBUG
static void print_abort_reason(struct u8500_i2c_regs *i2c_regs)
{
int cause;
printf("abort: risr %08x, sr %08x\n", i2c_regs->risr, i2c_regs->sr);
cause = (readl(&i2c_regs->sr) & U8500_I2C_SR_CAUSE) >>
U8500_I2C_SR_SHIFT_CAUSE;
switch (cause) {
case U8500_I2C_NACK_ADDR:
printf("No Ack received after Slave Address xmission\n");
break;
case U8500_I2C_NACK_DATA:
printf("Valid for MASTER_WRITE: No Ack received "
"during data phase\n");
break;
case U8500_I2C_ACK_MCODE:
printf("Master recv ack after xmission of master code"
"in hs mode\n");
break;
case U8500_I2C_ARB_LOST:
printf("Master Lost arbitration\n");
break;
case U8500_I2C_BERR_START:
printf("Slave restarts\n");
break;
case U8500_I2C_BERR_STOP:
printf("Slave reset\n");
break;
case U8500_I2C_OVFL:
printf("Overflow\n");
break;
default:
printf("Unknown error type\n");
}
}
#endif
/*
* i2c_abort - called when a I2C transaction failed
*/
static void i2c_abort(struct u8500_i2c_regs *i2c_regs)
{
#ifdef DEBUG
print_abort_reason(i2c_regs);
#endif
/* flush RX and TX fifos */
flush_fifo(i2c_regs);
/* Acknowledge the Master Transaction Done */
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
/* Acknowledge the Master Transaction Done Without Stop */
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
i2c_init(i2c_bus_speed[i2c_bus_num], CONFIG_SYS_I2C_SLAVE);
}
/*
* write addr, alias index, to I2C bus.
*/
static int i2c_write_addr(struct u8500_i2c_regs *i2c_regs, uint addr, int alen)
{
while (alen--) {
/* Wait until the Tx Fifo is not full */
if (loop_till_bit_clear((void *)&i2c_regs->risr,
U8500_I2C_INT_TXFF,
U8500_I2C_ENDAD_COUNTER)) {
i2c_abort(i2c_regs);
return -1;
}
/* MSB first */
writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->tfr);
}
return 0;
}
/*
* Internal simplified read function:
* i2c_regs: Pointer to I2C registers for current bus
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one register)
* value: Where to put the data
*
* Returns: 0 on success, not 0 on failure
*/
static int i2c_read_byte(struct u8500_i2c_regs *i2c_regs, uchar chip,
uint addr, int alen, uchar *value)
{
u32 mcr = 0;
/* Set the address mode to 7 bit */
WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
/* Store the slave address in the master control register */
WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
if (alen != 0) {
/* Master write operation */
mcr &= ~(U8500_I2C_MCR_OP);
/* Configure the Frame length to one byte */
WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH,
U8500_I2C_MCR_SHIFT_LENGTH, 1);
/* Repeated start, no stop */
mcr &= ~(U8500_I2C_MCR_STOP);
/* Write Master Control Register */
writel(mcr, &i2c_regs->mcr);
/* send addr/index */
if (i2c_write_addr(i2c_regs, addr, alen) != 0)
return -1;
/* Check for the Master Transaction Done Without Stop */
if (loop_till_bit_set((void *)&i2c_regs->risr,
U8500_I2C_INT_MTDWS,
U8500_I2C_ENDAD_COUNTER)) {
return -1;
}
/* Acknowledge the Master Transaction Done Without Stop */
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
}
/* Master control configuration for read operation */
mcr |= U8500_I2C_MCR_OP;
/* Configure the STOP condition, we read only one byte */
mcr |= U8500_I2C_MCR_STOP;
/* Set the frame length to one byte, we support only 1 byte reads */
WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
i2c_write_field(&i2c_regs->mcr, U8500_I2C_MCR_LENGTH_STOP_OP,
U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP, mcr);
/*
* receive_data_polling
*/
/* Wait until the Rx FIFO is not empty */
if (loop_till_bit_clear((void *)&i2c_regs->risr,
U8500_I2C_INT_RXFE,
U8500_I2C_ENDAD_COUNTER))
return -1;
/* Read the data byte from Rx FIFO */
*value = readb(&i2c_regs->rfr);
/* Wait until the work is done */
if (loop_till_bit_set((void *)&i2c_regs->risr, U8500_I2C_INT_MTD,
U8500_I2C_ENDAD_COUNTER))
return -1;
/* Acknowledge the Master Transaction Done */
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
/* If MTD is set, Master Transaction Done Without Stop is set too */
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
return 0;
}
/*
* Internal simplified write function:
* i2c_regs: Pointer to I2C registers for current bus
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one register)
* data: Where to read the data
* len: How many bytes to write
*
* Returns: 0 on success, not 0 on failure
*/
static int __i2c_write(struct u8500_i2c_regs *i2c_regs, u8 chip, uint addr,
int alen, u8 *data, int len)
{
int i;
u32 mcr = 0;
/* Set the address mode to 7 bit */
WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
/* Store the slave address in the master control register */
WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
/* Write operation */
mcr &= ~(U8500_I2C_MCR_OP);
/* Current transaction is terminated by STOP condition */
mcr |= U8500_I2C_MCR_STOP;
/* Frame length: addr byte + len */
WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH,
(alen + len));
/* Write MCR register */
writel(mcr, &i2c_regs->mcr);
if (i2c_write_addr(i2c_regs, addr, alen) != 0)
return -1;
for (i = 0; i < len; i++) {
/* Wait until the Tx FIFO is not full */
if (loop_till_bit_clear((void *)&i2c_regs->risr,
U8500_I2C_INT_TXFF,
U8500_I2C_ENDAD_COUNTER))
return -1;
/* it is a 32 bit register with upper 24 reserved R/O */
writeb(data[i], &i2c_regs->tfr);
}
/* Check for Master Transaction Done */
if (loop_till_bit_set((void *)&i2c_regs->risr,
U8500_I2C_INT_MTD,
U8500_I2C_ENDAD_COUNTER)) {
printf("i2c_write_byte error2: risr %08x\n",
i2c_regs->risr);
return -1;
}
/* Acknowledge Master Transaction Done */
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
/* Acknowledge Master Transaction Done Without Stop */
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
return 0;
}
/*
* Probe the given I2C chip address. Returns 0 if a chip responded,
* not 0 on failure.
*/
int i2c_probe(uchar chip)
{
u32 mcr = 0;
struct u8500_i2c_regs *i2c_regs;
if (chip == CONFIG_SYS_I2C_SLAVE)
return 1;
i2c_regs = i2c_dev[i2c_bus_num];
/* Set the address mode to 7 bit */
WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
/* Store the slave address in the master control register */
WRITE_FIELD(mcr, U8500_I2C_MCR_A10, U8500_I2C_MCR_SHIFT_A7, chip);
/* Read operation */
mcr |= U8500_I2C_MCR_OP;
/* Set the frame length to one byte */
WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
/* Current transaction is terminated by STOP condition */
mcr |= U8500_I2C_MCR_STOP;
/* Write MCR register */
writel(mcr, &i2c_regs->mcr);
/* Wait until the Rx Fifo is not empty */
if (loop_till_bit_clear((void *)&i2c_regs->risr,
U8500_I2C_INT_RXFE,
U8500_I2C_ENDAD_COUNTER)) {
i2c_abort(i2c_regs);
return -1;
}
flush_fifo(i2c_regs);
/* Acknowledge the Master Transaction Done */
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
/* Acknowledge the Master Transaction Done Without Stop */
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
return 0;
}
/*
* Read/Write interface:
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one
* register)
* buffer: Where to read/write the data
* len: How many bytes to read/write
*
* Returns: 0 on success, not 0 on failure
*/
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int i;
int rc;
struct u8500_i2c_regs *i2c_regs;
if (alen > 2) {
debug("I2C read: addr len %d not supported\n", alen);
return 1;
}
i2c_regs = i2c_dev[i2c_bus_num];
for (i = 0; i < len; i++) {
rc = i2c_read_byte(i2c_regs, chip, addr + i, alen, &buffer[i]);
if (rc != 0) {
debug("I2C read: I/O error: %d\n", rc);
i2c_abort(i2c_regs);
return rc;
}
}
return 0;
}
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int rc;
struct u8500_i2c_regs *i2c_regs;
i2c_regs = i2c_dev[i2c_bus_num];
rc = __i2c_write(i2c_regs, chip, addr, alen, buffer,
len);
if (rc != 0) {
debug("I2C write: I/O error\n");
i2c_abort(i2c_regs);
return rc;
}
return 0;
}
int i2c_set_bus_num(unsigned int bus)
{
if (bus > ARRAY_SIZE(i2c_dev) - 1) {
debug("i2c_set_bus_num: only up to bus %d supported\n",
ARRAY_SIZE(i2c_dev)-1);
return -1;
}
i2c_bus_num = bus;
if (!bus_initialized[i2c_bus_num])
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
return 0;
}
int i2c_set_bus_speed(unsigned int speed)
{
if (speed > U8500_I2C_MAX_STANDARD_SCL) {
debug("i2c_set_bus_speed: only up to %d supported\n",
U8500_I2C_MAX_STANDARD_SCL);
return -1;
}
/* sets as side effect i2c_bus_speed[i2c_bus_num] */
i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
return 0;
}
unsigned int i2c_get_bus_num(void)
{
return i2c_bus_num;
}
unsigned int i2c_get_bus_speed(void)
{
return i2c_bus_speed[i2c_bus_num];
}

194
drivers/i2c/u8500_i2c.h Normal file
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/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _U8500_I2C_H_
#define _U8500_I2C_H_
#include <asm/types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/u8500.h>
struct u8500_i2c_regs {
u32 cr; /* Control Register 0x00 */
u32 scr; /* Slave Address Register 0x04 */
u32 hsmcr; /* HS Master code Register 0x08 */
u32 mcr; /* Master Control Register 0x0C */
u32 tfr; /* Transmit Fifo Register 0x10 */
u32 sr; /* Status Register 0x14 */
u32 rfr; /* Receiver Fifo Register 0x18 */
u32 tftr; /* Transmit Fifo Threshold Register 0x1C */
u32 rftr; /* Receiver Fifo Threshold Register 0x20 */
u32 dmar; /* DMA register 0x24 */
u32 brcr; /* Baud Rate Counter Register 0x28 */
u32 imscr; /* Interrupt Mask Set and Clear Register 0x2C */
u32 risr; /* Raw interrupt status register 0x30 */
u32 misr; /* Masked interrupt status register 0x34 */
u32 icr; /* Interrupt Set and Clear Register 0x38 */
u32 reserved_1[(0xFE0 - 0x3c) >> 2]; /* Reserved 0x03C to 0xFE0 */
u32 periph_id_0; /* peripheral ID 0 0xFE0 */
u32 periph_id_1; /* peripheral ID 1 0xFE4 */
u32 periph_id_2; /* peripheral ID 2 0xFE8 */
u32 periph_id_3; /* peripheral ID 3 0xFEC */
u32 cell_id_0; /* I2C cell ID 0 0xFF0 */
u32 cell_id_1; /* I2C cell ID 1 0xFF4 */
u32 cell_id_2; /* I2C cell ID 2 0xFF8 */
u32 cell_id_3; /* I2C cell ID 3 0xFFC */
};
/* Control Register */
/* Mask values for control register mask */
#define U8500_I2C_CR_PE 0x0001 /* Peripheral enable */
#define U8500_I2C_CR_OM 0x0006 /* Operation mode */
#define U8500_I2C_CR_SAM 0x0008 /* Slave Addressing mode */
#define U8500_I2C_CR_SM 0x0030 /* Speed mode */
#define U8500_I2C_CR_SGCM 0x0040 /* Slave General call mode */
#define U8500_I2C_CR_FTX 0x0080 /* Flush Transmit */
#define U8500_I2C_CR_FRX 0x0100 /* Flush Receive */
#define U8500_I2C_CR_DMA_TX_EN 0x0200 /* DMA TX Enable */
#define U8500_I2C_CR_DMA_RX_EN 0x0400 /* DMA Rx Enable */
#define U8500_I2C_CR_DMA_SLE 0x0800 /* DMA Synchronization Logic enable */
#define U8500_I2C_CR_LM 0x1000 /* Loop back mode */
#define U8500_I2C_CR_FON 0x6000 /* Filtering On */
/* shift valus for control register bit fields */
#define U8500_I2C_CR_SHIFT_PE 0 /* Peripheral enable */
#define U8500_I2C_CR_SHIFT_OM 1 /* Operation mode */
#define U8500_I2C_CR_SHIFT_SAM 3 /* Slave Addressing mode */
#define U8500_I2C_CR_SHIFT_SM 4 /* Speed mode */
#define U8500_I2C_CR_SHIFT_SGCM 6 /* Slave General call mode */
#define U8500_I2C_CR_SHIFT_FTX 7 /* Flush Transmit */
#define U8500_I2C_CR_SHIFT_FRX 8 /* Flush Receive */
#define U8500_I2C_CR_SHIFT_DMA_TX_EN 9 /* DMA TX Enable */
#define U8500_I2C_CR_SHIFT_DMA_RX_EN 10 /* DMA Rx Enable */
#define U8500_I2C_CR_SHIFT_DMA_SLE 11 /* DMA Synch Logic enable */
#define U8500_I2C_CR_SHIFT_LM 12 /* Loop back mode */
#define U8500_I2C_CR_SHIFT_FON 13 /* Filtering On */
/* bus operation modes */
#define U8500_I2C_BUS_SLAVE_MODE 0
#define U8500_I2C_BUS_MASTER_MODE 1
#define U8500_I2C_BUS_MASTER_SLAVE_MODE 2
/* Slave control register*/
/* Mask values slave control register */
#define U8500_I2C_SCR_ADDR 0x3FF
#define U8500_I2C_SCR_DATA_SETUP_TIME 0xFFFF0000
/* Shift values for Slave control register */
#define U8500_I2C_SCR_SHIFT_ADDR 0
#define U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME 16
/* Master Control Register */
/* Mask values for Master control register */
#define U8500_I2C_MCR_OP 0x00000001 /* Operation */
#define U8500_I2C_MCR_A7 0x000000FE /* LSB bits of Address */
#define U8500_I2C_MCR_EA10 0x00000700 /* Extended Address */
#define U8500_I2C_MCR_SB 0x00000800 /* Start byte procedure */
#define U8500_I2C_MCR_AM 0x00003000 /* Address type */
#define U8500_I2C_MCR_STOP 0x00004000 /* stop condition */
#define U8500_I2C_MCR_LENGTH 0x03FF8000 /* Frame length */
#define U8500_I2C_MCR_A10 0x000007FE /* Enable 10 bit address */
/* mask for length field,stop and operation */
#define U8500_I2C_MCR_LENGTH_STOP_OP 0x3FFC001
/* Shift values for Master control values */
#define U8500_I2C_MCR_SHIFT_OP 0 /* Operation */
#define U8500_I2C_MCR_SHIFT_A7 1 /* LSB bits of Address */
#define U8500_I2C_MCR_SHIFT_EA10 8 /* Extended Address */
#define U8500_I2C_MCR_SHIFT_SB 11 /* Start byte procedure */
#define U8500_I2C_MCR_SHIFT_AM 12 /* Address type */
#define U8500_I2C_MCR_SHIFT_STOP 14 /* stop condition */
#define U8500_I2C_MCR_SHIFT_LENGTH 15 /* Frame length */
#define U8500_I2C_MCR_SHIFT_A10 1 /* Enable 10 bit address */
#define U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP 0
/* Status Register */
/* Mask values for Status register */
#define U8500_I2C_SR_OP 0x00000003 /* Operation */
#define U8500_I2C_SR_STATUS 0x0000000C /* Controller Status */
#define U8500_I2C_SR_CAUSE 0x00000070 /* Abort Cause */
#define U8500_I2C_SR_TYPE 0x00000180 /* Receive Type */
#define U8500_I2C_SR_LENGTH 0x000FF700 /* Transfer length */
/* Shift values for Status register */
#define U8500_I2C_SR_SHIFT_OP 0 /* Operation */
#define U8500_I2C_SR_SHIFT_STATUS 2 /* Controller Status */
#define U8500_I2C_SR_SHIFT_CAUSE 4 /* Abort Cause */
#define U8500_I2C_SR_SHIFT_TYPE 7 /* Receive Type */
#define U8500_I2C_SR_SHIFT_LENGTH 9 /* Transfer length */
/* abort cause */
#define U8500_I2C_NACK_ADDR 0
#define U8500_I2C_NACK_DATA 1
#define U8500_I2C_ACK_MCODE 2
#define U8500_I2C_ARB_LOST 3
#define U8500_I2C_BERR_START 4
#define U8500_I2C_BERR_STOP 5
#define U8500_I2C_OVFL 6
/* Baud rate counter registers */
/* Mask values for Baud rate counter register */
#define U8500_I2C_BRCR_BRCNT2 0xFFFF /* Baud Rate Cntr BRCR for HS */
#define U8500_I2C_BRCR_BRCNT1 0xFFFF0000 /* BRCR for Standard and Fast */
/* Shift values for the Baud rate counter register */
#define U8500_I2C_BRCR_SHIFT_BRCNT2 0
#define U8500_I2C_BRCR_SHIFT_BRCNT1 16
/* Interrupt Register */
/* Mask values for Interrupt registers */
#define U8500_I2C_INT_TXFE 0x00000001 /* Tx fifo empty */
#define U8500_I2C_INT_TXFNE 0x00000002 /* Tx Fifo nearly empty */
#define U8500_I2C_INT_TXFF 0x00000004 /* Tx Fifo Full */
#define U8500_I2C_INT_TXFOVR 0x00000008 /* Tx Fifo over run */
#define U8500_I2C_INT_RXFE 0x00000010 /* Rx Fifo Empty */
#define U8500_I2C_INT_RXFNF 0x00000020 /* Rx Fifo nearly empty */
#define U8500_I2C_INT_RXFF 0x00000040 /* Rx Fifo Full */
#define U8500_I2C_INT_RFSR 0x00010000 /* Read From slave request */
#define U8500_I2C_INT_RFSE 0x00020000 /* Read from slave empty */
#define U8500_I2C_INT_WTSR 0x00040000 /* Write to Slave request */
#define U8500_I2C_INT_MTD 0x00080000 /* Master Transcation Done*/
#define U8500_I2C_INT_STD 0x00100000 /* Slave Transaction Done */
#define U8500_I2C_INT_MAL 0x01000000 /* Master Arbitation Lost */
#define U8500_I2C_INT_BERR 0x02000000 /* Bus Error */
#define U8500_I2C_INT_MTDWS 0x10000000 /* Master Tran Done wo/ Stop */
/* Max clocks (Hz) */
#define U8500_I2C_MAX_STANDARD_SCL 100000
#define U8500_I2C_MAX_FAST_SCL 400000
#define U8500_I2C_MAX_HIGH_SPEED_SCL 3400000
#endif /* _U8500_I2C_H_ */

6
drivers/mmc/s5p_mmc.c
View file

@ -22,6 +22,7 @@
#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/mmc.h>
#include <asm/arch/clk.h>
/* support 4 mmc hosts */
struct mmc mmc_dev[4];
@ -291,6 +292,8 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
clk = (div << 8) | (1 << 0);
writew(clk, &host->reg->clkcon);
set_mmc_clk(host->dev_index, div);
/* Wait max 10 ms */
timeout = 10;
while (!(readw(&host->reg->clkcon) & (1 << 1))) {
@ -464,9 +467,10 @@ static int s5p_mmc_initialize(int dev_index, int bus_width)
mmc->f_min = 400000;
mmc->f_max = 52000000;
mmc_host[dev_index].dev_index = dev_index;
mmc_host[dev_index].clock = 0;
mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
mmc->m_bmax = 0;
mmc->b_max = 0;
mmc_register(mmc);
return 0;

2
drivers/net/mvgbe.h
View file

@ -84,6 +84,7 @@
MVGBE_TX_BURST_SIZE_16_64BIT)
/* Default port serial control value */
#ifndef PORT_SERIAL_CONTROL_VALUE
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
@ -101,6 +102,7 @@
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
#endif
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */

5
include/configs/VCMA9.h
View file

@ -247,4 +247,9 @@
#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

1
include/configs/aspenite.h
View file

@ -53,7 +53,6 @@
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_I2C
#define CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*

1
include/configs/dkb.h
View file

@ -46,7 +46,6 @@
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS

9
include/configs/km/keymile-common.h
View file

@ -30,15 +30,6 @@
#define CONFIG_BOOTCOUNT_LIMIT
/*
* By default kwbimage.cfg from board specific folder is used
* If for some board, different configuration file need to be used,
* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
*/
#ifndef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */
/*
* Command line configuration.
*/

25
include/configs/km/km_arm.h
View file

@ -64,6 +64,9 @@
#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */
#define CONFIG_KM_DEF_ENV_CPU \
"addbootcount=" \
"setenv bootargs ${bootargs} " \
"bootcountaddr=${bootcountaddr}\0" \
"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
"boot=bootm ${actual_kernel_addr} - -\0" \
"cramfsloadfdt=true\0" \
@ -88,6 +91,7 @@
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
/*
* Serial Port configuration
@ -132,7 +136,12 @@
#define BOOTFLASH_START 0x0
/* Kirkwood has two serial IF */
#if (CONFIG_CONS_INDEX == 2)
#define CONFIG_KM_CONSOLE_TTY "ttyS1"
#else
#define CONFIG_KM_CONSOLE_TTY "ttyS0"
#endif
/*
* Other required minimal configurations
@ -239,9 +248,25 @@ int get_scl(void);
"sf write ${u-boot_addr_r} 0 ${filesize};" \
"spi off\0"
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
"newenv=setenv addr 0x100000 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
"rootpath=/opt/eldk/arm\0" \
"EEprom_ivm=" KM_IVM_BUS "\0" \
""
#if defined(CONFIG_SYS_NO_FLASH)
#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
#undef CONFIG_FLASH_CFI_MTD
#undef CONFIG_CMD_JFFS2
#undef CONFIG_JFFS2_CMDLINE
#endif

53
include/configs/mgcoge2un.h → include/configs/mgcoge3un.h
View file

@ -31,8 +31,8 @@
/* for linking errors see
* http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
#ifndef _CONFIG_MGCOGE2UN_H
#define _CONFIG_MGCOGE2UN_H
#ifndef _CONFIG_MGCOGE3UN_H
#define _CONFIG_MGCOGE3UN_H
/* include common defines/options for all arm based Keymile boards */
#include "km/km_arm.h"
@ -40,26 +40,39 @@
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nKeymile MGCOGE2UN"
#define CONFIG_HOSTNAME mgcoge2un
#define CONFIG_IDENT_STRING "\nKeymile MGCOGE3UN"
#define CONFIG_HOSTNAME mgcoge3un
#define CONFIG_MGCOGE3UN
#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
"newenv=setenv addr 0x100000 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
"rootpath=/opt/eldk/arm\0" \
"EEprom_ivm=" KM_IVM_BUS "\0" \
""
/* we use a new RAM type on mgcoge3un board */
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
#endif /* _CONFIG_MGCOGE2UN_H */
/*
* mgcoge3un has a fixed link to the marvell switch
* with 100MB full duplex and autoneg off, for this
* reason we have to change the default settings
*/
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
MVGBE_ADV_NO_FLOW_CTRL | \
MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MVGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
MVGBE_DO_NOT_FORCE_LINK_FAIL | \
MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
MVGBE_DTE_ADV_0 | \
MVGBE_MIIPHY_MAC_MODE | \
MVGBE_AUTO_NEG_NO_CHANGE | \
MVGBE_MAX_RX_PACKET_1552BYTE | \
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
MVGBE_SET_GMII_SPEED_TO_10_100 |\
MVGBE_SET_MII_SPEED_TO_100)
#endif /* _CONFIG_MGCOGE3UN_H */

32
include/configs/mx31pdk.h
View file

@ -33,17 +33,17 @@
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
#define CONFIG_MX31 1 /* in a mx31 */
#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
#define CONFIG_MX31 /* in a mx31 */
#define CONFIG_MX31_HCLK_FREQ 26000000
#define CONFIG_MX31_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SKIP_LOWLEVEL_INIT
@ -58,12 +58,12 @@
* Hardware drivers
*/
#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
#define CONFIG_MXC_UART
#define CONFIG_SYS_MX31_UART1
#define CONFIG_HW_WATCHDOG
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
@ -72,7 +72,7 @@
#define CONFIG_FSL_PMIC_CS 2
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
#define CONFIG_RTC_MC13783
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@ -114,9 +114,9 @@
"nand write 0x81000000 0x0 0x40000\0"
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE 0xB6000000
#define CONFIG_SMC911X_32_BIT 1
#define CONFIG_SMC911X_32_BIT
/*
* Miscellaneous configurable options
@ -141,7 +141,7 @@
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_CMDLINE_EDITING
/*-----------------------------------------------------------------------
* Stack sizes
@ -156,7 +156,7 @@
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
@ -168,9 +168,9 @@
* FLASH and environment organization
*/
/* No NOR flash present */
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_OFFSET_REDUND 0x60000
#define CONFIG_ENV_SIZE (128 * 1024)

3
include/configs/mx51evk.h
View file

@ -226,7 +226,4 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_OF_LIBFDT
#define CONFIG_SYS_BOOTMAPSZ 0x800000
#endif

3
include/configs/mx53evk.h
View file

@ -192,7 +192,4 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_OF_LIBFDT
#define CONFIG_SYS_BOOTMAPSZ 0x800000
#endif /* __CONFIG_H */

185
include/configs/mx53loco.h Normal file
View file

@ -0,0 +1,185 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* Configuration settings for Freescale MX53 low cost board.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MX53
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_L2_OFF
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_SYS_MX53_UART1
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
/* Eth Configs */
#define CONFIG_HAS_ETH1
#define CONFIG_NET_MULTI
#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1F
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/* Command definition */
#include <config_cmd_default.h>
#undef CONFIG_CMD_IMLS
#define CONFIG_BOOTDELAY 3
#define CONFIG_PRIME "FEC0"
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=uImage\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm\0" \
"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"dhcp ${uimage}; bootm\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "MX53LOCO U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x70000000
#define CONFIG_SYS_MEMTEST_END 0x70010000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/* Stack sizes */
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_OF_LIBFDT
#endif /* __CONFIG_H */

191
include/configs/mx53smd.h Normal file
View file

@ -0,0 +1,191 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
*
* Configuration settings for the MX53-SMDFreescale board.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MX53
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_L2_OFF
#include <asm/arch/imx-regs.h>
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_SYS_MX53_UART1
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT2
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
/* Eth Configs */
#define CONFIG_HAS_ETH1
#define CONFIG_NET_MULTI
#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1F
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/* Command definition */
#include <config_cmd_default.h>
#undef CONFIG_CMD_IMLS
#define CONFIG_BOOTDELAY 3
#define CONFIG_PRIME "FEC0"
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=uImage\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm\0" \
"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"dhcp ${uimage}; bootm\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "MX53SMD U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x70000000
#define CONFIG_SYS_MEMTEST_END 0x10000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/* Stack sizes */
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_OF_LIBFDT
#endif /* __CONFIG_H */

1
include/configs/openrd.h
View file

@ -62,7 +62,6 @@
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#define CONFIG_SYS_MVFS
#include <config_cmd_default.h>
#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII

1
include/configs/rd6281a.h
View file

@ -44,7 +44,6 @@
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT

175
include/configs/smdk2410.h
View file

@ -33,22 +33,23 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
#define CONFIG_ARM920T /* This is an ARM920T Core */
#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
#define USE_920T_MMU 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
#define CONFIG_SYS_CLK_FREQ 12000000
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/*
* Hardware drivers
@ -62,19 +63,24 @@
* select serial console configuration
*/
#define CONFIG_S3C24X0_SERIAL
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
/************************************************************
* USB support (currently only works with D-cache off)
************************************************************/
#define CONFIG_USB_OHCI
#define CONFIG_USB_KEYBOARD
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
/************************************************************
* RTC
************************************************************/
#define CONFIG_RTC_S3C24X0 1
#define CONFIG_RTC_S3C24X0
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
/*
* BOOTP options
*/
@ -83,52 +89,71 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_BOOTDELAY 3
/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */
#define CONFIG_NETMASK 255.255.255.0
/* autoboot */
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_RESET_TO_RETRY
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.0.0.110
#define CONFIG_SERVERIP 10.0.0.1
/*#define CONFIG_BOOTFILE "elinos-lart" */
/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "SMDK2410 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "SMDK2410 # "
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
/* may be activated as soon as s3c24x0 has print_cpuinfo support */
/*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */
#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_LOAD_ADDR 0x30800000
#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* support additional compression methods */
#define CONFIG_BZIP2
#define CONFIG_LZO
#define CONFIG_LZMA
/*-----------------------------------------------------------------------
* Stack sizes
*
@ -143,40 +168,72 @@
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
#if 0
#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx16
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_SECT (19)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000)
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 0x10000
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/*
* Size of malloc() pool
* BZIP2 / LZO / LZMA need a lot of RAM
*/
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_LEN (448 * 1024)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/*
* NAND configuration
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_S3C2410
#define CONFIG_SYS_S3C2410_NAND_HWECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x4E000000
#endif
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#ifdef CONFIG_AMD_LV800
#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
#endif
#ifdef CONFIG_AMD_LV400
#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
#endif
/*
* File system
*/
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_YAFFS2
#define CONFIG_RBTREE
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
#endif /* __CONFIG_H */

169
include/configs/smdkv310.h Normal file
View file

@ -0,0 +1,169 @@
/*
* Copyright (C) 2011 Samsung Electronics
*
* Configuration settings for the SAMSUNG SMDKV310 (S5PC210) board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_ARMV7 1 /*This is an ARM V7 CPU core */
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5P 1 /* S5P Family */
#define CONFIG_S5PC210 1 /* which is in a S5PC210 SoC */
#define CONFIG_SMDKV310 1 /* working with SMDKV310*/
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* Keep L2 Cache Disabled */
#define CONFIG_L2_OFF 1
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x43E00000
/* input clock of PLL: SMDKV310 has 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ 24000000
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
/* Handling Sleep Mode*/
#define S5P_CHECK_SLEEP 0x00000BAD
#define S5P_CHECK_DIDLE 0xBAD00000
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SERIAL1 1 /* use SERIAL 1 */
#define CONFIG_BAUDRATE 115200
#define S5PC210_DEFAULT_UART_OFFSET 0x010000
/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_S5P_MMC 1
/* PWM */
#define CONFIG_PWM 1
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Command definition*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NET
#define CONFIG_CMD_FAT
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_MMC_U_BOOT
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "SMDKV310 # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* Stack sizes */
#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
/* SMDKV310 has 4 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS 4
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH 1
#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING " for SMDKC210/V310"
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
#define CONFIG_CLK_1000_400_200
/* MIU (Memory Interleaving Unit) */
#define CONFIG_MIU_2BIT_INTERLEAVED
#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
#define RESERVE_BLOCK_SIZE (512)
#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
/* U-boot copy size from boot Media to DRAM.*/
#define COPY_BL2_SIZE 0x80000
#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE 0x5000000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_ENV_SROM_BANK 1
#endif /*CONFIG_CMD_NET*/
#endif /* __CONFIG_H */

15
include/configs/suen3.h
View file

@ -46,19 +46,4 @@
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
"newenv=setenv addr 0x100000 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
"rootpath=/opt/eldk/arm\0" \
"EEprom_ivm=" KM_IVM_BUS "\0" \
""
#endif /* _CONFIG_SUEN3_H */

15
include/configs/suen8.h
View file

@ -47,19 +47,4 @@
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
"newenv=setenv addr 0x100000 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
"rootpath=/opt/eldk/arm\0" \
"EEprom_ivm=" KM_IVM_BUS "\0" \
""
#endif /* _CONFIG_SUEN8_H */

245
include/configs/u8500_href.h Normal file
View file

@ -0,0 +1,245 @@
/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_U8500
#define CONFIG_L2_OFF
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
#define CONFIG_SYS_HZ 1000 /* must be 1000 */
#define CONFIG_BOARD_EARLY_INIT_F
#define BOARD_LATE_INIT
/*
* Size of malloc() pool
*/
#ifdef CONFIG_BOOT_SRAM
#define CONFIG_ENV_SIZE (32*1024)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024)
#else
#define CONFIG_ENV_SIZE (128*1024)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
#endif
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
/*
* PL011 Configuration
*/
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_SERIAL_RLCR
#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
/*
* U8500 UART registers base for 3 serial devices
*/
#define CFG_UART0_BASE 0x80120000
#define CFG_UART1_BASE 0x80121000
#define CFG_UART2_BASE 0x80007000
#define CFG_SERIAL0 CFG_UART0_BASE
#define CFG_SERIAL1 CFG_UART1_BASE
#define CFG_SERIAL2 CFG_UART2_BASE
#define CONFIG_PL011_CLOCK 38400000
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
(void *)CFG_SERIAL2 }
#define CONFIG_CONS_INDEX 2
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Devices and file systems
*/
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
/*
* Commands
*/
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_BDI
#define CONFIG_CMD_IMI
#define CONFIG_CMD_MISC
#define CONFIG_CMD_RUN
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EMMC
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_I2C
#ifndef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY 1
#endif
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND "run emmcboot"
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
"loadaddr=0x00100000\0" \
"console=ttyAMA2,115200n8\0" \
"memargs256=mem=96M@0 mem_modem=32M@96M mem=30M@128M " \
"pmem=22M@158M pmem_hwb=44M@180M mem_mali=32@224M\0" \
"memargs512=mem=96M@0 mem_modem=32M@96M mem=44M@128M " \
"pmem=22M@172M mem=30M@194M mem_mali=32M@224M " \
"pmem_hwb=54M@256M mem=202M@310M\0" \
"commonargs=setenv bootargs cachepolicy=writealloc noinitrd " \
"init=init " \
"board_id=${board_id} " \
"logo.${logo} " \
"startup_graphics=${startup_graphics}\0" \
"emmcargs=setenv bootargs ${bootargs} " \
"root=/dev/mmcblk0p2 " \
"rootdelay=1\0" \
"addcons=setenv bootargs ${bootargs} " \
"console=${console}\0" \
"emmcboot=echo Booting from eMMC ...; " \
"run commonargs emmcargs addcons memargs;" \
"mmc read 0 ${loadaddr} 0xA0000 0x4000;" \
"bootm ${loadaddr}\0" \
"flash=mmc init 1;fatload mmc 1 ${loadaddr} flash.scr;" \
"source ${loadaddr}\0" \
"loaduimage=mmc init 1;fatload mmc 1 ${loadaddr} uImage\0" \
"usbtty=cdc_acm\0" \
"stdout=serial,usbtty\0" \
"stdin=serial,usbtty\0" \
"stderr=serial,usbtty\0"
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
#define CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SETUP_MEMORY_TAGS 2
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
/*
* I2C
*/
#define CONFIG_U8500_I2C
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0 /* slave addr of controller */
#define CONFIG_SYS_U8500_I2C0_BASE 0x80004000
#define CONFIG_SYS_U8500_I2C1_BASE 0x80122000
#define CONFIG_SYS_U8500_I2C2_BASE 0x80128000
#define CONFIG_SYS_U8500_I2C3_BASE 0x80110000
#define CONFIG_SYS_U8500_I2C_BUS_MAX 4
#define CONFIG_SYS_I2C_GPIOE_ADDR 0x42 /* GPIO expander chip addr */
#define CONFIG_TC35892_GPIO
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
#define PHYS_SDRAM_SIZE_1 0x20000000 /* 512 MB */
/*
* additions for new relocation code
*/
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
/* landing address before relocation */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x0
#endif
/*
* MMC related configs
* NB Only externa SD slot is currently supported
*/
#define MMC_BLOCK_SIZE 512
#define CONFIG_ARM_PL180_MMCI
#define CONFIG_ARM_PL180_MMCI_BASE 0x80126000 /* MMC base for 8500 */
#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
#define CONFIG_MMC_DEV_NUM 1
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV /* CMD_ENV is obsolete but used in env_emmc.c */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET 0x13F80000
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
/*
* FLASH and environment organization
*/
#define CONFIG_SYS_NO_FLASH
/*
* base register values for U8500
*/
#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock
management unit */
#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
#endif /* __CONFIG_H */

1
include/configs/vision2.h
View file

@ -27,6 +27,7 @@
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_L2_OFF
#define CONFIG_SYS_TEXT_BASE 0x97800000
#include <asm/arch/imx-regs.h>

105
mmc_spl/board/samsung/smdkv310/Makefile Normal file
View file

@ -0,0 +1,105 @@
#
# (C) Copyright 2006-2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# (C) Copyright 2011
# Chander Kashyap, Samsung Electronics, <k.chander@samsung.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_MMC_SPL = y
include $(TOPDIR)/config.mk
LDSCRIPT= $(TOPDIR)/mmc_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS = -Bstatic -T $(mmcobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_MMC_SPL
CFLAGS += -DCONFIG_MMC_SPL
CFLAGS += -DCONFIG_PRELOADER
SOBJS = start.o mem_setup.o lowlevel_init.o
COBJS = mmc_boot.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(OBJTREE)/mmc_spl/board/$(BOARDDIR)
mmcobj := $(OBJTREE)/mmc_spl/
MKV310_MMC_SPL_EXEC = mkv310_mmc_spl_exec
MMC_SPL_BIN = u-boot-mmc-spl.bin
ALL = $(mmcobj)u-boot-spl $(mmcobj)u-boot-spl.bin $(mmcobj)$(MMC_SPL_BIN)
all: $(obj).depend $(ALL)
$(mmcobj)$(MMC_SPL_BIN): $(mmcobj)u-boot-spl.bin tools/$(MKV310_MMC_SPL_EXEC)
./tools/$(MKV310_MMC_SPL_EXEC) $(mmcobj)u-boot-spl.bin $(mmcobj)$(MMC_SPL_BIN)
rm -f tools/$(MKV310_MMC_SPL_EXEC)
tools/$(MKV310_MMC_SPL_EXEC): tools/mkv310_image.c
$(HOSTCC) tools/mkv310_image.c -o tools/$(MKV310_MMC_SPL_EXEC)
$(mmcobj)u-boot-spl.bin: $(mmcobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(mmcobj)u-boot-spl: $(OBJS) $(mmcobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
-Map $(mmcobj)u-boot-spl.map \
-o $(mmcobj)u-boot-spl
$(mmcobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)start.S:
@rm -f $@
@ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@
# from board directory
$(obj)mem_setup.S:
@rm -f $@
@ln -s $(TOPDIR)/board/samsung/smdkv310/mem_setup.S $@
$(obj)lowlevel_init.S:
@rm -f $@
@ln -s $(TOPDIR)/board/samsung/smdkv310/lowlevel_init.S $@
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

85
mmc_spl/board/samsung/smdkv310/mmc_boot.c Normal file
View file

@ -0,0 +1,85 @@
/*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include<common.h>
#include<config.h>
typedef u32(*copy_sd_mmc_to_mem) \
(u32 start_block, u32 block_count, u32 *dest_addr);
void copy_uboot_to_ram(void)
{
copy_sd_mmc_to_mem copy_bl2 = (copy_sd_mmc_to_mem)(0x00002488);
copy_bl2(BL2_START_OFFSET,\
BL2_SIZE_BLOC_COUNT, (u32 *)CONFIG_SYS_TEXT_BASE);
}
void board_init_f(unsigned long bootflag)
{
__attribute__((noreturn)) void (*uboot)(void);
copy_uboot_to_ram();
/* Jump to U-Boot image */
uboot = (void *)CONFIG_SYS_TEXT_BASE;
(*uboot)();
/* Never returns Here */
}
/* Place Holders */
void board_init_r(gd_t *id, ulong dest_addr)
{
/*Function attribute is no-return*/
/*This Function never executes*/
while (1)
;
}
void do_undefined_instruction(struct pt_regs *pt_regs)
{
}
void do_software_interrupt(struct pt_regs *pt_regs)
{
}
void do_prefetch_abort(struct pt_regs *pt_regs)
{
}
void do_data_abort(struct pt_regs *pt_regs)
{
}
void do_not_used(struct pt_regs *pt_regs)
{
}
void do_fiq(struct pt_regs *pt_regs)
{
}
#ifndef CONFIG_USE_IRQ
void do_irq(struct pt_regs *pt_regs)
{
}
#endif

116
mmc_spl/board/samsung/smdkv310/tools/mkv310_image.c Normal file
View file

@ -0,0 +1,116 @@
/*
* Copyright (C) 2011 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <errno.h>
#include <string.h>
#define CHECKSUM_OFFSET (14*1024-4)
#define BUFSIZE (16*1024)
#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \
| S_IWGRP | S_IROTH | S_IWOTH)
/*
* Requirement:
* IROM code reads first 14K bytes from boot device.
* It then calculates the checksum of 14K-4 bytes and compare with data at
* 14K-4 offset.
*
* This function takes two filenames:
* IN "u-boot-spl.bin" and
* OUT "u-boot-mmc-spl.bin" as filenames.
* It reads the "u-boot-spl.bin" in 16K buffer.
* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
* It writes the buffer to "u-boot-mmc-spl.bin" file.
*/
int main(int argc, char **argv)
{
int i, len;
unsigned char buffer[BUFSIZE] = {0};
int ifd, ofd;
unsigned int checksum = 0, count;
if (argc != 3) {
printf(" %d Wrong number of arguments\n", argc);
exit(EXIT_FAILURE);
}
ifd = open(argv[1], O_RDONLY);
if (ifd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
argv[0], argv[1], strerror(errno));
exit(EXIT_FAILURE);
}
ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
if (ifd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
argv[0], argv[2], strerror(errno));
if (ifd)
close(ifd);
exit(EXIT_FAILURE);
}
len = lseek(ifd, 0, SEEK_END);
lseek(ifd, 0, SEEK_SET);
count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET;
if (read(ifd, buffer, count) != count) {
fprintf(stderr, "%s: Can't read %s: %s\n",
argv[0], argv[1], strerror(errno));
if (ifd)
close(ifd);
if (ofd)
close(ofd);
exit(EXIT_FAILURE);
}
for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++)
checksum += buffer[i];
memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum));
if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
fprintf(stderr, "%s: Can't write %s: %s\n",
argv[0], argv[2], strerror(errno));
if (ifd)
close(ifd);
if (ofd)
close(ofd);
exit(EXIT_FAILURE);
}
if (ifd)
close(ifd);
if (ofd)
close(ofd);
return EXIT_SUCCESS;
}

86
mmc_spl/board/samsung/smdkv310/u-boot.lds Normal file
View file

@ -0,0 +1,86 @@
/*
* (C) Copyright 2011
* Chander Kashyap, Samsung Electronics, <k.chander@samsung.com>
*
* January 2004 - Changed to support H4 device
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : {
*(.data)
}
. = ALIGN(4);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
}
.dynsym : {
__dynsym_start = .;
*(.dynsym)
}
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss)
. = ALIGN(4);
__bss_end__ = .;
}
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}

2
nand_spl/board/samsung/smdk6400/u-boot.lds
View file

@ -67,6 +67,8 @@ SECTIONS
*(.dynsym)
}
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss)