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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
binman: Show the image name for the top-level section
At present we show 'main section' as the top-level section name. It may be more helpful to show the actual image name. This is tricky because Image is a parent class of Entry_section, so there is no distinction between an image and a section. Update it to show the image name. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
parent
a5e490f14e
commit
193d3dbd45
2 changed files with 31 additions and 39 deletions
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@ -1503,7 +1503,7 @@ class TestFunctional(unittest.TestCase):
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"""Tests outputting a map of the images"""
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_, _, map_data, _ = self._DoReadFileDtb('055_sections.dts', map=True)
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self.assertEqual('''ImagePos Offset Size Name
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00000000 00000000 00000028 main-section
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00000000 00000000 00000028 image
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00000000 00000000 00000010 section@0
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00000000 00000000 00000004 u-boot
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00000010 00000010 00000010 section@1
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@ -1516,7 +1516,7 @@ class TestFunctional(unittest.TestCase):
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"""Tests that name prefixes are used"""
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_, _, map_data, _ = self._DoReadFileDtb('056_name_prefix.dts', map=True)
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self.assertEqual('''ImagePos Offset Size Name
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00000000 00000000 00000028 main-section
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00000000 00000000 00000028 image
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00000000 00000000 00000010 section@0
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00000000 00000000 00000004 ro-u-boot
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00000010 00000010 00000010 section@1
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@ -1795,8 +1795,7 @@ class TestFunctional(unittest.TestCase):
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self._DoTestFile('071_gbb.dts', force_missing_bintools='futility',
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entry_args=entry_args)
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err = stderr.getvalue()
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self.assertRegex(err,
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"Image 'main-section'.*missing bintools.*: futility")
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self.assertRegex(err, "Image 'image'.*missing bintools.*: futility")
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def _HandleVblockCommand(self, pipe_list):
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"""Fake calls to the futility utility
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@ -1893,8 +1892,7 @@ class TestFunctional(unittest.TestCase):
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force_missing_bintools='futility',
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entry_args=entry_args)
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err = stderr.getvalue()
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self.assertRegex(err,
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"Image 'main-section'.*missing bintools.*: futility")
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self.assertRegex(err, "Image 'image'.*missing bintools.*: futility")
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def testTpl(self):
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"""Test that an image with TPL and its device tree can be created"""
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@ -2106,7 +2104,7 @@ class TestFunctional(unittest.TestCase):
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tools.get_bytes(ord('d'), 8))
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self.assertEqual(expect, data)
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self.assertEqual('''ImagePos Offset Size Name
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00000000 00000000 00000028 main-section
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00000000 00000000 00000028 image
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00000000 00000000 00000008 fill
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00000008 00000008 00000004 u-boot
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0000000c 0000000c 00000004 section
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@ -2259,7 +2257,7 @@ class TestFunctional(unittest.TestCase):
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self.assertTrue(os.path.exists(map_fname))
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map_data = tools.read_file(map_fname, binary=False)
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self.assertEqual('''ImagePos Offset Size Name
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<none> 00000000 00000008 main-section
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<none> 00000000 00000008 image
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<none> 00000000 00000004 u-boot
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<none> 00000003 00000004 u-boot-align
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''', map_data)
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@ -2274,7 +2272,7 @@ class TestFunctional(unittest.TestCase):
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data, _, map_data, _ = self._DoReadFileDtb('101_sections_offset.dts',
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map=True)
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self.assertEqual('''ImagePos Offset Size Name
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00000000 00000000 00000038 main-section
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00000000 00000000 00000038 image
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00000004 00000004 00000010 section@0
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00000004 00000000 00000004 u-boot
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00000018 00000018 00000010 section@1
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@ -2446,7 +2444,7 @@ class TestFunctional(unittest.TestCase):
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force_missing_bintools='ifwitool')
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err = stderr.getvalue()
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self.assertRegex(err,
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"Image 'main-section'.*missing bintools.*: ifwitool")
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"Image 'image'.*missing bintools.*: ifwitool")
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def testCbfsOffset(self):
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"""Test a CBFS with files at particular offsets
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@ -2633,7 +2631,7 @@ class TestFunctional(unittest.TestCase):
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ent = entries[0]
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self.assertEqual(0, ent.indent)
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self.assertEqual('main-section', ent.name)
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self.assertEqual('image', ent.name)
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self.assertEqual('section', ent.etype)
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self.assertEqual(len(data), ent.size)
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self.assertEqual(0, ent.image_pos)
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@ -2792,7 +2790,7 @@ class TestFunctional(unittest.TestCase):
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expected = [
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'Name Image-pos Size Entry-type Offset Uncomp-size',
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'----------------------------------------------------------------------',
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'main-section 0 c00 section 0',
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'image 0 c00 section 0',
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' u-boot 0 4 u-boot 0',
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' section 100 %x section 100' % section_size,
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' cbfs 100 400 cbfs 0',
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@ -3735,8 +3733,7 @@ class TestFunctional(unittest.TestCase):
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self._DoTestFile('156_mkimage.dts',
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force_missing_bintools='mkimage')
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err = stderr.getvalue()
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self.assertRegex(err,
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"Image 'main-section'.*missing bintools.*: mkimage")
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self.assertRegex(err, "Image 'image'.*missing bintools.*: mkimage")
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def testExtblob(self):
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"""Test an image with an external blob"""
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@ -3757,7 +3754,7 @@ class TestFunctional(unittest.TestCase):
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allow_missing=True)
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self.assertEqual(103, ret)
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err = stderr.getvalue()
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self.assertRegex(err, "Image 'main-section'.*missing.*: blob-ext")
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self.assertRegex(err, "Image 'image'.*missing.*: blob-ext")
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self.assertIn('Some images are invalid', err)
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def testExtblobMissingOkFlag(self):
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@ -3767,7 +3764,7 @@ class TestFunctional(unittest.TestCase):
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allow_missing=True, ignore_missing=True)
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self.assertEqual(0, ret)
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err = stderr.getvalue()
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self.assertRegex(err, "Image 'main-section'.*missing.*: blob-ext")
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self.assertRegex(err, "Image 'image'.*missing.*: blob-ext")
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self.assertIn('Some images are invalid', err)
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def testExtblobMissingOkSect(self):
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@ -3776,16 +3773,14 @@ class TestFunctional(unittest.TestCase):
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self._DoTestFile('159_blob_ext_missing_sect.dts',
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allow_missing=True)
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err = stderr.getvalue()
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self.assertRegex(err, "Image 'main-section'.*missing.*: "
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"blob-ext blob-ext2")
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self.assertRegex(err, "Image 'image'.*missing.*: blob-ext blob-ext2")
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def testPackX86RomMeMissingDesc(self):
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"""Test that an missing Intel descriptor entry is allowed"""
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with test_util.capture_sys_output() as (stdout, stderr):
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self._DoTestFile('164_x86_rom_me_missing.dts', allow_missing=True)
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err = stderr.getvalue()
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self.assertRegex(err,
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"Image 'main-section'.*missing.*: intel-descriptor")
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self.assertRegex(err, "Image 'image'.*missing.*: intel-descriptor")
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def testPackX86RomMissingIfwi(self):
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"""Test that an x86 ROM with Integrated Firmware Image can be created"""
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@ -3795,7 +3790,7 @@ class TestFunctional(unittest.TestCase):
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with test_util.capture_sys_output() as (stdout, stderr):
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self._DoTestFile('111_x86_rom_ifwi.dts', allow_missing=True)
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err = stderr.getvalue()
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self.assertRegex(err, "Image 'main-section'.*missing.*: intel-ifwi")
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self.assertRegex(err, "Image 'image'.*missing.*: intel-ifwi")
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def testPackOverlapZero(self):
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"""Test that zero-size overlapping regions are ignored"""
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@ -4009,8 +4004,7 @@ class TestFunctional(unittest.TestCase):
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self._DoTestFile('162_fit_external.dts',
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force_missing_bintools='mkimage')
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err = stderr.getvalue()
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self.assertRegex(err,
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"Image 'main-section'.*missing bintools.*: mkimage")
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self.assertRegex(err, "Image 'image'.*missing bintools.*: mkimage")
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def testSectionIgnoreHashSignature(self):
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"""Test that sections ignore hash, signature nodes for its data"""
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@ -4084,7 +4078,7 @@ class TestFunctional(unittest.TestCase):
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self._DoTestFile('168_fit_missing_blob.dts',
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allow_missing=True)
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err = stderr.getvalue()
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self.assertRegex(err, "Image 'main-section'.*missing.*: atf-bl31")
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self.assertRegex(err, "Image 'image'.*missing.*: atf-bl31")
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def testBlobNamedByArgMissing(self):
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"""Test handling of a missing entry arg"""
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@ -4490,8 +4484,7 @@ class TestFunctional(unittest.TestCase):
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self._DoTestFile('185_compress_section.dts',
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force_missing_bintools='lz4')
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err = stderr.getvalue()
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self.assertRegex(err,
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"Image 'main-section'.*missing bintools.*: lz4")
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self.assertRegex(err, "Image 'image'.*missing bintools.*: lz4")
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def testCompressExtra(self):
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"""Test compression of a section with no fixed size"""
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@ -5045,7 +5038,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap
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self._DoTestFile('216_blob_ext_list_missing.dts',
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allow_missing=True)
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err = stderr.getvalue()
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self.assertRegex(err, "Image 'main-section'.*missing.*: blob-ext")
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self.assertRegex(err, "Image 'image'.*missing.*: blob-ext")
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def testFip(self):
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"""Basic test of generation of an ARM Firmware Image Package (FIP)"""
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@ -5123,13 +5116,13 @@ fdt fdtmap Extract the devicetree blob from the fdtmap
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shutil.rmtree(tmpdir)
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lines = stdout.getvalue().splitlines()
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expected = [
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'Name Image-pos Size Entry-type Offset Uncomp-size',
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'----------------------------------------------------------------',
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'main-section 0 2d3 section 0',
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' atf-fip 0 90 atf-fip 0',
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' soc-fw 88 4 blob-ext 88',
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' u-boot 8c 4 u-boot 8c',
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' fdtmap 90 243 fdtmap 90',
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'Name Image-pos Size Entry-type Offset Uncomp-size',
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'--------------------------------------------------------------',
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'image 0 2d3 section 0',
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' atf-fip 0 90 atf-fip 0',
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' soc-fw 88 4 blob-ext 88',
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' u-boot 8c 4 u-boot 8c',
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' fdtmap 90 243 fdtmap 90',
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]
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self.assertEqual(expected, lines)
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@ -5202,7 +5195,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap
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with test_util.capture_sys_output() as (stdout, stderr):
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self._DoTestFile('209_fip_missing.dts', allow_missing=True)
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err = stderr.getvalue()
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self.assertRegex(err, "Image 'main-section'.*missing.*: rmm-fw")
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self.assertRegex(err, "Image 'image'.*missing.*: rmm-fw")
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def testFipSize(self):
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"""Test a FIP with a size property"""
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@ -5267,7 +5260,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap
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self._DoTestFile('216_blob_ext_list_missing.dts',
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allow_fake_blobs=True)
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err = stderr.getvalue()
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self.assertRegex(err, "Image 'main-section'.*faked.*: blob-ext-list")
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self.assertRegex(err, "Image 'image'.*faked.*: blob-ext-list")
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def testListBintools(self):
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args = ['tool', '--list']
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@ -5355,8 +5348,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap
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self._DoTestFile('220_fit_subentry_bintool.dts',
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force_missing_bintools='futility', entry_args=entry_args)
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err = stderr.getvalue()
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self.assertRegex(err,
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"Image 'main-section'.*missing bintools.*: futility")
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self.assertRegex(err, "Image 'image'.*missing bintools.*: futility")
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def testFitSubentryHashSubnode(self):
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"""Test an image with a FIT inside"""
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@ -77,7 +77,7 @@ class Image(section.Entry_section):
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generate=True):
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super().__init__(None, 'section', node, test=test)
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self.copy_to_orig = copy_to_orig
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self.name = 'main-section'
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self.name = name
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self.image_name = name
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self._filename = '%s.bin' % self.image_name
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self.fdtmap_dtb = None
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