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https://github.com/AsahiLinux/u-boot
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spi: davinci_spi: Convert to driver to adapt to DM
Convert davinci_spi driver so that it complies with SPI DM framework. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
This commit is contained in:
Vignesh R
Jagan Teki
parent
7c61686255
commit
192bb756dc
1 changed files with 254 additions and 103 deletions
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@ -14,6 +14,7 @@
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <dm.h>
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/* SPIGCR0 */
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#define SPIGCR0_SPIENA_MASK 0x1
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@ -51,6 +52,7 @@
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/* SPIDEF */
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#define SPIDEF_CSDEF0_MASK BIT(0)
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#ifndef CONFIG_DM_SPI
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#define SPI0_BUS 0
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#define SPI0_BASE CONFIG_SYS_SPI_BASE
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/*
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@ -83,6 +85,9 @@
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#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
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#define SPI2_BASE CONFIG_SYS_SPI2_BASE
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#endif
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* davinci spi register set */
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struct davinci_spi_regs {
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@ -114,16 +119,17 @@ struct davinci_spi_regs {
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/* davinci spi slave */
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struct davinci_spi_slave {
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#ifndef CONFIG_DM_SPI
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struct spi_slave slave;
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#endif
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struct davinci_spi_regs *regs;
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unsigned int freq;
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unsigned int freq; /* current SPI bus frequency */
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unsigned int mode; /* current SPI mode used */
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u8 num_cs; /* total no. of CS available */
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u8 cur_cs; /* CS of current slave */
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bool half_duplex; /* true, if master is half-duplex only */
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};
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static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct davinci_spi_slave, slave);
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}
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/*
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* This functions needs to act like a macro to avoid pipeline reloads in the
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* loops below. Use always_inline. This gains us about 160KiB/s and the bloat
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@ -144,15 +150,14 @@ static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
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return buf_reg_val;
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}
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static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
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static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len,
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u8 *rxp, unsigned long flags)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int data1_reg_val;
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/* enable CS hold, CS[n] and clear the data bits */
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data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
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(slave->cs << SPIDAT1_CSNR_SHIFT));
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(ds->cur_cs << SPIDAT1_CSNR_SHIFT));
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/* wait till TXFULL is deasserted */
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while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
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@ -175,15 +180,14 @@ static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
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return 0;
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}
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static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
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static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len,
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const u8 *txp, unsigned long flags)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int data1_reg_val;
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/* enable CS hold and clear the data bits */
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data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
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(slave->cs << SPIDAT1_CSNR_SHIFT));
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(ds->cur_cs << SPIDAT1_CSNR_SHIFT));
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/* wait till TXFULL is deasserted */
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while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
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@ -209,16 +213,15 @@ static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
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return 0;
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}
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#ifndef CONFIG_SPI_HALF_DUPLEX
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static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
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u8 *rxp, const u8 *txp, unsigned long flags)
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static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
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int len, u8 *rxp, const u8 *txp,
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unsigned long flags)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int data1_reg_val;
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/* enable CS hold and clear the data bits */
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data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
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(slave->cs << SPIDAT1_CSNR_SHIFT));
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(ds->cur_cs << SPIDAT1_CSNR_SHIFT));
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/* wait till TXFULL is deasserted */
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while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
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@ -237,7 +240,115 @@ static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
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return 0;
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}
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#endif
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static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
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{
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unsigned int mode = 0, scalar;
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/* Enable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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udelay(1000);
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writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
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/* Set master mode, powered up and not activated */
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writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
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/* CS, CLK, SIMO and SOMI are functional pins */
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writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
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SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
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/* setup format */
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scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
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/*
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* Use following format:
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* character length = 8,
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* MSB shifted out first
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*/
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if (ds->mode & SPI_CPOL)
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mode |= SPI_CPOL;
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if (!(ds->mode & SPI_CPHA))
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mode |= SPI_CPHA;
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writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
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(mode << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
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/*
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* Including a minor delay. No science here. Should be good even with
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* no delay
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*/
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writel((50 << SPI_C2TDELAY_SHIFT) |
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(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
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/* default chip select register */
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writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
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/* no interrupts */
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writel(0, &ds->regs->int0);
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writel(0, &ds->regs->lvl);
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/* enable SPI */
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writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
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return 0;
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}
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static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
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{
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/* Disable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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return 0;
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}
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static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
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unsigned int bitlen, const void *dout, void *din,
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unsigned long flags)
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{
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unsigned int len;
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if (bitlen == 0)
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/* Finish any previously submitted transfers */
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goto out;
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/*
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* It's not clear how non-8-bit-aligned transfers are supposed to be
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* represented as a stream of bytes...this is a limitation of
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* the current SPI interface - here we terminate on receiving such a
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* transfer request.
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*/
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if (bitlen % 8) {
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/* Errors always terminate an ongoing transfer */
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flags |= SPI_XFER_END;
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goto out;
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}
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len = bitlen / 8;
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if (!dout)
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return davinci_spi_read(ds, len, din, flags);
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if (!din)
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return davinci_spi_write(ds, len, dout, flags);
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if (!ds->half_duplex)
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return davinci_spi_read_write(ds, len, din, dout, flags);
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printf("SPI full duplex not supported\n");
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flags |= SPI_XFER_END;
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out:
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if (flags & SPI_XFER_END) {
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u8 dummy = 0;
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davinci_spi_write(ds, 1, &dummy, flags);
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}
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return 0;
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}
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#ifndef CONFIG_DM_SPI
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static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct davinci_spi_slave, slave);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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@ -313,6 +424,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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}
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ds->freq = max_hz;
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ds->mode = mode;
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return &ds->slave;
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}
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@ -324,104 +436,143 @@ void spi_free_slave(struct spi_slave *slave)
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free(ds);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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ds->cur_cs = slave->cs;
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return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int scalar;
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/* Enable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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udelay(1000);
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writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
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/* Set master mode, powered up and not activated */
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writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
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/* CS, CLK, SIMO and SOMI are functional pins */
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writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
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SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
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/* setup format */
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scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
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/*
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* Use following format:
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* character length = 8,
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* clock signal delayed by half clk cycle,
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* clock low in idle state - Mode 0,
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* MSB shifted out first
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*/
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writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
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(1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
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/*
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* Including a minor delay. No science here. Should be good even with
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* no delay
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*/
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writel((50 << SPI_C2TDELAY_SHIFT) |
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(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
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/* default chip select register */
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writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
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/* no interrupts */
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writel(0, &ds->regs->int0);
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writel(0, &ds->regs->lvl);
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/* enable SPI */
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writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
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return 0;
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#ifdef CONFIG_SPI_HALF_DUPLEX
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ds->half_duplex = true;
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#else
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ds->half_duplex = false;
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#endif
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return __davinci_spi_claim_bus(ds, ds->slave.cs);
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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/* Disable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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__davinci_spi_release_bus(ds);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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unsigned int len;
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if (bitlen == 0)
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/* Finish any previously submitted transfers */
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goto out;
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/*
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* It's not clear how non-8-bit-aligned transfers are supposed to be
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* represented as a stream of bytes...this is a limitation of
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* the current SPI interface - here we terminate on receiving such a
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* transfer request.
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*/
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if (bitlen % 8) {
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/* Errors always terminate an ongoing transfer */
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flags |= SPI_XFER_END;
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goto out;
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}
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len = bitlen / 8;
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if (!dout)
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return davinci_spi_read(slave, len, din, flags);
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else if (!din)
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return davinci_spi_write(slave, len, dout, flags);
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#ifndef CONFIG_SPI_HALF_DUPLEX
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else
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return davinci_spi_read_write(slave, len, din, dout, flags);
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#else
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printf("SPI full duplex transaction requested with "
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"CONFIG_SPI_HALF_DUPLEX defined.\n");
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flags |= SPI_XFER_END;
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#endif
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static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
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{
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struct davinci_spi_slave *ds = dev_get_priv(bus);
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debug("%s speed %u\n", __func__, max_hz);
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if (max_hz > CONFIG_SYS_SPI_CLK / 2)
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return -EINVAL;
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ds->freq = max_hz;
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out:
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if (flags & SPI_XFER_END) {
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u8 dummy = 0;
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davinci_spi_write(slave, 1, &dummy, flags);
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}
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return 0;
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}
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static int davinci_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct davinci_spi_slave *ds = dev_get_priv(bus);
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debug("%s mode %u\n", __func__, mode);
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ds->mode = mode;
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return 0;
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}
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static int davinci_spi_claim_bus(struct udevice *dev)
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{
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struct dm_spi_slave_platdata *slave_plat =
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dev_get_parent_platdata(dev);
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struct udevice *bus = dev->parent;
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struct davinci_spi_slave *ds = dev_get_priv(bus);
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if (slave_plat->cs >= ds->num_cs) {
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printf("Invalid SPI chipselect\n");
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return -EINVAL;
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}
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ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
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return __davinci_spi_claim_bus(ds, slave_plat->cs);
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}
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static int davinci_spi_release_bus(struct udevice *dev)
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{
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struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
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return __davinci_spi_release_bus(ds);
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}
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static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din,
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unsigned long flags)
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{
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struct dm_spi_slave_platdata *slave =
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dev_get_parent_platdata(dev);
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struct udevice *bus = dev->parent;
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struct davinci_spi_slave *ds = dev_get_priv(bus);
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if (slave->cs >= ds->num_cs) {
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printf("Invalid SPI chipselect\n");
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return -EINVAL;
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}
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ds->cur_cs = slave->cs;
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return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
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}
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static int davinci_spi_probe(struct udevice *bus)
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{
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/* Nothing to do */
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return 0;
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}
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static int davinci_ofdata_to_platadata(struct udevice *bus)
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{
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struct davinci_spi_slave *ds = dev_get_priv(bus);
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const void *blob = gd->fdt_blob;
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int node = bus->of_offset;
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ds->regs = dev_map_physmem(bus, sizeof(struct davinci_spi_regs));
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if (!ds->regs) {
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printf("%s: could not map device address\n", __func__);
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return -EINVAL;
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}
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ds->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
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return 0;
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}
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static const struct dm_spi_ops davinci_spi_ops = {
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.claim_bus = davinci_spi_claim_bus,
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.release_bus = davinci_spi_release_bus,
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.xfer = davinci_spi_xfer,
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.set_speed = davinci_spi_set_speed,
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.set_mode = davinci_spi_set_mode,
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};
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static const struct udevice_id davinci_spi_ids[] = {
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{ .compatible = "ti,keystone-spi" },
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{ .compatible = "ti,dm6441-spi" },
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{ }
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};
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U_BOOT_DRIVER(davinci_spi) = {
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.name = "davinci_spi",
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.id = UCLASS_SPI,
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||||
.of_match = davinci_spi_ids,
|
||||
.ops = &davinci_spi_ops,
|
||||
.ofdata_to_platdata = davinci_ofdata_to_platadata,
|
||||
.priv_auto_alloc_size = sizeof(struct davinci_spi_slave),
|
||||
.probe = davinci_spi_probe,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue