mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
mmc: Define timing macro's
Define timing macro's for all the available speeds of mmc. This is done similar to linux. Replace speed macro's used with these new timing macro's wherever applicable. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
parent
7a49a16ec5
commit
17a42abb40
3 changed files with 25 additions and 22 deletions
|
@ -8,6 +8,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <linux/delay.h>
|
||||
#include <mmc.h>
|
||||
|
||||
#define SD_DLL_CTRL 0xFF180358
|
||||
#define SD_ITAP_DLY 0xFF180314
|
||||
|
@ -54,15 +55,6 @@
|
|||
|
||||
#define MMC_BANK2 0x2
|
||||
|
||||
#define MMC_TIMING_UHS_SDR25 1
|
||||
#define MMC_TIMING_UHS_SDR50 2
|
||||
#define MMC_TIMING_UHS_SDR104 3
|
||||
#define MMC_TIMING_UHS_DDR50 4
|
||||
#define MMC_TIMING_MMC_HS200 5
|
||||
#define MMC_TIMING_SD_HS 6
|
||||
#define MMC_TIMING_MMC_DDR52 7
|
||||
#define MMC_TIMING_MMC_HS 8
|
||||
|
||||
void zynqmp_dll_reset(u8 deviceid)
|
||||
{
|
||||
/* Issue DLL Reset */
|
||||
|
|
|
@ -32,20 +32,18 @@ struct arasan_sdhci_priv {
|
|||
};
|
||||
|
||||
#if defined(CONFIG_ARCH_ZYNQMP)
|
||||
#define MMC_HS200_BUS_SPEED 5
|
||||
|
||||
static const u8 mode2timing[] = {
|
||||
[MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
|
||||
[MMC_HS] = HIGH_SPEED_BUS_SPEED,
|
||||
[SD_HS] = HIGH_SPEED_BUS_SPEED,
|
||||
[MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
|
||||
[MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
|
||||
[UHS_SDR12] = UHS_SDR12_BUS_SPEED,
|
||||
[UHS_SDR25] = UHS_SDR25_BUS_SPEED,
|
||||
[UHS_SDR50] = UHS_SDR50_BUS_SPEED,
|
||||
[UHS_DDR50] = UHS_DDR50_BUS_SPEED,
|
||||
[UHS_SDR104] = UHS_SDR104_BUS_SPEED,
|
||||
[MMC_HS_200] = MMC_HS200_BUS_SPEED,
|
||||
[MMC_LEGACY] = MMC_TIMING_LEGACY,
|
||||
[MMC_HS] = MMC_TIMING_MMC_HS,
|
||||
[SD_HS] = MMC_TIMING_SD_HS,
|
||||
[MMC_HS_52] = MMC_TIMING_UHS_SDR50,
|
||||
[MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
|
||||
[UHS_SDR12] = MMC_TIMING_UHS_SDR12,
|
||||
[UHS_SDR25] = MMC_TIMING_UHS_SDR25,
|
||||
[UHS_SDR50] = MMC_TIMING_UHS_SDR50,
|
||||
[UHS_DDR50] = MMC_TIMING_UHS_DDR50,
|
||||
[UHS_SDR104] = MMC_TIMING_UHS_SDR104,
|
||||
[MMC_HS_200] = MMC_TIMING_MMC_HS200,
|
||||
};
|
||||
|
||||
#define SDHCI_TUNING_LOOP_COUNT 40
|
||||
|
|
|
@ -360,6 +360,19 @@ enum mmc_voltage {
|
|||
#define MMC_NUM_BOOT_PARTITION 2
|
||||
#define MMC_PART_RPMB 3 /* RPMB partition number */
|
||||
|
||||
/* timing specification used */
|
||||
#define MMC_TIMING_LEGACY 0
|
||||
#define MMC_TIMING_MMC_HS 1
|
||||
#define MMC_TIMING_SD_HS 2
|
||||
#define MMC_TIMING_UHS_SDR12 3
|
||||
#define MMC_TIMING_UHS_SDR25 4
|
||||
#define MMC_TIMING_UHS_SDR50 5
|
||||
#define MMC_TIMING_UHS_SDR104 6
|
||||
#define MMC_TIMING_UHS_DDR50 7
|
||||
#define MMC_TIMING_MMC_DDR52 8
|
||||
#define MMC_TIMING_MMC_HS200 9
|
||||
#define MMC_TIMING_MMC_HS400 10
|
||||
|
||||
/* Driver model support */
|
||||
|
||||
/**
|
||||
|
|
Loading…
Reference in a new issue