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armv8: ls1088aqds: support DSPI mode by hwconfig
BRDCFG4[USBOSC] and BRDCFG5[SPR] register field of Qixis device is used to control SPI and other IP signal routing. USBOSC: 0= SPI_CLK used as external USB REFCLK input driven with 24.000 MHz. SPI devices are unusable in this mode. 1= SPI_CLK used as SPI clock. SPI devices are usable in this mode. USB block is clocked from internal sources SPR[3:2]: SPI_CS / SDHC_DAT4:7 Routing (schematic net CFG_SPI_ROUTE[3:2]): 00= SDHC/eMMC 8-bit 01= SD Card Rev 2.0/3.0 10= SPI on-board memory 11= TDM Riser / SPI off-board connector. The default value is 00 if an SDCard/eMMC card is selected as the boot device. SPR[1:0]: SPI_SIN/SOUT/SCK Routing (schematic net CFG_SPI_ROUTE[1:0]): 00= SDHC Sync loop 01= TDM Riser / SPI off-board connector. 10= SPI on-board memory. 11= SPI off-board connector. By default, the SPI feature is not available, so we need to configure the above register fields to select the route to the SPI feature. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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3 changed files with 39 additions and 0 deletions
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@ -591,6 +591,32 @@ int misc_init_r(void)
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QIXIS_WRITE(brdcfg[5], brdcfg5);
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}
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#endif
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#ifdef CONFIG_TARGET_LS1088AQDS
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u8 brdcfg4, brdcfg5;
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if (hwconfig("dspi-on-board")) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
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brdcfg4 |= BRDCFG4_SPI;
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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brdcfg5 = QIXIS_READ(brdcfg[5]);
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brdcfg5 &= ~BRDCFG5_SPR_MASK;
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brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
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QIXIS_WRITE(brdcfg[5], brdcfg5);
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} else if (hwconfig("dspi-off-board")) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
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brdcfg4 |= BRDCFG4_SPI;
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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brdcfg5 = QIXIS_READ(brdcfg[5]);
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brdcfg5 &= ~BRDCFG5_SPR_MASK;
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brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
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QIXIS_WRITE(brdcfg[5], brdcfg5);
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}
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#endif
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return 0;
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}
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#endif
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@ -41,4 +41,15 @@
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#define BRDCFG5_SPISDHC_MASK 0x0C
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#define BRDCFG5_FORCE_SD 0x08
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/* Definitions of QIXIS Registers for LS1088AQDS */
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/* BRDCFG4 */
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#define BRDCFG4_USBOSC_MASK 0x01
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#define BRDCFG4_SPI 0x01
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/* BRDCFG5 */
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#define BRDCFG5_SPR_MASK 0x0f
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#define BRDCFG5_SPI_ON_BOARD 0x0a
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#define BRDCFG5_SPI_OFF_BOARD 0x0f
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#endif
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@ -17,6 +17,8 @@ unsigned long get_board_ddr_clk(void);
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#ifdef CONFIG_TFABOOT
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_MISC_INIT_R
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_OFFSET 0x500000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
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