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doc: arch: Convert README.NDS32 to reST
Convert plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. This also merges README.N1213 contents into the new nds32.rst file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Bin Meng
Tom Rini
parent
76e4b3bbe0
commit
16b390a706
4 changed files with 102 additions and 96 deletions
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N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
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Features
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========
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CPU Core
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- 16-/32-bit mixable instruction format.
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- 32 general-purpose 32-bit registers.
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- 8-stage pipeline.
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- Dynamic branch prediction.
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- 32/64/128/256 BTB.
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- Return address stack (RAS).
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- Vector interrupts for internal/external.
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interrupt controller with 6 hardware interrupt signals.
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- 3 HW-level nested interruptions.
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- User and super-user mode support.
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- Memory-mapped I/O.
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- Address space up to 4GB.
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Memory Management Unit
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- TLB
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- 4/8-entry fully associative iTLB/dTLB.
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- 32/64/128-entry 4-way set-associati.ve main TLB.
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- TLB locking support
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- Optional hardware page table walker.
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- Two groups of page size support.
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- 4KB & 1MB.
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- 8KB & 1MB.
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Memory Subsystem
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- I & D cache.
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- Virtually indexed and physically tagged.
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- Cache size: 8KB/16KB/32KB/64KB.
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- Cache line size: 16B/32B.
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- Set associativity: 2-way, 4-way or direct-mapped.
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- Cache locking support.
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- I & D local memory (LM).
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- Size: 4KB to 1MB.
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- Bank numbers: 1 or 2.
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- Optional 1D/2D DMA engine.
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- Internal or external to CPU core.
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Bus Interface
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- Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
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- Synchronous High speed memory port.
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(HSMP): 0, 1 or 2 ports.
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Debug
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- JTAG debug interface.
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- Embedded debug module (EDM).
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- Optional embedded program tracer interface.
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Miscellaneous
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- Programmable data endian control.
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- Performance monitoring mechanism.
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@ -1,41 +0,0 @@
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NDS32 is a new high-performance 32-bit RISC microprocessor core.
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http://www.andestech.com/
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AndeStar ISA
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============
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AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
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achieve optimal system performance, code density, and power efficiency.
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It contains the following features:
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- Intermixable 32-bit and 16-bit instruction sets without the need for
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mode switch.
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- 16-bit instructions as a frequently used subset of 32-bit instructions.
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- RISC-style register-based instruction set.
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- 32 32-bit General Purpose Registers (GPR).
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- Upto 1024 User Special Registers (USR) for existing and extension
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instructions.
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- Rich load/store instructions for...
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- Single memory access with base address update.
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- Multiple aligned and unaligned memory accesses for memory copy and stack
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operations.
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- Data prefetch to improve data cache performance.
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- Non-bus locking synchronization instructions.
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- PC relative jump and PC read instructions for efficient position independent
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code.
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- Multiply-add and multiple-sub with 64-bit accumulator.
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- Instruction for efficient power management.
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- Bi-endian support.
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- Three instruction extension space for application acceleration:
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- Performance extension.
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- Andes future extensions (for floating-point, multimedia, etc.)
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- Customer extensions.
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AndesCore CPU
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=============
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Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
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For details about N12 CPU family, please check doc/README.N1213.
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The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and
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other associated software are actively supported by Andes Technology Corporation.
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@ -8,4 +8,5 @@ Architecture-specific doc
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arm64
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mips
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nds32
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x86
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101
doc/arch/nds32.rst
Normal file
101
doc/arch/nds32.rst
Normal file
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@ -0,0 +1,101 @@
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.. SPDX-License-Identifier: GPL-2.0+
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NDS32
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=====
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NDS32 is a new high-performance 32-bit RISC microprocessor core.
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http://www.andestech.com/
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AndeStar ISA
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------------
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AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
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achieve optimal system performance, code density, and power efficiency.
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It contains the following features:
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- Intermixable 32-bit and 16-bit instruction sets without the need for
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mode switch.
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- 16-bit instructions as a frequently used subset of 32-bit instructions.
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- RISC-style register-based instruction set.
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- 32 32-bit General Purpose Registers (GPR).
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- Upto 1024 User Special Registers (USR) for existing and extension
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instructions.
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- Rich load/store instructions for...
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- Single memory access with base address update.
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- Multiple aligned and unaligned memory accesses for memory copy and stack
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operations.
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- Data prefetch to improve data cache performance.
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- Non-bus locking synchronization instructions.
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- PC relative jump and PC read instructions for efficient position independent
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code.
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- Multiply-add and multiple-sub with 64-bit accumulator.
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- Instruction for efficient power management.
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- Bi-endian support.
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- Three instruction extension space for application acceleration:
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- Performance extension.
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- Andes future extensions (for floating-point, multimedia, etc.)
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- Customer extensions.
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AndesCore CPU
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-------------
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Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
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For details about N12 CPU family, please check below N1213 features.
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N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
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N1213 Features
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^^^^^^^^^^^^^^
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CPU Core
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- 16-/32-bit mixable instruction format.
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- 32 general-purpose 32-bit registers.
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- 8-stage pipeline.
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- Dynamic branch prediction.
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- 32/64/128/256 BTB.
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- Return address stack (RAS).
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- Vector interrupts for internal/external.
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interrupt controller with 6 hardware interrupt signals.
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- 3 HW-level nested interruptions.
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- User and super-user mode support.
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- Memory-mapped I/O.
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- Address space up to 4GB.
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Memory Management Unit
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- TLB
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- 4/8-entry fully associative iTLB/dTLB.
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- 32/64/128-entry 4-way set-associati.ve main TLB.
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- TLB locking support
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- Optional hardware page table walker.
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- Two groups of page size support.
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- 4KB & 1MB.
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- 8KB & 1MB.
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Memory Subsystem
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- I & D cache.
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- Virtually indexed and physically tagged.
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- Cache size: 8KB/16KB/32KB/64KB.
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- Cache line size: 16B/32B.
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- Set associativity: 2-way, 4-way or direct-mapped.
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- Cache locking support.
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- I & D local memory (LM).
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- Size: 4KB to 1MB.
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- Bank numbers: 1 or 2.
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- Optional 1D/2D DMA engine.
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- Internal or external to CPU core.
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Bus Interface
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- Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
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- Synchronous High speed memory port.
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(HSMP): 0, 1 or 2 ports.
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Debug
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- JTAG debug interface.
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- Embedded debug module (EDM).
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- Optional embedded program tracer interface.
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Miscellaneous
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- Programmable data endian control.
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- Performance monitoring mechanism.
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The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and other
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associated software are actively supported by Andes Technology Corporation.
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