mirror of
https://github.com/AsahiLinux/u-boot
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Add the files for the SMN42 board
This commit is contained in:
Peter Pearse
parent
5c6d2b5a50
commit
160131bf96
13 changed files with 2303 additions and 0 deletions
50
cpu/arm720t/lpc2292/Makefile
Normal file
50
cpu/arm720t/lpc2292/Makefile
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@ -0,0 +1,50 @@
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#
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# (C) Copyright 2000-2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).a
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COBJS = flash.o mmc.o mmc_hw.o spi.o
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SOBJS = $(obj)iap_entry.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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all: $(obj).depend $(LIB)
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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# this MUST be compiled as thumb code!
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$(SOBJS):
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$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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249
cpu/arm720t/lpc2292/flash.c
Normal file
249
cpu/arm720t/lpc2292/flash.c
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@ -0,0 +1,249 @@
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/*
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* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
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*
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* Modified to remove all but the IAP-command related code by
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* Gary Jennejohn <garyj@denx.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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/* IAP commands use 32 bytes at the top of CPU internal sram, we
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use 512 bytes below that */
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#define COPY_BUFFER_LOCATION 0x40003de0
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#define IAP_LOCATION 0x7ffffff1
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#define IAP_CMD_PREPARE 50
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#define IAP_CMD_COPY 51
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#define IAP_CMD_ERASE 52
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#define IAP_CMD_CHECK 53
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#define IAP_CMD_ID 54
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#define IAP_CMD_VERSION 55
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#define IAP_CMD_COMPARE 56
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#define IAP_RET_CMD_SUCCESS 0
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static unsigned long command[5];
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static unsigned long result[2];
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extern void iap_entry(unsigned long * command, unsigned long * result);
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/*-----------------------------------------------------------------------
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*
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*/
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static int get_flash_sector(flash_info_t * info, ulong flash_addr)
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{
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int i;
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for(i = 1; i < (info->sector_count); i++) {
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if (flash_addr < (info->start[i]))
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break;
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}
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return (i-1);
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}
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/*-----------------------------------------------------------------------
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* This function assumes that flash_addr is aligned on 512 bytes boundary
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* in flash. This function also assumes that prepare have been called
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* for the sector in question.
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*/
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int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
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{
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int first_sector;
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int last_sector;
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first_sector = get_flash_sector(info, flash_addr);
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last_sector = get_flash_sector(info, flash_addr + 512 - 1);
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/* prepare sectors for write */
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command[0] = IAP_CMD_PREPARE;
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command[1] = first_sector;
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command[2] = last_sector;
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iap_entry(command, result);
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if (result[0] != IAP_RET_CMD_SUCCESS) {
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printf("IAP prepare failed\n");
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return ERR_PROG_ERROR;
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}
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command[0] = IAP_CMD_COPY;
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command[1] = flash_addr;
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command[2] = COPY_BUFFER_LOCATION;
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command[3] = 512;
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command[4] = CFG_SYS_CLK_FREQ >> 10;
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iap_entry(command, result);
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if (result[0] != IAP_RET_CMD_SUCCESS) {
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printf("IAP copy failed\n");
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return 1;
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}
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return 0;
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}
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/*-----------------------------------------------------------------------
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*/
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int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
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{
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int flag;
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int prot;
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int sect;
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot)
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return ERR_PROTECTED;
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flag = disable_interrupts();
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printf ("Erasing %d sectors starting at sector %2d.\n"
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"This make take some time ... ",
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s_last - s_first + 1, s_first);
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command[0] = IAP_CMD_PREPARE;
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command[1] = s_first;
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command[2] = s_last;
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iap_entry(command, result);
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if (result[0] != IAP_RET_CMD_SUCCESS) {
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printf("IAP prepare failed\n");
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return ERR_PROTECTED;
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}
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command[0] = IAP_CMD_ERASE;
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command[1] = s_first;
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command[2] = s_last;
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command[3] = CFG_SYS_CLK_FREQ >> 10;
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iap_entry(command, result);
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if (result[0] != IAP_RET_CMD_SUCCESS) {
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printf("IAP erase failed\n");
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return ERR_PROTECTED;
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}
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if (flag)
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enable_interrupts();
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return ERR_OK;
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}
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int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr,
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ulong cnt)
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{
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int first_copy_size;
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int last_copy_size;
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int first_block;
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int last_block;
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int nbr_mid_blocks;
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uchar memmap_value;
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ulong i;
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uchar* src_org;
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uchar* dst_org;
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int ret = ERR_OK;
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src_org = src;
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dst_org = (uchar*)addr;
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first_block = addr / 512;
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last_block = (addr + cnt) / 512;
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nbr_mid_blocks = last_block - first_block - 1;
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first_copy_size = 512 - (addr % 512);
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last_copy_size = (addr + cnt) % 512;
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debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
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"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
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(ulong)(first_block * 512),
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(ulong)COPY_BUFFER_LOCATION,
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(ulong)src,
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(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
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first_copy_size,
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(ulong)COPY_BUFFER_LOCATION,
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(ulong)(first_block * 512));
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/* copy first block */
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memcpy((void*)COPY_BUFFER_LOCATION,
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(void*)(first_block * 512), 512);
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memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
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src, first_copy_size);
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lpc2292_copy_buffer_to_flash(info, first_block * 512);
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src += first_copy_size;
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addr += first_copy_size;
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/* copy middle blocks */
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for (i = 0; i < nbr_mid_blocks; i++) {
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debug("copy middle block: %lX -> %lX 512 bytes, "
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"%lX -> %lX 512 bytes\n",
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(ulong)src,
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(ulong)COPY_BUFFER_LOCATION,
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(ulong)COPY_BUFFER_LOCATION,
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(ulong)addr);
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memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
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lpc2292_copy_buffer_to_flash(info, addr);
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src += 512;
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addr += 512;
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}
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if (last_copy_size > 0) {
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debug("copy last block: (1) %lX -> %lX 0x200 bytes, "
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"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
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(ulong)(last_block * 512),
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(ulong)COPY_BUFFER_LOCATION,
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(ulong)src,
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(ulong)(COPY_BUFFER_LOCATION),
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last_copy_size,
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(ulong)COPY_BUFFER_LOCATION,
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(ulong)addr);
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/* copy last block */
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memcpy((void*)COPY_BUFFER_LOCATION,
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(void*)(last_block * 512), 512);
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memcpy((void*)COPY_BUFFER_LOCATION,
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src, last_copy_size);
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lpc2292_copy_buffer_to_flash(info, addr);
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}
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/* verify write */
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memmap_value = GET8(MEMMAP);
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disable_interrupts();
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PUT8(MEMMAP, 01); /* we must make sure that initial 64
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bytes are taken from flash when we
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do the compare */
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for (i = 0; i < cnt; i++) {
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if (*dst_org != *src_org){
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printf("Write failed. Byte %lX differs\n", i);
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ret = ERR_PROG_ERROR;
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break;
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}
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dst_org++;
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src_org++;
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}
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PUT8(MEMMAP, memmap_value);
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enable_interrupts();
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return ret;
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}
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7
cpu/arm720t/lpc2292/iap_entry.S
Normal file
7
cpu/arm720t/lpc2292/iap_entry.S
Normal file
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@ -0,0 +1,7 @@
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IAP_ADDRESS: .word 0x7FFFFFF1
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.globl iap_entry
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iap_entry:
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ldr r2, IAP_ADDRESS
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bx r2
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mov pc, lr
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157
cpu/arm720t/lpc2292/mmc.c
Normal file
157
cpu/arm720t/lpc2292/mmc.c
Normal file
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@ -0,0 +1,157 @@
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <mmc.h>
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#include <asm/errno.h>
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#include <asm/arch/hardware.h>
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#include <part.h>
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#include <fat.h>
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#include "mmc_hw.h"
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#include <asm/arch/spi.h>
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#ifdef CONFIG_MMC
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#undef MMC_DEBUG
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static block_dev_desc_t mmc_dev;
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/* these are filled out by a call to mmc_hw_get_parameters */
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static int hw_size; /* in kbytes */
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static int hw_nr_sects;
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static int hw_sect_size; /* in bytes */
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block_dev_desc_t * mmc_get_dev(int dev)
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{
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return (block_dev_desc_t *)(&mmc_dev);
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}
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unsigned long mmc_block_read(int dev,
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unsigned long start,
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lbaint_t blkcnt,
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void *buffer)
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{
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unsigned long rc = 0;
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unsigned char *p = (unsigned char *)buffer;
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unsigned long i;
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unsigned long addr = start;
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#ifdef MMC_DEBUG
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printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
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(unsigned long)blkcnt);
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#endif
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for(i = 0; i < (unsigned long)blkcnt; i++) {
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#ifdef MMC_DEBUG
|
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printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
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#endif
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(void)mmc_read_sector(addr, p);
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rc++;
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addr++;
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p += hw_sect_size;
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}
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return rc;
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}
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|
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/*-----------------------------------------------------------------------------
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* Read hardware paramterers (sector size, size, number of sectors)
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*/
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static int mmc_hw_get_parameters(void)
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{
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unsigned char csddata[16];
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unsigned int sizemult;
|
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unsigned int size;
|
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|
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mmc_read_csd(csddata);
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hw_sect_size = 1<<(csddata[5] & 0x0f);
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size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
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sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
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hw_nr_sects = (size+1)*(1<<(sizemult+2));
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hw_size = hw_nr_sects*hw_sect_size/1024;
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|
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#ifdef MMC_DEBUG
|
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printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
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"hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
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#endif
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|
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return 0;
|
||||
}
|
||||
|
||||
int mmc_init(int verbose)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
|
||||
if (verbose)
|
||||
printf("mmc_init\n");
|
||||
|
||||
spi_init();
|
||||
/* this meeds to be done twice */
|
||||
mmc_hw_init();
|
||||
udelay(1000);
|
||||
mmc_hw_init();
|
||||
|
||||
mmc_hw_get_parameters();
|
||||
|
||||
mmc_dev.if_type = IF_TYPE_MMC;
|
||||
mmc_dev.part_type = PART_TYPE_DOS;
|
||||
mmc_dev.dev = 0;
|
||||
mmc_dev.lun = 0;
|
||||
mmc_dev.type = 0;
|
||||
mmc_dev.blksz = hw_sect_size;
|
||||
mmc_dev.lba = hw_nr_sects;
|
||||
sprintf((char*)mmc_dev.vendor, "Unknown vendor");
|
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sprintf((char*)mmc_dev.product, "Unknown product");
|
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sprintf((char*)mmc_dev.revision, "N/A");
|
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mmc_dev.removable = 0; /* should be true??? */
|
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mmc_dev.block_read = mmc_block_read;
|
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|
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fat_register_device(&mmc_dev, 1);
|
||||
|
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ret = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mmc_write(uchar * src, ulong dst, int size)
|
||||
{
|
||||
#ifdef MMC_DEBUG
|
||||
printf("mmc_write: src=%p, dst=%lu, size=%u\n", src, dst, size);
|
||||
#endif
|
||||
/* Since mmc2info always returns 0 this function will never be called */
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_read(ulong src, uchar * dst, int size)
|
||||
{
|
||||
#ifdef MMC_DEBUG
|
||||
printf("mmc_read: src=%lu, dst=%p, size=%u\n", src, dst, size);
|
||||
#endif
|
||||
/* Since mmc2info always returns 0 this function will never be called */
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc2info(ulong addr)
|
||||
{
|
||||
/* This function is used by cmd_cp to determine if source or destination
|
||||
address resides on MMC-card or not. We do not support copy to and from
|
||||
MMC-card so we always return 0. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MMC */
|
||||
233
cpu/arm720t/lpc2292/mmc_hw.c
Normal file
233
cpu/arm720t/lpc2292/mmc_hw.c
Normal file
|
|
@ -0,0 +1,233 @@
|
|||
/*
|
||||
This code was original written by Ulrich Radig and modified by
|
||||
Embedded Artists AB (www.embeddedartists.com).
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/spi.h>
|
||||
|
||||
#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
|
||||
#define MMC_Disable() PUT32(IO1SET, 1l << 22)
|
||||
#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
|
||||
|
||||
static unsigned char Write_Command_MMC (unsigned char *CMD);
|
||||
static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
|
||||
unsigned short int Bytes);
|
||||
|
||||
/* initialize the hardware */
|
||||
int mmc_hw_init(void)
|
||||
{
|
||||
unsigned long a;
|
||||
unsigned short int Timeout = 0;
|
||||
unsigned char b;
|
||||
unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
|
||||
|
||||
/* set-up GPIO and SPI */
|
||||
(*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
|
||||
(*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
|
||||
|
||||
MMC_Disable();
|
||||
|
||||
spi_lock();
|
||||
spi_set_clock(248);
|
||||
spi_set_cfg(0, 1, 0);
|
||||
MMC_Enable();
|
||||
|
||||
/* waste some time */
|
||||
for(a=0; a < 20000; a++)
|
||||
asm("nop");
|
||||
|
||||
/* Put the MMC/SD-card into SPI-mode */
|
||||
for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
|
||||
spi_write(0xff);
|
||||
|
||||
/* Sends command CMD0 to MMC/SD-card */
|
||||
while (Write_Command_MMC(CMD) != 1) {
|
||||
if (Timeout++ > 200) {
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
return(1); /* Abort with command 1 (return 1) */
|
||||
}
|
||||
}
|
||||
/* Sends Command CMD1 an MMC/SD-card */
|
||||
Timeout = 0;
|
||||
CMD[0] = 0x41;/* Command 1 */
|
||||
CMD[5] = 0xFF;
|
||||
|
||||
while (Write_Command_MMC(CMD) != 0) {
|
||||
if (Timeout++ > 200) {
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
return (2); /* Abort with command 2 (return 2) */
|
||||
}
|
||||
}
|
||||
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ############################################################################
|
||||
Sends a command to the MMC/SD-card
|
||||
######################################################################### */
|
||||
static unsigned char Write_Command_MMC (unsigned char *CMD)
|
||||
{
|
||||
unsigned char a, tmp = 0xff;
|
||||
unsigned short int Timeout = 0;
|
||||
|
||||
MMC_Disable();
|
||||
spi_write(0xFF);
|
||||
MMC_Enable();
|
||||
|
||||
for (a = 0; a < 0x06; a++)
|
||||
spi_write(*CMD++);
|
||||
|
||||
while (tmp == 0xff) {
|
||||
tmp = spi_read();
|
||||
if (Timeout++ > 5000)
|
||||
break;
|
||||
}
|
||||
|
||||
return (tmp);
|
||||
}
|
||||
|
||||
/* ############################################################################
|
||||
Routine to read the CID register from the MMC/SD-card (16 bytes)
|
||||
######################################################################### */
|
||||
void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
|
||||
int Bytes)
|
||||
{
|
||||
unsigned short int a;
|
||||
|
||||
spi_lock();
|
||||
mmc_spi_cfg();
|
||||
MMC_Enable();
|
||||
|
||||
if (Write_Command_MMC(CMD) != 0) {
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
return;
|
||||
}
|
||||
|
||||
while (spi_read() != 0xfe) {};
|
||||
for (a = 0; a < Bytes; a++)
|
||||
*Buffer++ = spi_read();
|
||||
|
||||
/* Read the CRC-byte */
|
||||
spi_read(); /* CRC - byte is discarded */
|
||||
spi_read(); /* CRC - byte is discarded */
|
||||
/* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* ############################################################################
|
||||
Routine to read a block (512 bytes) from the MMC/SD-card
|
||||
######################################################################### */
|
||||
unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
|
||||
{
|
||||
/* Command 16 to read aBlocks from the MMC/SD - caed */
|
||||
unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
|
||||
|
||||
/* The addres on the MMC/SD-card is in bytes,
|
||||
addr is transformed from blocks to bytes and the result is
|
||||
placed into the command */
|
||||
|
||||
addr = addr << 9; /* addr = addr * 512 */
|
||||
|
||||
CMD[1] = ((addr & 0xFF000000) >> 24);
|
||||
CMD[2] = ((addr & 0x00FF0000) >> 16);
|
||||
CMD[3] = ((addr & 0x0000FF00) >> 8 );
|
||||
|
||||
MMC_Read_Block(CMD, Buffer, 512);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ############################################################################
|
||||
Routine to write a block (512 byte) to the MMC/SD-card
|
||||
######################################################################### */
|
||||
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
|
||||
{
|
||||
unsigned char tmp, a;
|
||||
unsigned short int b;
|
||||
/* Command 24 to write a block to the MMC/SD - card */
|
||||
unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
|
||||
|
||||
/* The addres on the MMC/SD-card is in bytes,
|
||||
addr is transformed from blocks to bytes and the result is
|
||||
placed into the command */
|
||||
|
||||
addr = addr << 9; /* addr = addr * 512 */
|
||||
|
||||
CMD[1] = ((addr & 0xFF000000) >> 24);
|
||||
CMD[2] = ((addr & 0x00FF0000) >> 16);
|
||||
CMD[3] = ((addr & 0x0000FF00) >> 8 );
|
||||
|
||||
spi_lock();
|
||||
mmc_spi_cfg();
|
||||
MMC_Enable();
|
||||
|
||||
/* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
|
||||
tmp = Write_Command_MMC(CMD);
|
||||
if (tmp != 0) {
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
return(tmp);
|
||||
}
|
||||
|
||||
/* Do a short delay and send a clock-pulse to the MMC/SD-card */
|
||||
for (a = 0; a < 100; a++)
|
||||
spi_read();
|
||||
|
||||
/* Send a start byte to the MMC/SD-card */
|
||||
spi_write(0xFE);
|
||||
|
||||
/* Write the block (512 bytes) to the MMC/SD-card */
|
||||
for (b = 0; b < 512; b++)
|
||||
spi_write(*Buffer++);
|
||||
|
||||
/* write the CRC-Byte */
|
||||
spi_write(0xFF); /* write a dummy CRC */
|
||||
spi_write(0xFF); /* CRC code is not used */
|
||||
|
||||
/* Wait for MMC/SD-card busy */
|
||||
while (spi_read() != 0xff) {};
|
||||
|
||||
/* set MMC_Chip_Select to high (MMC/SD-card inactive) */
|
||||
MMC_Disable();
|
||||
spi_unlock();
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* #########################################################################
|
||||
Routine to read the CSD register from the MMC/SD-card (16 bytes)
|
||||
######################################################################### */
|
||||
unsigned char mmc_read_csd (unsigned char *Buffer)
|
||||
{
|
||||
/* Command to read the CSD register */
|
||||
unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
|
||||
|
||||
MMC_Read_Block(CMD, Buffer, 16);
|
||||
|
||||
return (0);
|
||||
}
|
||||
29
cpu/arm720t/lpc2292/mmc_hw.h
Normal file
29
cpu/arm720t/lpc2292/mmc_hw.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
This module implements a linux character device driver for the 24c256 chip.
|
||||
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _MMC_HW_
|
||||
#define _MMC_HW_
|
||||
|
||||
unsigned char mmc_read_csd(unsigned char *Buffer);
|
||||
unsigned char mmc_read_sector (unsigned long addr,
|
||||
unsigned char *Buffer);
|
||||
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
|
||||
int mmc_hw_init(void);
|
||||
|
||||
#endif /* _MMC_HW_ */
|
||||
40
cpu/arm720t/lpc2292/spi.c
Normal file
40
cpu/arm720t/lpc2292/spi.c
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
This module implements an interface to the SPI on the lpc22xx.
|
||||
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/spi.h>
|
||||
|
||||
unsigned long spi_flags;
|
||||
unsigned char spi_idle = 0x00;
|
||||
|
||||
int spi_init(void)
|
||||
{
|
||||
unsigned long pinsel0_value;
|
||||
|
||||
/* activate spi pins */
|
||||
pinsel0_value = GET32(PINSEL0);
|
||||
pinsel0_value &= ~(0xFFl << 8);
|
||||
pinsel0_value |= (0x55l << 8);
|
||||
PUT32(PINSEL0, pinsel0_value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
978
drivers/enc28j60.c
Normal file
978
drivers/enc28j60.c
Normal file
|
|
@ -0,0 +1,978 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#ifdef CONFIG_ENC28J60
|
||||
#include <net.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/spi.h>
|
||||
|
||||
/*
|
||||
* Control Registers in Bank 0
|
||||
*/
|
||||
|
||||
#define CTL_REG_ERDPTL 0x00
|
||||
#define CTL_REG_ERDPTH 0x01
|
||||
#define CTL_REG_EWRPTL 0x02
|
||||
#define CTL_REG_EWRPTH 0x03
|
||||
#define CTL_REG_ETXSTL 0x04
|
||||
#define CTL_REG_ETXSTH 0x05
|
||||
#define CTL_REG_ETXNDL 0x06
|
||||
#define CTL_REG_ETXNDH 0x07
|
||||
#define CTL_REG_ERXSTL 0x08
|
||||
#define CTL_REG_ERXSTH 0x09
|
||||
#define CTL_REG_ERXNDL 0x0A
|
||||
#define CTL_REG_ERXNDH 0x0B
|
||||
#define CTL_REG_ERXRDPTL 0x0C
|
||||
#define CTL_REG_ERXRDPTH 0x0D
|
||||
#define CTL_REG_ERXWRPTL 0x0E
|
||||
#define CTL_REG_ERXWRPTH 0x0F
|
||||
#define CTL_REG_EDMASTL 0x10
|
||||
#define CTL_REG_EDMASTH 0x11
|
||||
#define CTL_REG_EDMANDL 0x12
|
||||
#define CTL_REG_EDMANDH 0x13
|
||||
#define CTL_REG_EDMADSTL 0x14
|
||||
#define CTL_REG_EDMADSTH 0x15
|
||||
#define CTL_REG_EDMACSL 0x16
|
||||
#define CTL_REG_EDMACSH 0x17
|
||||
/* these are common in all banks */
|
||||
#define CTL_REG_EIE 0x1B
|
||||
#define CTL_REG_EIR 0x1C
|
||||
#define CTL_REG_ESTAT 0x1D
|
||||
#define CTL_REG_ECON2 0x1E
|
||||
#define CTL_REG_ECON1 0x1F
|
||||
|
||||
/*
|
||||
* Control Registers in Bank 1
|
||||
*/
|
||||
|
||||
#define CTL_REG_EHT0 0x00
|
||||
#define CTL_REG_EHT1 0x01
|
||||
#define CTL_REG_EHT2 0x02
|
||||
#define CTL_REG_EHT3 0x03
|
||||
#define CTL_REG_EHT4 0x04
|
||||
#define CTL_REG_EHT5 0x05
|
||||
#define CTL_REG_EHT6 0x06
|
||||
#define CTL_REG_EHT7 0x07
|
||||
#define CTL_REG_EPMM0 0x08
|
||||
#define CTL_REG_EPMM1 0x09
|
||||
#define CTL_REG_EPMM2 0x0A
|
||||
#define CTL_REG_EPMM3 0x0B
|
||||
#define CTL_REG_EPMM4 0x0C
|
||||
#define CTL_REG_EPMM5 0x0D
|
||||
#define CTL_REG_EPMM6 0x0E
|
||||
#define CTL_REG_EPMM7 0x0F
|
||||
#define CTL_REG_EPMCSL 0x10
|
||||
#define CTL_REG_EPMCSH 0x11
|
||||
#define CTL_REG_EPMOL 0x14
|
||||
#define CTL_REG_EPMOH 0x15
|
||||
#define CTL_REG_EWOLIE 0x16
|
||||
#define CTL_REG_EWOLIR 0x17
|
||||
#define CTL_REG_ERXFCON 0x18
|
||||
#define CTL_REG_EPKTCNT 0x19
|
||||
|
||||
/*
|
||||
* Control Registers in Bank 2
|
||||
*/
|
||||
|
||||
#define CTL_REG_MACON1 0x00
|
||||
#define CTL_REG_MACON2 0x01
|
||||
#define CTL_REG_MACON3 0x02
|
||||
#define CTL_REG_MACON4 0x03
|
||||
#define CTL_REG_MABBIPG 0x04
|
||||
#define CTL_REG_MAIPGL 0x06
|
||||
#define CTL_REG_MAIPGH 0x07
|
||||
#define CTL_REG_MACLCON1 0x08
|
||||
#define CTL_REG_MACLCON2 0x09
|
||||
#define CTL_REG_MAMXFLL 0x0A
|
||||
#define CTL_REG_MAMXFLH 0x0B
|
||||
#define CTL_REG_MAPHSUP 0x0D
|
||||
#define CTL_REG_MICON 0x11
|
||||
#define CTL_REG_MICMD 0x12
|
||||
#define CTL_REG_MIREGADR 0x14
|
||||
#define CTL_REG_MIWRL 0x16
|
||||
#define CTL_REG_MIWRH 0x17
|
||||
#define CTL_REG_MIRDL 0x18
|
||||
#define CTL_REG_MIRDH 0x19
|
||||
|
||||
/*
|
||||
* Control Registers in Bank 3
|
||||
*/
|
||||
|
||||
#define CTL_REG_MAADR1 0x00
|
||||
#define CTL_REG_MAADR0 0x01
|
||||
#define CTL_REG_MAADR3 0x02
|
||||
#define CTL_REG_MAADR2 0x03
|
||||
#define CTL_REG_MAADR5 0x04
|
||||
#define CTL_REG_MAADR4 0x05
|
||||
#define CTL_REG_EBSTSD 0x06
|
||||
#define CTL_REG_EBSTCON 0x07
|
||||
#define CTL_REG_EBSTCSL 0x08
|
||||
#define CTL_REG_EBSTCSH 0x09
|
||||
#define CTL_REG_MISTAT 0x0A
|
||||
#define CTL_REG_EREVID 0x12
|
||||
#define CTL_REG_ECOCON 0x15
|
||||
#define CTL_REG_EFLOCON 0x17
|
||||
#define CTL_REG_EPAUSL 0x18
|
||||
#define CTL_REG_EPAUSH 0x19
|
||||
|
||||
|
||||
/*
|
||||
* PHY Register
|
||||
*/
|
||||
|
||||
#define PHY_REG_PHID1 0x02
|
||||
#define PHY_REG_PHID2 0x03
|
||||
/* taken from the Linux driver */
|
||||
#define PHY_REG_PHCON1 0x00
|
||||
#define PHY_REG_PHCON2 0x10
|
||||
#define PHY_REG_PHLCON 0x14
|
||||
|
||||
/*
|
||||
* Receive Filter Register (ERXFCON) bits
|
||||
*/
|
||||
|
||||
#define ENC_RFR_UCEN 0x80
|
||||
#define ENC_RFR_ANDOR 0x40
|
||||
#define ENC_RFR_CRCEN 0x20
|
||||
#define ENC_RFR_PMEN 0x10
|
||||
#define ENC_RFR_MPEN 0x08
|
||||
#define ENC_RFR_HTEN 0x04
|
||||
#define ENC_RFR_MCEN 0x02
|
||||
#define ENC_RFR_BCEN 0x01
|
||||
|
||||
/*
|
||||
* ECON1 Register Bits
|
||||
*/
|
||||
|
||||
#define ENC_ECON1_TXRST 0x80
|
||||
#define ENC_ECON1_RXRST 0x40
|
||||
#define ENC_ECON1_DMAST 0x20
|
||||
#define ENC_ECON1_CSUMEN 0x10
|
||||
#define ENC_ECON1_TXRTS 0x08
|
||||
#define ENC_ECON1_RXEN 0x04
|
||||
#define ENC_ECON1_BSEL1 0x02
|
||||
#define ENC_ECON1_BSEL0 0x01
|
||||
|
||||
/*
|
||||
* ECON2 Register Bits
|
||||
*/
|
||||
#define ENC_ECON2_AUTOINC 0x80
|
||||
#define ENC_ECON2_PKTDEC 0x40
|
||||
#define ENC_ECON2_PWRSV 0x20
|
||||
#define ENC_ECON2_VRPS 0x08
|
||||
|
||||
/*
|
||||
* EIR Register Bits
|
||||
*/
|
||||
#define ENC_EIR_PKTIF 0x40
|
||||
#define ENC_EIR_DMAIF 0x20
|
||||
#define ENC_EIR_LINKIF 0x10
|
||||
#define ENC_EIR_TXIF 0x08
|
||||
#define ENC_EIR_WOLIF 0x04
|
||||
#define ENC_EIR_TXERIF 0x02
|
||||
#define ENC_EIR_RXERIF 0x01
|
||||
|
||||
/*
|
||||
* ESTAT Register Bits
|
||||
*/
|
||||
|
||||
#define ENC_ESTAT_INT 0x80
|
||||
#define ENC_ESTAT_LATECOL 0x10
|
||||
#define ENC_ESTAT_RXBUSY 0x04
|
||||
#define ENC_ESTAT_TXABRT 0x02
|
||||
#define ENC_ESTAT_CLKRDY 0x01
|
||||
|
||||
/*
|
||||
* EIE Register Bits
|
||||
*/
|
||||
|
||||
#define ENC_EIE_INTIE 0x80
|
||||
#define ENC_EIE_PKTIE 0x40
|
||||
#define ENC_EIE_DMAIE 0x20
|
||||
#define ENC_EIE_LINKIE 0x10
|
||||
#define ENC_EIE_TXIE 0x08
|
||||
#define ENC_EIE_WOLIE 0x04
|
||||
#define ENC_EIE_TXERIE 0x02
|
||||
#define ENC_EIE_RXERIE 0x01
|
||||
|
||||
/*
|
||||
* MACON1 Register Bits
|
||||
*/
|
||||
#define ENC_MACON1_LOOPBK 0x10
|
||||
#define ENC_MACON1_TXPAUS 0x08
|
||||
#define ENC_MACON1_RXPAUS 0x04
|
||||
#define ENC_MACON1_PASSALL 0x02
|
||||
#define ENC_MACON1_MARXEN 0x01
|
||||
|
||||
|
||||
/*
|
||||
* MACON2 Register Bits
|
||||
*/
|
||||
#define ENC_MACON2_MARST 0x80
|
||||
#define ENC_MACON2_RNDRST 0x40
|
||||
#define ENC_MACON2_MARXRST 0x08
|
||||
#define ENC_MACON2_RFUNRST 0x04
|
||||
#define ENC_MACON2_MATXRST 0x02
|
||||
#define ENC_MACON2_TFUNRST 0x01
|
||||
|
||||
/*
|
||||
* MACON3 Register Bits
|
||||
*/
|
||||
#define ENC_MACON3_PADCFG2 0x80
|
||||
#define ENC_MACON3_PADCFG1 0x40
|
||||
#define ENC_MACON3_PADCFG0 0x20
|
||||
#define ENC_MACON3_TXCRCEN 0x10
|
||||
#define ENC_MACON3_PHDRLEN 0x08
|
||||
#define ENC_MACON3_HFRMEN 0x04
|
||||
#define ENC_MACON3_FRMLNEN 0x02
|
||||
#define ENC_MACON3_FULDPX 0x01
|
||||
|
||||
/*
|
||||
* MICMD Register Bits
|
||||
*/
|
||||
#define ENC_MICMD_MIISCAN 0x02
|
||||
#define ENC_MICMD_MIIRD 0x01
|
||||
|
||||
/*
|
||||
* MISTAT Register Bits
|
||||
*/
|
||||
#define ENC_MISTAT_NVALID 0x04
|
||||
#define ENC_MISTAT_SCAN 0x02
|
||||
#define ENC_MISTAT_BUSY 0x01
|
||||
|
||||
/*
|
||||
* PHID1 and PHID2 values
|
||||
*/
|
||||
#define ENC_PHID1_VALUE 0x0083
|
||||
#define ENC_PHID2_VALUE 0x1400
|
||||
#define ENC_PHID2_MASK 0xFC00
|
||||
|
||||
|
||||
#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */
|
||||
#define ENC_RESET 0x00020000 /* pin P1.17 */
|
||||
|
||||
#define FAILSAFE_VALUE 5000
|
||||
|
||||
/*
|
||||
* Controller memory layout:
|
||||
*
|
||||
* 0x0000 - 0x17ff 6k bytes receive buffer
|
||||
* 0x1800 - 0x1fff 2k bytes transmit buffer
|
||||
*/
|
||||
/* Use the lower memory for receiver buffer. See errata pt. 5 */
|
||||
#define ENC_RX_BUF_START 0x0000
|
||||
#define ENC_TX_BUF_START 0x1800
|
||||
/* taken from the Linux driver */
|
||||
#define ENC_RX_BUF_END 0x17ff
|
||||
#define ENC_TX_BUF_END 0x1fff
|
||||
|
||||
/* maximum frame length */
|
||||
#define ENC_MAX_FRM_LEN 1518
|
||||
|
||||
#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
|
||||
#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
|
||||
#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
|
||||
|
||||
|
||||
static unsigned char encReadReg (unsigned char regNo);
|
||||
static void encWriteReg (unsigned char regNo, unsigned char data);
|
||||
static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
|
||||
static void encReadBuff (unsigned short length, unsigned char *pBuff);
|
||||
static void encWriteBuff (unsigned short length, unsigned char *pBuff);
|
||||
static void encBitSet (unsigned char regNo, unsigned char data);
|
||||
static void encBitClr (unsigned char regNo, unsigned char data);
|
||||
static void encReset (void);
|
||||
static void encInit (unsigned char *pEthAddr);
|
||||
static unsigned short phyRead (unsigned char addr);
|
||||
static void phyWrite(unsigned char, unsigned short);
|
||||
static void encPoll (void);
|
||||
static void encRx (void);
|
||||
|
||||
#define m_nic_read(reg) encReadReg(reg)
|
||||
#define m_nic_write(reg, data) encWriteReg(reg, data)
|
||||
#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
|
||||
#define m_nic_read_data(len, buf) encReadBuff((len), (buf))
|
||||
#define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
|
||||
|
||||
/* bit field set */
|
||||
#define m_nic_bfs(reg, data) encBitSet(reg, data)
|
||||
|
||||
/* bit field clear */
|
||||
#define m_nic_bfc(reg, data) encBitClr(reg, data)
|
||||
|
||||
static unsigned char bank = 0; /* current bank in enc28j60 */
|
||||
static unsigned char next_pointer_lsb;
|
||||
static unsigned char next_pointer_msb;
|
||||
|
||||
static unsigned char buffer[ENC_MAX_FRM_LEN];
|
||||
static int rxResetCounter = 0;
|
||||
|
||||
#define RX_RESET_COUNTER 1000;
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Always returns 0
|
||||
*/
|
||||
int eth_init (bd_t * bis)
|
||||
{
|
||||
unsigned char estatVal;
|
||||
|
||||
/* configure GPIO */
|
||||
(*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
|
||||
(*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
|
||||
|
||||
/* CS and RESET active low */
|
||||
PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
|
||||
PUT32 (IO1SET, ENC_RESET);
|
||||
|
||||
spi_init ();
|
||||
|
||||
/* taken from the Linux driver - dangerous stuff here! */
|
||||
/* Wait for CLKRDY to become set (i.e., check that we can communicate with
|
||||
the ENC) */
|
||||
do
|
||||
{
|
||||
estatVal = m_nic_read(CTL_REG_ESTAT);
|
||||
} while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY));
|
||||
|
||||
/* initialize controller */
|
||||
encReset ();
|
||||
encInit (bis->bi_enetaddr);
|
||||
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int eth_send (volatile void *packet, int length)
|
||||
{
|
||||
/* check frame length, etc. */
|
||||
/* TODO: */
|
||||
|
||||
/* switch to bank 0 */
|
||||
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||
|
||||
/* set EWRPT */
|
||||
m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
|
||||
m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
|
||||
|
||||
/* set ETXND */
|
||||
m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
|
||||
m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
|
||||
|
||||
/* set ETXST */
|
||||
m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
|
||||
m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
|
||||
|
||||
/* write packet */
|
||||
m_nic_write_data (length, (unsigned char *) packet);
|
||||
|
||||
/* taken from the Linux driver */
|
||||
/* Verify that the internal transmit logic has not been altered by excessive
|
||||
collisions. See Errata B4 12 and 14.
|
||||
*/
|
||||
if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) {
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST);
|
||||
m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST);
|
||||
}
|
||||
m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
|
||||
|
||||
/* set ECON1.TXRTS */
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* This function resets the receiver only. This function may be called from
|
||||
* interrupt-context.
|
||||
*/
|
||||
static void encReceiverReset (void)
|
||||
{
|
||||
unsigned char econ1;
|
||||
|
||||
econ1 = m_nic_read (CTL_REG_ECON1);
|
||||
if ((econ1 & ENC_ECON1_RXRST) == 0) {
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
|
||||
rxResetCounter = RX_RESET_COUNTER;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* receiver reset timer
|
||||
*/
|
||||
static void encReceiverResetCallback (void)
|
||||
{
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Check for received packets. Call NetReceive for each packet. The return
|
||||
* value is ignored by the caller.
|
||||
*/
|
||||
int eth_rx (void)
|
||||
{
|
||||
if (rxResetCounter > 0 && --rxResetCounter == 0) {
|
||||
encReceiverResetCallback ();
|
||||
}
|
||||
|
||||
encPoll ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void eth_halt (void)
|
||||
{
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
static void encPoll (void)
|
||||
{
|
||||
unsigned char eir_reg;
|
||||
volatile unsigned char estat_reg;
|
||||
unsigned char pkt_cnt;
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* clear global interrupt enable bit in enc28j60 */
|
||||
m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||
#endif
|
||||
estat_reg = m_nic_read (CTL_REG_ESTAT);
|
||||
|
||||
eir_reg = m_nic_read (CTL_REG_EIR);
|
||||
|
||||
if (eir_reg & ENC_EIR_TXIF) {
|
||||
/* clear TXIF bit in EIR */
|
||||
m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
|
||||
}
|
||||
|
||||
/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
|
||||
|
||||
/* move to bank 1 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
|
||||
/* read pktcnt */
|
||||
pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
|
||||
|
||||
if (pkt_cnt > 0) {
|
||||
if ((eir_reg & ENC_EIR_PKTIF) == 0) {
|
||||
/*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
|
||||
}
|
||||
encRx ();
|
||||
/* clear PKTIF bit in EIR, this should not need to be done but it
|
||||
seems like we get problems if we do not */
|
||||
m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
|
||||
}
|
||||
|
||||
if (eir_reg & ENC_EIR_RXERIF) {
|
||||
printf ("encPoll: rx error\n");
|
||||
m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
|
||||
}
|
||||
if (eir_reg & ENC_EIR_TXERIF) {
|
||||
printf ("encPoll: tx error\n");
|
||||
m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* set global interrupt enable bit in enc28j60 */
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void encRx (void)
|
||||
{
|
||||
unsigned short pkt_len;
|
||||
unsigned short copy_len;
|
||||
unsigned short status;
|
||||
unsigned char eir_reg;
|
||||
unsigned char pkt_cnt = 0;
|
||||
unsigned short rxbuf_rdpt;
|
||||
|
||||
/* switch to bank 0 */
|
||||
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||
|
||||
m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
|
||||
m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
|
||||
|
||||
do {
|
||||
m_nic_read_data (6, buffer);
|
||||
next_pointer_lsb = buffer[0];
|
||||
next_pointer_msb = buffer[1];
|
||||
pkt_len = buffer[2];
|
||||
pkt_len |= (unsigned short) buffer[3] << 8;
|
||||
status = buffer[4];
|
||||
status |= (unsigned short) buffer[5] << 8;
|
||||
|
||||
if (pkt_len <= ENC_MAX_FRM_LEN)
|
||||
copy_len = pkt_len;
|
||||
else
|
||||
copy_len = 0;
|
||||
|
||||
if ((status & (1L << 7)) == 0) /* check Received Ok bit */
|
||||
copy_len = 0;
|
||||
|
||||
/* taken from the Linux driver */
|
||||
/* check if next pointer is resonable */
|
||||
if ((((unsigned int)next_pointer_msb << 8) |
|
||||
(unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START)
|
||||
copy_len = 0;
|
||||
|
||||
if (copy_len > 0) {
|
||||
m_nic_read_data (copy_len, buffer);
|
||||
}
|
||||
|
||||
/* advance read pointer to next pointer */
|
||||
m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
|
||||
m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
|
||||
|
||||
/* decrease packet counter */
|
||||
m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
|
||||
|
||||
/* taken from the Linux driver */
|
||||
/* Only odd values should be written to ERXRDPTL, see errata B4 pt.13 */ rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1;
|
||||
if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 |
|
||||
m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt >
|
||||
(m_nic_read(CTL_REG_ERXNDH) << 8 |
|
||||
m_nic_read(CTL_REG_ERXNDL)))) {
|
||||
m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL));
|
||||
m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH));
|
||||
} else {
|
||||
m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF);
|
||||
m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8);
|
||||
}
|
||||
|
||||
/* move to bank 1 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
|
||||
/* read pktcnt */
|
||||
pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
|
||||
|
||||
/* switch to bank 0 */
|
||||
m_nic_bfc (CTL_REG_ECON1,
|
||||
(ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||
|
||||
if (copy_len == 0) {
|
||||
eir_reg = m_nic_read (CTL_REG_EIR);
|
||||
encReceiverReset ();
|
||||
printf ("eth_rx: copy_len=0\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
NetReceive ((unsigned char *) buffer, pkt_len);
|
||||
|
||||
eir_reg = m_nic_read (CTL_REG_EIR);
|
||||
} while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
|
||||
}
|
||||
|
||||
static void encWriteReg (unsigned char regNo, unsigned char data)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x40 | regNo); /* write in regNo */
|
||||
spi_write (data);
|
||||
|
||||
enc_disable ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x1f); /* write reg 0x1f */
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
}
|
||||
|
||||
static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
|
||||
{
|
||||
unsigned char readback;
|
||||
int i;
|
||||
|
||||
spi_lock ();
|
||||
|
||||
for (i = 0; i < c; i++) {
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x40 | regNo); /* write in regNo */
|
||||
spi_write (data);
|
||||
|
||||
enc_disable ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x1f); /* write reg 0x1f */
|
||||
|
||||
enc_disable ();
|
||||
|
||||
spi_unlock (); /* we must unlock spi first */
|
||||
|
||||
readback = encReadReg (regNo);
|
||||
|
||||
spi_lock ();
|
||||
|
||||
if (readback == data)
|
||||
break;
|
||||
}
|
||||
spi_unlock ();
|
||||
|
||||
if (i == c) {
|
||||
printf ("enc28j60: write reg %d failed\n", regNo);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned char encReadReg (unsigned char regNo)
|
||||
{
|
||||
unsigned char rxByte;
|
||||
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x1f); /* read reg 0x1f */
|
||||
|
||||
bank = spi_read () & 0x3;
|
||||
|
||||
enc_disable ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (regNo);
|
||||
rxByte = spi_read ();
|
||||
|
||||
/* check if MAC or MII register */
|
||||
if (((bank == 2) && (regNo <= 0x1a)) ||
|
||||
((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
|
||||
/* ignore first byte and read another byte */
|
||||
rxByte = spi_read ();
|
||||
}
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
|
||||
return rxByte;
|
||||
}
|
||||
|
||||
static void encReadBuff (unsigned short length, unsigned char *pBuff)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x20 | 0x1a); /* read buffer memory */
|
||||
|
||||
while (length--) {
|
||||
if (pBuff != NULL)
|
||||
*pBuff++ = spi_read ();
|
||||
else
|
||||
spi_write (0);
|
||||
}
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
}
|
||||
|
||||
static void encWriteBuff (unsigned short length, unsigned char *pBuff)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x60 | 0x1a); /* write buffer memory */
|
||||
|
||||
spi_write (0x00); /* control byte */
|
||||
|
||||
while (length--)
|
||||
spi_write (*pBuff++);
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
}
|
||||
|
||||
static void encBitSet (unsigned char regNo, unsigned char data)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0x80 | regNo); /* bit field set */
|
||||
spi_write (data);
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
}
|
||||
|
||||
static void encBitClr (unsigned char regNo, unsigned char data)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0xA0 | regNo); /* bit field clear */
|
||||
spi_write (data);
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
}
|
||||
|
||||
static void encReset (void)
|
||||
{
|
||||
spi_lock ();
|
||||
enc_cfg_spi ();
|
||||
enc_enable ();
|
||||
|
||||
spi_write (0xff); /* soft reset */
|
||||
|
||||
enc_disable ();
|
||||
spi_unlock ();
|
||||
|
||||
/* sleep 1 ms. See errata pt. 2 */
|
||||
udelay (1000);
|
||||
}
|
||||
|
||||
static void encInit (unsigned char *pEthAddr)
|
||||
{
|
||||
unsigned short phid1 = 0;
|
||||
unsigned short phid2 = 0;
|
||||
|
||||
/* switch to bank 0 */
|
||||
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||
|
||||
/*
|
||||
* Setup the buffer space. The reset values are valid for the
|
||||
* other pointers.
|
||||
*/
|
||||
/* We shall not write to ERXST, see errata pt. 5. Instead we
|
||||
have to make sure that ENC_RX_BUS_START is 0. */
|
||||
m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
|
||||
m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
|
||||
|
||||
/* taken from the Linux driver */
|
||||
m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1);
|
||||
m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1);
|
||||
|
||||
m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
|
||||
m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
|
||||
|
||||
next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
|
||||
next_pointer_msb = (ENC_RX_BUF_START >> 8);
|
||||
|
||||
/* verify identification */
|
||||
phid1 = phyRead (PHY_REG_PHID1);
|
||||
phid2 = phyRead (PHY_REG_PHID2);
|
||||
|
||||
if (phid1 != ENC_PHID1_VALUE
|
||||
|| (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
|
||||
printf ("ERROR: failed to identify controller\n");
|
||||
printf ("phid1 = %x, phid2 = %x\n",
|
||||
phid1, (phid2 & ENC_PHID2_MASK));
|
||||
printf ("should be phid1 = %x, phid2 = %x\n",
|
||||
ENC_PHID1_VALUE, ENC_PHID2_VALUE);
|
||||
}
|
||||
|
||||
/*
|
||||
* --- MAC Initialization ---
|
||||
*/
|
||||
|
||||
/* Pull MAC out of Reset */
|
||||
|
||||
/* switch to bank 2 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* enable MAC to receive frames */
|
||||
/* added some bits from the Linux driver */
|
||||
m_nic_write_retry (CTL_REG_MACON1, (ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS), 10);
|
||||
|
||||
/* configure pad, tx-crc and duplex */
|
||||
/* added a bit from the Linux driver */
|
||||
m_nic_write_retry (CTL_REG_MACON3,
|
||||
(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN),
|
||||
10);
|
||||
|
||||
/* added 4 new lines from the Linux driver */
|
||||
/* Allow infinite deferals if the medium is continously busy */
|
||||
m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10);
|
||||
|
||||
/* Late collisions occur beyond 63 bytes */
|
||||
m_nic_write_retry(CTL_REG_MACLCON2, 63, 10);
|
||||
|
||||
/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
|
||||
m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10);
|
||||
|
||||
/*
|
||||
* Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
|
||||
* 0x0c for half-duplex. Nothing for full-duplex
|
||||
*/
|
||||
m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10);
|
||||
|
||||
/* set maximum frame length */
|
||||
m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
|
||||
m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
|
||||
|
||||
/*
|
||||
* Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
|
||||
* and 0x15 for full duplex.
|
||||
*/
|
||||
m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
|
||||
|
||||
/* set MAC address */
|
||||
|
||||
/* switch to bank 3 */
|
||||
m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
|
||||
|
||||
m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
|
||||
|
||||
/*
|
||||
* PHY Initialization taken from the Linux driver
|
||||
*/
|
||||
|
||||
/* Prevent automatic loopback of data beeing transmitted by setting
|
||||
ENC_PHCON2_HDLDIS */
|
||||
phyWrite(PHY_REG_PHCON2, (1<<8));
|
||||
|
||||
/* LEDs configuration
|
||||
* LEDA: LACFG = 0100 -> display link status
|
||||
* LEDB: LBCFG = 0111 -> display TX & RX activity
|
||||
* STRCH = 1 -> LED pulses
|
||||
*/
|
||||
phyWrite(PHY_REG_PHLCON, 0x0472);
|
||||
|
||||
/* Reset PDPXMD-bit => half duplex */
|
||||
phyWrite(PHY_REG_PHCON1, 0);
|
||||
|
||||
/*
|
||||
* Receive settings
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* enable interrupts */
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Description:
|
||||
* Read PHY registers.
|
||||
*
|
||||
* NOTE! This function will change to Bank 2.
|
||||
*
|
||||
* Params:
|
||||
* [in] addr address of the register to read
|
||||
*
|
||||
* Returns:
|
||||
* The value in the register
|
||||
*/
|
||||
static unsigned short phyRead (unsigned char addr)
|
||||
{
|
||||
unsigned short ret = 0;
|
||||
|
||||
/* move to bank 2 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* write address to MIREGADR */
|
||||
m_nic_write (CTL_REG_MIREGADR, addr);
|
||||
|
||||
/* set MICMD.MIIRD */
|
||||
m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
|
||||
|
||||
/* taken from the Linux driver */
|
||||
/* move to bank 3 */
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* poll MISTAT.BUSY bit until operation is complete */
|
||||
while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
|
||||
static int cnt = 0;
|
||||
|
||||
if (cnt++ >= 1000) {
|
||||
/* GJ - this seems extremely dangerous! */
|
||||
/* printf("#"); */
|
||||
cnt = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* taken from the Linux driver */
|
||||
/* move to bank 2 */
|
||||
m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* clear MICMD.MIIRD */
|
||||
m_nic_write (CTL_REG_MICMD, 0);
|
||||
|
||||
ret = (m_nic_read (CTL_REG_MIRDH) << 8);
|
||||
ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Taken from the Linux driver.
|
||||
* Description:
|
||||
* Write PHY registers.
|
||||
*
|
||||
* NOTE! This function will change to Bank 3.
|
||||
*
|
||||
* Params:
|
||||
* [in] addr address of the register to write to
|
||||
* [in] data to be written
|
||||
*
|
||||
* Returns:
|
||||
* None
|
||||
*/
|
||||
static void phyWrite(unsigned char addr, unsigned short data)
|
||||
{
|
||||
/* move to bank 2 */
|
||||
m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* write address to MIREGADR */
|
||||
m_nic_write(CTL_REG_MIREGADR, addr);
|
||||
|
||||
m_nic_write(CTL_REG_MIWRL, data & 0xff);
|
||||
m_nic_write(CTL_REG_MIWRH, data >> 8);
|
||||
|
||||
/* move to bank 3 */
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* poll MISTAT.BUSY bit until operation is complete */
|
||||
while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
|
||||
static int cnt = 0;
|
||||
|
||||
if(cnt++ >= 1000) {
|
||||
cnt = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ENC28J60 */
|
||||
33
include/asm-arm/arch-lpc2292/hardware.h
Normal file
33
include/asm-arm/arch-lpc2292/hardware.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
/*
|
||||
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
|
||||
* Curt Brune <curt@cucy.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_LPC2292)
|
||||
#include <asm-arm/arch-lpc2292/lpc2292_registers.h>
|
||||
#else
|
||||
#error No hardware file defined for this configuration
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */
|
||||
225
include/asm-arm/arch-lpc2292/lpc2292_registers.h
Normal file
225
include/asm-arm/arch-lpc2292/lpc2292_registers.h
Normal file
|
|
@ -0,0 +1,225 @@
|
|||
#ifndef __LPC2292_REGISTERS_H
|
||||
#define __LPC2292_REGISTERS_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* Macros for reading/writing registers */
|
||||
#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
|
||||
#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
|
||||
#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
|
||||
#define GET8(reg) (*(volatile unsigned char*)(reg))
|
||||
#define GET16(reg) (*(volatile unsigned short*)(reg))
|
||||
#define GET32(reg) (*(volatile unsigned int*)(reg))
|
||||
|
||||
/* External Memory Controller */
|
||||
|
||||
#define BCFG0 0xFFE00000 /* 32-bits */
|
||||
#define BCFG1 0xFFE00004 /* 32-bits */
|
||||
#define BCFG2 0xFFE00008 /* 32-bits */
|
||||
#define BCFG3 0xFFE0000c /* 32-bits */
|
||||
|
||||
/* System Control Block */
|
||||
|
||||
#define EXTINT 0xE01FC140
|
||||
#define EXTWAKE 0xE01FC144
|
||||
#define EXTMODE 0xE01FC148
|
||||
#define EXTPOLAR 0xE01FC14C
|
||||
#define MEMMAP 0xE01FC040
|
||||
#define PLLCON 0xE01FC080
|
||||
#define PLLCFG 0xE01FC084
|
||||
#define PLLSTAT 0xE01FC088
|
||||
#define PLLFEED 0xE01FC08C
|
||||
#define PCON 0xE01FC0C0
|
||||
#define PCONP 0xE01FC0C4
|
||||
#define VPBDIV 0xE01FC100
|
||||
|
||||
/* Memory Acceleration Module */
|
||||
|
||||
#define MAMCR 0xE01FC000
|
||||
#define MAMTIM 0xE01FC004
|
||||
|
||||
/* Vectored Interrupt Controller */
|
||||
|
||||
#define VICIRQStatus 0xFFFFF000
|
||||
#define VICFIQStatus 0xFFFFF004
|
||||
#define VICRawIntr 0xFFFFF008
|
||||
#define VICIntSelect 0xFFFFF00C
|
||||
#define VICIntEnable 0xFFFFF010
|
||||
#define VICIntEnClr 0xFFFFF014
|
||||
#define VICSoftInt 0xFFFFF018
|
||||
#define VICSoftIntClear 0xFFFFF01C
|
||||
#define VICProtection 0xFFFFF020
|
||||
#define VICVectAddr 0xFFFFF030
|
||||
#define VICDefVectAddr 0xFFFFF034
|
||||
#define VICVectAddr0 0xFFFFF100
|
||||
#define VICVectAddr1 0xFFFFF104
|
||||
#define VICVectAddr2 0xFFFFF108
|
||||
#define VICVectAddr3 0xFFFFF10C
|
||||
#define VICVectAddr4 0xFFFFF110
|
||||
#define VICVectAddr5 0xFFFFF114
|
||||
#define VICVectAddr6 0xFFFFF118
|
||||
#define VICVectAddr7 0xFFFFF11C
|
||||
#define VICVectAddr8 0xFFFFF120
|
||||
#define VICVectAddr9 0xFFFFF124
|
||||
#define VICVectAddr10 0xFFFFF128
|
||||
#define VICVectAddr11 0xFFFFF12C
|
||||
#define VICVectAddr12 0xFFFFF130
|
||||
#define VICVectAddr13 0xFFFFF134
|
||||
#define VICVectAddr14 0xFFFFF138
|
||||
#define VICVectAddr15 0xFFFFF13C
|
||||
#define VICVectCntl0 0xFFFFF200
|
||||
#define VICVectCntl1 0xFFFFF204
|
||||
#define VICVectCntl2 0xFFFFF208
|
||||
#define VICVectCntl3 0xFFFFF20C
|
||||
#define VICVectCntl4 0xFFFFF210
|
||||
#define VICVectCntl5 0xFFFFF214
|
||||
#define VICVectCntl6 0xFFFFF218
|
||||
#define VICVectCntl7 0xFFFFF21C
|
||||
#define VICVectCntl8 0xFFFFF220
|
||||
#define VICVectCntl9 0xFFFFF224
|
||||
#define VICVectCntl10 0xFFFFF228
|
||||
#define VICVectCntl11 0xFFFFF22C
|
||||
#define VICVectCntl12 0xFFFFF230
|
||||
#define VICVectCntl13 0xFFFFF234
|
||||
#define VICVectCntl14 0xFFFFF238
|
||||
#define VICVectCntl15 0xFFFFF23C
|
||||
|
||||
/* Pin connect block */
|
||||
|
||||
#define PINSEL0 0xE002C000 /* 32 bits */
|
||||
#define PINSEL1 0xE002C004 /* 32 bits */
|
||||
#define PINSEL2 0xE002C014 /* 32 bits */
|
||||
|
||||
/* GPIO */
|
||||
|
||||
#define IO0PIN 0xE0028000
|
||||
#define IO0SET 0xE0028004
|
||||
#define IO0DIR 0xE0028008
|
||||
#define IO0CLR 0xE002800C
|
||||
#define IO1PIN 0xE0028010
|
||||
#define IO1SET 0xE0028014
|
||||
#define IO1DIR 0xE0028018
|
||||
#define IO1CLR 0xE002801C
|
||||
#define IO2PIN 0xE0028020
|
||||
#define IO2SET 0xE0028024
|
||||
#define IO2DIR 0xE0028028
|
||||
#define IO2CLR 0xE002802C
|
||||
#define IO3PIN 0xE0028030
|
||||
#define IO3SET 0xE0028034
|
||||
#define IO3DIR 0xE0028038
|
||||
#define IO3CLR 0xE002803C
|
||||
|
||||
/* Uarts */
|
||||
|
||||
#define U0RBR 0xE000C000
|
||||
#define U0THR 0xE000C000
|
||||
#define U0IER 0xE000C004
|
||||
#define U0IIR 0xE000C008
|
||||
#define U0FCR 0xE000C008
|
||||
#define U0LCR 0xE000C00C
|
||||
#define U0LSR 0xE000C014
|
||||
#define U0SCR 0xE000C01C
|
||||
#define U0DLL 0xE000C000
|
||||
#define U0DLM 0xE000C004
|
||||
|
||||
#define U1RBR 0xE0010000
|
||||
#define U1THR 0xE0010000
|
||||
#define U1IER 0xE0010004
|
||||
#define U1IIR 0xE0010008
|
||||
#define U1FCR 0xE0010008
|
||||
#define U1LCR 0xE001000C
|
||||
#define U1MCR 0xE0010010
|
||||
#define U1LSR 0xE0010014
|
||||
#define U1MSR 0xE0010018
|
||||
#define U1SCR 0xE001001C
|
||||
#define U1DLL 0xE0010000
|
||||
#define U1DLM 0xE0010004
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define I2CONSET 0xE001C000
|
||||
#define I2STAT 0xE001C004
|
||||
#define I2DAT 0xE001C008
|
||||
#define I2ADR 0xE001C00C
|
||||
#define I2SCLH 0xE001C010
|
||||
#define I2SCLL 0xE001C014
|
||||
#define I2CONCLR 0xE001C018
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define S0SPCR 0xE0020000
|
||||
#define S0SPSR 0xE0020004
|
||||
#define S0SPDR 0xE0020008
|
||||
#define S0SPCCR 0xE002000C
|
||||
#define S0SPINT 0xE002001C
|
||||
|
||||
#define S1SPCR 0xE0030000
|
||||
#define S1SPSR 0xE0030004
|
||||
#define S1SPDR 0xE0030008
|
||||
#define S1SPCCR 0xE003000C
|
||||
#define S1SPINT 0xE003001C
|
||||
|
||||
/* CAN controller */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* Timers */
|
||||
|
||||
#define T0IR 0xE0004000
|
||||
#define T0TCR 0xE0004004
|
||||
#define T0TC 0xE0004008
|
||||
#define T0PR 0xE000400C
|
||||
#define T0PC 0xE0004010
|
||||
#define T0MCR 0xE0004014
|
||||
#define T0MR0 0xE0004018
|
||||
#define T0MR1 0xE000401C
|
||||
#define T0MR2 0xE0004020
|
||||
#define T0MR3 0xE0004024
|
||||
#define T0CCR 0xE0004028
|
||||
#define T0CR0 0xE000402C
|
||||
#define T0CR1 0xE0004030
|
||||
#define T0CR2 0xE0004034
|
||||
#define T0CR3 0xE0004038
|
||||
#define T0EMR 0xE000403C
|
||||
|
||||
#define T1IR 0xE0008000
|
||||
#define T1TCR 0xE0008004
|
||||
#define T1TC 0xE0008008
|
||||
#define T1PR 0xE000800C
|
||||
#define T1PC 0xE0008010
|
||||
#define T1MCR 0xE0008014
|
||||
#define T1MR0 0xE0008018
|
||||
#define T1MR1 0xE000801C
|
||||
#define T1MR2 0xE0008020
|
||||
#define T1MR3 0xE0008024
|
||||
#define T1CCR 0xE0008028
|
||||
#define T1CR0 0xE000802C
|
||||
#define T1CR1 0xE0008030
|
||||
#define T1CR2 0xE0008034
|
||||
#define T1CR3 0xE0008038
|
||||
#define T1EMR 0xE000803C
|
||||
|
||||
/* PWM */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* A/D converter */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* Real Time Clock */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
/* Watchdog */
|
||||
|
||||
#define WDMOD 0xE0000000
|
||||
#define WDTC 0xE0000004
|
||||
#define WDFEED 0xE0000008
|
||||
#define WDTV 0xE000000C
|
||||
|
||||
/* EmbeddedICE LOGIC */
|
||||
|
||||
/* skip for now */
|
||||
|
||||
#endif
|
||||
22
include/asm-arm/arch-lpc2292/mmc.h
Normal file
22
include/asm-arm/arch-lpc2292/mmc.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* A dummy header file for use with the LPC2292 port to keep the
|
||||
* compiler happy.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MMC_ARM_TDM_H_
|
||||
#define _MMC_ARM_TDM_H_
|
||||
#endif /* _MMC_ARM_TDM_H_ */
|
||||
82
include/asm-arm/arch-lpc2292/spi.h
Normal file
82
include/asm-arm/arch-lpc2292/spi.h
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
This file defines the interface to the lpc22xx SPI module.
|
||||
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
|
||||
|
||||
This file may be included in software not adhering to the GPL.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef SPI_H
|
||||
#define SPI_H
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#define SPIF 0x80
|
||||
|
||||
#define spi_lock() disable_interrupts();
|
||||
#define spi_unlock() enable_interrupts();
|
||||
|
||||
extern unsigned long spi_flags;
|
||||
extern unsigned char spi_idle;
|
||||
|
||||
int spi_init(void);
|
||||
|
||||
static inline unsigned char spi_read(void)
|
||||
{
|
||||
unsigned char b;
|
||||
|
||||
PUT8(S0SPDR, spi_idle);
|
||||
while (!(GET8(S0SPSR) & SPIF));
|
||||
b = GET8(S0SPDR);
|
||||
|
||||
return b;
|
||||
}
|
||||
|
||||
static inline void spi_write(unsigned char b)
|
||||
{
|
||||
PUT8(S0SPDR, b);
|
||||
while (!(GET8(S0SPSR) & SPIF));
|
||||
GET8(S0SPDR); /* this will clear the SPIF bit */
|
||||
}
|
||||
|
||||
static inline void spi_set_clock(unsigned char clk_value)
|
||||
{
|
||||
PUT8(S0SPCCR, clk_value);
|
||||
}
|
||||
|
||||
static inline void spi_set_cfg(unsigned char phase,
|
||||
unsigned char polarity,
|
||||
unsigned char lsbf)
|
||||
{
|
||||
unsigned char v = 0x20; /* master bit set */
|
||||
|
||||
if (phase)
|
||||
v |= 0x08; /* set phase bit */
|
||||
if (polarity) {
|
||||
v |= 0x10; /* set polarity bit */
|
||||
spi_idle = 0xFF;
|
||||
} else {
|
||||
spi_idle = 0x00;
|
||||
}
|
||||
if (lsbf)
|
||||
v |= 0x40; /* set lsbf bit */
|
||||
|
||||
PUT8(S0SPCR, v);
|
||||
}
|
||||
#endif /* SPI_H */
|
||||
198
include/configs/SMN42.h
Normal file
198
include/configs/SMN42.h
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Configuation settings for the SMN42 board from Siemens.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start u-boot from ram
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#undef CONFIG_INIT_CRITICAL /* undef for developing */
|
||||
|
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
|
||||
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
|
||||
#define CONFIG_LPC2292
|
||||
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
|
||||
|
||||
#undef CONFIG_USE_IRQ /* don't need them anymore */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
/* this would be 0xAE if E0, E1 and E2 were pulled high */
|
||||
#define CFG_I2C_SLAVE 0xA0
|
||||
#define CFG_I2C_EEPROM_ADDR (0xA0 >> 1)
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
/* not used but required by devices.c */
|
||||
#define CFG_I2C_SPEED 10000
|
||||
|
||||
#ifdef CONFIG_SOFT_I2C
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define SCL 0x00000004 /* P0.2 */
|
||||
#define SDA 0x00000008 /* P0.3 */
|
||||
|
||||
#define I2C_READ ((GET32(IO0PIN) & SDA) ? 1 : 0)
|
||||
#define I2C_SDA(x) { if (x) PUT32(IO0SET, SDA); else PUT32(IO0CLR, SDA); }
|
||||
#define I2C_SCL(x) { if (x) PUT32(IO0SET, SCL); else PUT32(IO0CLR, SCL); }
|
||||
#define I2C_DELAY { udelay(100); }
|
||||
#define I2C_ACTIVE { unsigned int i2ctmp; \
|
||||
i2ctmp = GET32(IO0DIR); \
|
||||
i2ctmp |= SDA; \
|
||||
PUT32(IO0DIR, i2ctmp); }
|
||||
#define I2C_TRISTATE { unsigned int i2ctmp; \
|
||||
i2ctmp = GET32(IO0DIR); \
|
||||
i2ctmp &= ~SDA; \
|
||||
PUT32(IO0DIR, i2ctmp); }
|
||||
#endif /* CONFIG_SOFT_I2C */
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_MMC | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_PING)
|
||||
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "SMN42 # " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x81800000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x83000000 /* 24 MB in SRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x81000000 /* default load address for uClinux img is here*/
|
||||
|
||||
#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
|
||||
#define CFG_HZ 2048 /* decrementer freq in Hz */
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SRAM */
|
||||
#define PHYS_SDRAM_1 0x81000000 /* SRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB SRAM */
|
||||
|
||||
/* This is the external flash */
|
||||
#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
/*
|
||||
* The first entry in CFG_FLASH_BANKS_LIST is a dummy, but it must be present.
|
||||
*/
|
||||
#define CFG_FLASH_BANKS_LIST { 0, PHYS_FLASH_1 }
|
||||
#define CFG_FLASH_ADDR0 0x555
|
||||
#define CFG_FLASH_ADDR1 0x2AA
|
||||
#define CFG_FLASH_ERASE_TOUT 16384 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
/* The Environment Sector is in the CPU-internal flash */
|
||||
#define CFG_FLASH_BASE 0
|
||||
#define CFG_ENV_OFFSET 0x3C000
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_MMC 1
|
||||
/* we use this ethernet chip */
|
||||
#define CONFIG_ENC28J60
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue