davinci: da850evm/omapl138-lcdk: Move BSS to SDRAM because SRAM is full

In order to fully support SPL_OF_CONTROL, we need BSS to be a bit
larger. This patch relocates BSS to SDRAM instead of SRAM which
is similar to how ARMv7 boards (like OMAP2+) do it.

This means two new variables are required:
CONFIG_SPL_BSS_START_ADDR  set to DAVINCI_DDR_EMIF_DATA_BASE
CONFIG_SPL_BSS_MAX_SIZE is set to 0x1080000 which is 1 byte
before the location where U-Boot will load.

Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
Adam Ford 2019-02-25 21:53:46 -06:00 committed by Tom Rini
parent 4512380420
commit 15b8c75058
3 changed files with 18 additions and 9 deletions

View file

@ -10,6 +10,9 @@
MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\ MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_FOOTPRINT } LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
ENTRY(_start) ENTRY(_start)
@ -42,6 +45,15 @@ SECTIONS
__rel_dyn_end = .; __rel_dyn_end = .;
} >.sram } >.sram
__image_copy_end = .;
.end :
{
*(.__end)
}
_image_binary_end = .;
.bss : .bss :
{ {
. = ALIGN(4); . = ALIGN(4);
@ -49,12 +61,5 @@ SECTIONS
*(.bss*) *(.bss*)
. = ALIGN(4); . = ALIGN(4);
__bss_end = .; __bss_end = .;
} >.sram } >.sdram
__image_copy_end = .;
.end :
{
*(.__end)
}
} }

View file

@ -48,7 +48,8 @@
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
/* memtest start addr */ /* memtest start addr */
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)

View file

@ -43,6 +43,9 @@
#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
/* memtest start addr */ /* memtest start addr */
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)