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davinci: da850evm/omapl138-lcdk: Move BSS to SDRAM because SRAM is full
In order to fully support SPL_OF_CONTROL, we need BSS to be a bit larger. This patch relocates BSS to SDRAM instead of SRAM which is similar to how ARMv7 boards (like OMAP2+) do it. This means two new variables are required: CONFIG_SPL_BSS_START_ADDR set to DAVINCI_DDR_EMIF_DATA_BASE CONFIG_SPL_BSS_MAX_SIZE is set to 0x1080000 which is 1 byte before the location where U-Boot will load. Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
parent
4512380420
commit
15b8c75058
3 changed files with 18 additions and 9 deletions
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@ -10,6 +10,9 @@
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MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
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MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
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LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
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LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
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MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
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LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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ENTRY(_start)
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@ -42,6 +45,15 @@ SECTIONS
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__rel_dyn_end = .;
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__rel_dyn_end = .;
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} >.sram
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} >.sram
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__image_copy_end = .;
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.end :
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{
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*(.__end)
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}
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_image_binary_end = .;
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.bss :
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.bss :
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{
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{
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. = ALIGN(4);
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. = ALIGN(4);
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@ -49,12 +61,5 @@ SECTIONS
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*(.bss*)
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*(.bss*)
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. = ALIGN(4);
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. = ALIGN(4);
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__bss_end = .;
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__bss_end = .;
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} >.sram
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} >.sdram
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__image_copy_end = .;
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.end :
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{
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*(.__end)
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}
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}
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}
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@ -48,7 +48,8 @@
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
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#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
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#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
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#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
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/* memtest start addr */
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/* memtest start addr */
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
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@ -43,6 +43,9 @@
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
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#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
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/* memtest start addr */
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/* memtest start addr */
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
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