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MIPS: start{, 64}.S: fill branch delay slots with NOP instructions

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The romReserved and romExcHandle handlers are
accessed by a branch instruction however the
delay slots of those instructions are not filled.

Because the start.S uses the 'noreorder' directive,
the assembler will not fill the delay slots either,
and leads to the following assembly code:

  0000056c <romReserved>:
   56c:   1000ffff        b       56c <romReserved>

  00000570 <romExcHandle>:
   570:   1000ffff        b       570 <romExcHandle>

In the resulting code, the second branch instruction
is placed into the delay slot of the first branch
instruction, which is not allowed on the MIPS
architecture.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
This commit is contained in:
Gabor Juhos 2013-01-16 03:05:01 +00:00 committed by Daniel Schwierzeck
parent 0ef48d4c89
commit 14fdd1a8bf
2 changed files with 3 additions and 0 deletions
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2
arch/mips/cpu/mips32/start.S
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@ -380,6 +380,8 @@ in_ram:
/* Exception handlers */ /* Exception handlers */
romReserved: romReserved:
b romReserved b romReserved
nop
romExcHandle: romExcHandle:
b romExcHandle b romExcHandle
nop

1
arch/mips/cpu/mips64/start.S
View file

@ -259,3 +259,4 @@ in_ram:
/* Exception handlers */ /* Exception handlers */
romReserved: romReserved:
b romReserved b romReserved
nop