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mmc: zynq_sdhci: Add support for eMMC5.1 for Versal NET platform
Add support for eMMC 5.1 for Versal NET platform - Add new compatible string(xlnx,versal-net-5.1-emmc). - Add CONFIG_ARCH_VERSAL_NET condition wherever required. - Add DLL and Delay Chain mode support - Add input and output tap delays for eMMC. - Add Strobe select tap for HS400 mode. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
This commit is contained in:
Ashok Reddy Soma
Jaehoon Chung
parent
cf1f7355ae
commit
14ef4c7be5
1 changed files with 284 additions and 3 deletions
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013 - 2015 Xilinx, Inc.
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* (C) Copyright 2013 - 2022, Xilinx, Inc.
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* (C) Copyright 2022, Advanced Micro Devices, Inc.
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*
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* Xilinx Zynq SD Host Controller Interface
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*/
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@ -16,6 +17,7 @@
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#include <dm/device_compat.h>
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#include <linux/err.h>
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#include <linux/libfdt.h>
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#include <linux/iopoll.h>
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#include <asm/types.h>
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#include <linux/math64.h>
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#include <asm/cache.h>
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@ -48,6 +50,41 @@
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#define SD0_OTAPDLYSEL_MASK GENMASK(5, 0)
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#define SD1_OTAPDLYSEL_MASK GENMASK(21, 16)
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#define MIN_PHY_CLK_HZ 50000000
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#define PHY_CTRL_REG1 0x270
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#define PHY_CTRL_ITAPDLY_ENA_MASK BIT(0)
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#define PHY_CTRL_ITAPDLY_SEL_MASK GENMASK(5, 1)
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#define PHY_CTRL_ITAPDLY_SEL_SHIFT 1
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#define PHY_CTRL_ITAP_CHG_WIN_MASK BIT(6)
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#define PHY_CTRL_OTAPDLY_ENA_MASK BIT(8)
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#define PHY_CTRL_OTAPDLY_SEL_MASK GENMASK(15, 12)
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#define PHY_CTRL_OTAPDLY_SEL_SHIFT 12
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#define PHY_CTRL_STRB_SEL_MASK GENMASK(23, 16)
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#define PHY_CTRL_STRB_SEL_SHIFT 16
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#define PHY_CTRL_TEST_CTRL_MASK GENMASK(31, 24)
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#define PHY_CTRL_REG2 0x274
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#define PHY_CTRL_EN_DLL_MASK BIT(0)
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#define PHY_CTRL_DLL_RDY_MASK BIT(1)
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#define PHY_CTRL_FREQ_SEL_MASK GENMASK(6, 4)
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#define PHY_CTRL_FREQ_SEL_SHIFT 4
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#define PHY_CTRL_SEL_DLY_TX_MASK BIT(16)
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#define PHY_CTRL_SEL_DLY_RX_MASK BIT(17)
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#define FREQSEL_200M_170M 0x0
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#define FREQSEL_170M_140M 0x1
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#define FREQSEL_140M_110M 0x2
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#define FREQSEL_110M_80M 0x3
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#define FREQSEL_80M_50M 0x4
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#define FREQSEL_275M_250M 0x5
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#define FREQSEL_250M_225M 0x6
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#define FREQSEL_225M_200M 0x7
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#define PHY_DLL_TIMEOUT_MS 100
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#define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN 39
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#define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL 146
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#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0X77
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struct arasan_sdhci_clk_data {
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int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
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int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
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@ -64,6 +101,7 @@ struct arasan_sdhci_priv {
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u32 node_id;
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u8 bank;
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u8 no_1p8;
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bool internal_phy_reg;
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struct reset_ctl_bulk resets;
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};
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@ -84,7 +122,7 @@ __weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
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return 1;
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}
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#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
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#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
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/* Default settings for ZynqMP Clock Phases */
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static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
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0, 183, 54, 0, 0};
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@ -97,6 +135,12 @@ static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
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static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72,
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90, 36, 60, 90, 0};
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/* Default settings for versal-net eMMC Clock Phases */
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static const u32 versal_net_emmc_iclk_phases[] = {0, 0, 0, 0, 0, 0, 0, 0, 39,
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0, 0};
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static const u32 versal_net_emmc_oclk_phases[] = {0, 113, 0, 0, 0, 0, 0, 0,
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113, 79, 45};
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static const u8 mode2timing[] = {
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[MMC_LEGACY] = MMC_TIMING_LEGACY,
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[MMC_HS] = MMC_TIMING_MMC_HS,
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@ -111,6 +155,121 @@ static const u8 mode2timing[] = {
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[MMC_HS_200] = MMC_TIMING_MMC_HS200,
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};
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#if defined(CONFIG_ARCH_VERSAL_NET)
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/**
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* arasan_phy_set_delaychain - Set eMMC delay chain based Input/Output clock
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*
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* @host: Pointer to the sdhci_host structure
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* @enable: Enable or disable Delay chain based Tx and Rx clock
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* Return: None
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*
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* Enable or disable eMMC delay chain based Input and Output clock in
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* PHY_CTRL_REG2
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*/
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static void arasan_phy_set_delaychain(struct sdhci_host *host, bool enable)
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{
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u32 reg;
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reg = sdhci_readw(host, PHY_CTRL_REG2);
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if (enable)
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reg |= PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK;
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else
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reg &= ~(PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK);
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sdhci_writew(host, reg, PHY_CTRL_REG2);
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}
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/**
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* arasan_phy_set_dll - Set eMMC DLL clock
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*
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* @host: Pointer to the sdhci_host structure
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* @enable: Enable or disable DLL clock
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* Return: 0 if success or timeout error
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*
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* Enable or disable eMMC DLL clock in PHY_CTRL_REG2. When DLL enable is
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* set, wait till DLL is locked
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*/
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static int arasan_phy_set_dll(struct sdhci_host *host, bool enable)
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{
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u32 reg;
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reg = sdhci_readw(host, PHY_CTRL_REG2);
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if (enable)
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reg |= PHY_CTRL_EN_DLL_MASK;
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else
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reg &= ~PHY_CTRL_EN_DLL_MASK;
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sdhci_writew(host, reg, PHY_CTRL_REG2);
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/* If DLL is disabled return success */
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if (!enable)
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return 0;
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/* If DLL is enabled wait till DLL loop is locked, which is
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* indicated by dll_rdy bit(bit1) in PHY_CTRL_REG2
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*/
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return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg,
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(reg & PHY_CTRL_DLL_RDY_MASK),
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1000 * PHY_DLL_TIMEOUT_MS);
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}
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/**
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* arasan_phy_dll_set_freq - Select frequency range of DLL for eMMC
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*
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* @host: Pointer to the sdhci_host structure
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* @clock: clock value
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* Return: None
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*
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* Set frequency range bits based on the selected clock for eMMC
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*/
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static void arasan_phy_dll_set_freq(struct sdhci_host *host, int clock)
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{
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u32 reg, freq_sel, freq;
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freq = DIV_ROUND_CLOSEST(clock, 1000000);
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if (freq <= 200 && freq > 170)
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freq_sel = FREQSEL_200M_170M;
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else if (freq <= 170 && freq > 140)
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freq_sel = FREQSEL_170M_140M;
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else if (freq <= 140 && freq > 110)
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freq_sel = FREQSEL_140M_110M;
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else if (freq <= 110 && freq > 80)
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freq_sel = FREQSEL_110M_80M;
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else
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freq_sel = FREQSEL_80M_50M;
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reg = sdhci_readw(host, PHY_CTRL_REG2);
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reg &= ~PHY_CTRL_FREQ_SEL_MASK;
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reg |= (freq_sel << PHY_CTRL_FREQ_SEL_SHIFT);
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sdhci_writew(host, reg, PHY_CTRL_REG2);
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}
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static int arasan_sdhci_config_dll(struct sdhci_host *host, unsigned int clock, bool enable)
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{
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struct mmc *mmc = (struct mmc *)host->mmc;
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struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
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if (enable) {
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if (priv->internal_phy_reg && clock >= MIN_PHY_CLK_HZ && enable)
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arasan_phy_set_dll(host, 1);
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return 0;
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}
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if (priv->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) {
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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arasan_phy_set_dll(host, 0);
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arasan_phy_set_delaychain(host, 0);
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arasan_phy_dll_set_freq(host, clock);
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return 0;
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}
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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arasan_phy_set_delaychain(host, 1);
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return 0;
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}
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#endif
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static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
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{
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int ret;
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@ -585,6 +744,101 @@ static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
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return 0;
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}
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/**
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* sdhci_versal_net_emmc_sdcardclk_set_phase - Set eMMC Output Clock Tap Delays
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*
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* @host: Pointer to the sdhci_host structure.
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* @degrees: The clock phase shift between 0 - 359.
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* Return: 0
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*
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* Set eMMC Output Clock Tap Delays for Output path
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*/
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static int sdhci_versal_net_emmc_sdcardclk_set_phase(struct sdhci_host *host, int degrees)
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{
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struct mmc *mmc = (struct mmc *)host->mmc;
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int timing = mode2timing[mmc->selected_mode];
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u8 tap_delay, tap_max = 0;
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u32 regval;
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switch (timing) {
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_MMC_DDR52:
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tap_max = 16;
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break;
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case MMC_TIMING_MMC_HS200:
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case MMC_TIMING_MMC_HS400:
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/* For 200MHz clock, 32 Taps are available */
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tap_max = 32;
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break;
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default:
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break;
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}
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tap_delay = (degrees * tap_max) / 360;
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/* Set the Clock Phase */
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if (tap_delay) {
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regval = sdhci_readl(host, PHY_CTRL_REG1);
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regval |= PHY_CTRL_OTAPDLY_ENA_MASK;
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sdhci_writel(host, regval, PHY_CTRL_REG1);
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regval &= ~PHY_CTRL_OTAPDLY_SEL_MASK;
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regval |= tap_delay << PHY_CTRL_OTAPDLY_SEL_SHIFT;
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sdhci_writel(host, regval, PHY_CTRL_REG1);
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}
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return 0;
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}
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/**
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* sdhci_versal_net_emmc_sampleclk_set_phase - Set eMMC Input Clock Tap Delays
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*
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* @host: Pointer to the sdhci_host structure.
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* @degrees: The clock phase shift between 0 - 359.
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* Return: 0
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*
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* Set eMMC Input Clock Tap Delays for Input path. If HS400 is selected,
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* set strobe90 and strobe180 in PHY_CTRL_REG1.
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*/
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static int sdhci_versal_net_emmc_sampleclk_set_phase(struct sdhci_host *host, int degrees)
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{
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struct mmc *mmc = (struct mmc *)host->mmc;
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int timing = mode2timing[mmc->selected_mode];
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u8 tap_delay, tap_max = 0;
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u32 regval;
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switch (timing) {
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_MMC_DDR52:
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tap_max = 32;
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break;
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case MMC_TIMING_MMC_HS400:
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/* Strobe select tap point for strb90 and strb180 */
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regval = sdhci_readl(host, PHY_CTRL_REG1);
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regval &= ~PHY_CTRL_STRB_SEL_MASK;
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regval |= VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL << PHY_CTRL_STRB_SEL_SHIFT;
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sdhci_writel(host, regval, PHY_CTRL_REG1);
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break;
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default:
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break;
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}
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tap_delay = (degrees * tap_max) / 360;
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/* Set the Clock Phase */
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if (tap_delay) {
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regval = sdhci_readl(host, PHY_CTRL_REG1);
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regval |= PHY_CTRL_ITAP_CHG_WIN_MASK;
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sdhci_writel(host, regval, PHY_CTRL_REG1);
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regval |= PHY_CTRL_ITAPDLY_ENA_MASK;
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sdhci_writel(host, regval, PHY_CTRL_REG1);
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regval &= ~PHY_CTRL_ITAPDLY_SEL_MASK;
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regval |= tap_delay << PHY_CTRL_ITAPDLY_SEL_SHIFT;
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sdhci_writel(host, regval, PHY_CTRL_REG1);
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regval &= ~PHY_CTRL_ITAP_CHG_WIN_MASK;
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sdhci_writel(host, regval, PHY_CTRL_REG1);
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}
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return 0;
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}
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static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
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{
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struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
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@ -616,6 +870,19 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
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ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
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if (ret)
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return ret;
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} else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
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device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
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if (mmc->clock >= MIN_PHY_CLK_HZ)
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if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
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iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL;
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ret = sdhci_versal_net_emmc_sampleclk_set_phase(host, iclk_phase);
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if (ret)
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return ret;
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ret = sdhci_versal_net_emmc_sdcardclk_set_phase(host, oclk_phase);
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if (ret)
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return ret;
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}
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return 0;
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@ -678,6 +945,14 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev)
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}
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}
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if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
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device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
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for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
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clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i];
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clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i];
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}
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}
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arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
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"clk-phase-legacy");
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arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
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@ -706,6 +981,9 @@ static const struct sdhci_ops arasan_ops = {
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.platform_execute_tuning = &arasan_sdhci_execute_tuning,
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.set_delay = &arasan_sdhci_set_tapdelay,
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.set_control_reg = &sdhci_set_control_reg,
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#if defined(CONFIG_ARCH_VERSAL_NET)
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.config_dll = &arasan_sdhci_config_dll,
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#endif
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};
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#endif
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@ -822,6 +1100,8 @@ static int arasan_sdhci_probe(struct udevice *dev)
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}
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}
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#endif
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if (device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
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priv->internal_phy_reg = true;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0) {
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@ -905,7 +1185,7 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev)
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priv->host->name = dev->name;
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#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
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#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
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priv->host->ops = &arasan_ops;
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arasan_dt_parse_clk_phases(dev);
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#endif
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@ -933,6 +1213,7 @@ static int arasan_sdhci_bind(struct udevice *dev)
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static const struct udevice_id arasan_sdhci_ids[] = {
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{ .compatible = "arasan,sdhci-8.9a" },
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{ .compatible = "xlnx,versal-net-5.1-emmc" },
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{ }
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};
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