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https://github.com/AsahiLinux/u-boot
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phy: cadence: Sierra: Prepare driver to add support for multilink configurations
Sierra driver currently supports single link configurations only. Prepare driver to support multilink multiprotocol configurations along with different SSC modes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
This commit is contained in:
Swapnil Jakhade
Tom Rini
parent
3c1d89ff76
commit
14ed6703be
1 changed files with 135 additions and 53 deletions
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@ -28,6 +28,9 @@
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#include <dt-bindings/phy/phy-cadence.h>
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#include <regmap.h>
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#define NUM_SSC_MODE 3
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#define NUM_PHY_TYPE 3
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/* PHY register offsets */
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#define SIERRA_COMMON_CDB_OFFSET 0x0
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#define SIERRA_MACRO_ID_REG 0x0
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@ -214,8 +217,20 @@ struct cdns_sierra_pll_mux {
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#define reset_control_deassert(rst) cdns_reset_deassert(rst)
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#define reset_control reset_ctl
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enum cdns_sierra_phy_type {
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TYPE_NONE,
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TYPE_PCIE,
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TYPE_USB
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};
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enum cdns_sierra_ssc_mode {
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NO_SSC,
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EXTERNAL_SSC,
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INTERNAL_SSC
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};
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struct cdns_sierra_inst {
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u32 phy_type;
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enum cdns_sierra_phy_type phy_type;
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u32 num_lanes;
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u32 mlane;
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struct reset_ctl_bulk *lnk_rst;
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@ -226,18 +241,19 @@ struct cdns_reg_pairs {
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u32 off;
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};
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struct cdns_sierra_vals {
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const struct cdns_reg_pairs *reg_pairs;
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u32 num_regs;
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};
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struct cdns_sierra_data {
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u32 id_value;
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u8 block_offset_shift;
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u8 reg_offset_shift;
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u32 pcie_cmn_regs;
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u32 pcie_ln_regs;
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u32 usb_cmn_regs;
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u32 usb_ln_regs;
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struct cdns_reg_pairs *pcie_cmn_vals;
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struct cdns_reg_pairs *pcie_ln_vals;
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struct cdns_reg_pairs *usb_cmn_vals;
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struct cdns_reg_pairs *usb_ln_vals;
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struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
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[NUM_SSC_MODE];
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struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
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[NUM_SSC_MODE];
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};
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struct cdns_sierra_phy {
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@ -299,10 +315,14 @@ static int cdns_sierra_phy_init(struct phy *gphy)
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{
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struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
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struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
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struct cdns_sierra_data *init_data = phy->init_data;
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struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
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enum cdns_sierra_phy_type phy_type = ins->phy_type;
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enum cdns_sierra_ssc_mode ssc = EXTERNAL_SSC;
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const struct cdns_reg_pairs *reg_pairs;
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struct regmap *regmap = phy->regmap;
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u32 num_regs;
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int i, j;
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struct cdns_reg_pairs *cmn_vals, *ln_vals;
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u32 num_cmn_regs, num_ln_regs;
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/* Initialise the PHY registers, unless auto configured */
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if (phy->autoconf)
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@ -311,28 +331,25 @@ static int cdns_sierra_phy_init(struct phy *gphy)
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clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
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clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
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if (ins->phy_type == PHY_TYPE_PCIE) {
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num_cmn_regs = phy->init_data->pcie_cmn_regs;
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num_ln_regs = phy->init_data->pcie_ln_regs;
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cmn_vals = phy->init_data->pcie_cmn_vals;
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ln_vals = phy->init_data->pcie_ln_vals;
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} else if (ins->phy_type == PHY_TYPE_USB3) {
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num_cmn_regs = phy->init_data->usb_cmn_regs;
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num_ln_regs = phy->init_data->usb_ln_regs;
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cmn_vals = phy->init_data->usb_cmn_vals;
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ln_vals = phy->init_data->usb_ln_vals;
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} else {
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return -EINVAL;
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/* PMA common registers configurations */
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pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
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if (pma_cmn_vals) {
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reg_pairs = pma_cmn_vals->reg_pairs;
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num_regs = pma_cmn_vals->num_regs;
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regmap = phy->regmap_common_cdb;
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for (i = 0; i < num_regs; i++)
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regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
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}
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regmap = phy->regmap_common_cdb;
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for (j = 0; j < num_cmn_regs ; j++)
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regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val);
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for (i = 0; i < ins->num_lanes; i++) {
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for (j = 0; j < num_ln_regs ; j++) {
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/* PMA TX lane registers configurations */
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pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];
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if (pma_ln_vals) {
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reg_pairs = pma_ln_vals->reg_pairs;
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num_regs = pma_ln_vals->num_regs;
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for (i = 0; i < ins->num_lanes; i++) {
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regmap = phy->regmap_lane_cdb[i + ins->mlane];
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regmap_write(regmap, ln_vals[j].off, ln_vals[j].val);
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for (j = 0; j < num_regs; j++)
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regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
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}
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}
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@ -507,15 +524,28 @@ static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp)
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static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
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ofnode child)
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{
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u32 phy_type;
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if (ofnode_read_u32(child, "reg", &inst->mlane))
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return -EINVAL;
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if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
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return -EINVAL;
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if (ofnode_read_u32(child, "cdns,phy-type", &inst->phy_type))
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if (ofnode_read_u32(child, "cdns,phy-type", &phy_type))
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return -EINVAL;
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switch (phy_type) {
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case PHY_TYPE_PCIE:
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inst->phy_type = TYPE_PCIE;
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break;
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case PHY_TYPE_USB3:
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inst->phy_type = TYPE_USB;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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@ -873,6 +903,16 @@ static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
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{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
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};
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static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {
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.reg_pairs = cdns_pcie_cmn_regs_ext_ssc,
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.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
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};
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static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = {
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.reg_pairs = cdns_pcie_ln_regs_ext_ssc,
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.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
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};
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/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
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static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
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{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
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@ -980,32 +1020,74 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
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{0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
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};
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static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = {
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.reg_pairs = cdns_usb_cmn_regs_ext_ssc,
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.num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
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};
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static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = {
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.reg_pairs = cdns_usb_ln_regs_ext_ssc,
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.num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
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};
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static const struct cdns_sierra_data cdns_map_sierra = {
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SIERRA_MACRO_ID,
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0x2,
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0x2,
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ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
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ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
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ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
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ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
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cdns_pcie_cmn_regs_ext_ssc,
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cdns_pcie_ln_regs_ext_ssc,
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cdns_usb_cmn_regs_ext_ssc,
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cdns_usb_ln_regs_ext_ssc,
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.id_value = SIERRA_MACRO_ID,
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.block_offset_shift = 0x2,
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.reg_offset_shift = 0x2,
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.pma_cmn_vals = {
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[TYPE_PCIE] = {
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[TYPE_NONE] = {
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[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
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},
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},
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[TYPE_USB] = {
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[TYPE_NONE] = {
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[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
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},
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},
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},
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.pma_ln_vals = {
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[TYPE_PCIE] = {
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[TYPE_NONE] = {
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[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
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},
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},
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[TYPE_USB] = {
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[TYPE_NONE] = {
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[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
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},
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},
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},
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};
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static const struct cdns_sierra_data cdns_ti_map_sierra = {
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SIERRA_MACRO_ID,
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0x0,
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0x1,
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ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
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ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
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ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
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ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
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cdns_pcie_cmn_regs_ext_ssc,
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cdns_pcie_ln_regs_ext_ssc,
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cdns_usb_cmn_regs_ext_ssc,
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cdns_usb_ln_regs_ext_ssc,
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.id_value = SIERRA_MACRO_ID,
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.block_offset_shift = 0x0,
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.reg_offset_shift = 0x1,
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.pma_cmn_vals = {
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[TYPE_PCIE] = {
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[TYPE_NONE] = {
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[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
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},
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},
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[TYPE_USB] = {
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[TYPE_NONE] = {
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[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
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},
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},
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},
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.pma_ln_vals = {
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[TYPE_PCIE] = {
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[TYPE_NONE] = {
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[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
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},
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},
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[TYPE_USB] = {
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[TYPE_NONE] = {
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[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
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},
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},
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},
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};
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static const struct udevice_id cdns_sierra_id_table[] = {
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