mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 23:47:24 +00:00
Merge tag 'u-boot-rockchip-20221020' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- dts update and sync for rk356x, rk3288, rk3399 from Linux; - Add rk3399 EAIDK-610 board support; - Update for puma-rk3399 board; - some fix and typo fix in different drivers;
This commit is contained in:
Tom Rini
commit
145a996592
30 changed files with 3639 additions and 1100 deletions
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@ -136,6 +136,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
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dtb-$(CONFIG_ROCKCHIP_RK3399) += \
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dtb-$(CONFIG_ROCKCHIP_RK3399) += \
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rk3399-evb.dtb \
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rk3399-evb.dtb \
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rk3399-eaidk-610.dtb \
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rk3399-ficus.dtb \
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rk3399-ficus.dtb \
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rk3399-firefly.dtb \
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rk3399-firefly.dtb \
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rk3399-gru-bob.dtb \
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rk3399-gru-bob.dtb \
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@ -1,87 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for RK3288 SoC thermal
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*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <dt-bindings/thermal/thermal.h>
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reserve_thermal: reserve_thermal {
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polling-delay-passive = <1000>; /* milliseconds */
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polling-delay = <5000>; /* milliseconds */
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/* sensor ID */
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thermal-sensors = <&tsadc 0>;
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};
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cpu_thermal: cpu_thermal {
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polling-delay-passive = <100>; /* milliseconds */
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polling-delay = <5000>; /* milliseconds */
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/* sensor ID */
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thermal-sensors = <&tsadc 1>;
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linux,hwmon;
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trips {
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cpu_alert0: cpu_alert0 {
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temperature = <70000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert1: cpu_alert1 {
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temperature = <75000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_crit: cpu_crit {
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temperature = <100000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT 6>;
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};
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map1 {
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trip = <&cpu_alert1>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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gpu_thermal: gpu_thermal {
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polling-delay-passive = <100>; /* milliseconds */
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polling-delay = <5000>; /* milliseconds */
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/* sensor ID */
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thermal-sensors = <&tsadc 2>;
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linux,hwmon;
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trips {
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gpu_alert0: gpu_alert0 {
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temperature = <80000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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gpu_crit: gpu_crit {
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temperature = <100000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&gpu_alert0>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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@ -137,12 +137,6 @@
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};
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};
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};
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};
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edp {
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edp_hpd: edp_hpd {
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rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
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};
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};
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emmc {
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emmc {
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/* Make sure eMMC is not in reset */
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/* Make sure eMMC is not in reset */
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emmc_deassert_reset: emmc-deassert-reset {
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emmc_deassert_reset: emmc-deassert-reset {
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@ -560,10 +560,6 @@
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status = "okay";
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status = "okay";
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};
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};
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&hdmi_audio {
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status = "okay";
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|
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};
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&gpu {
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&gpu {
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status = "okay";
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status = "okay";
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};
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};
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@ -15,6 +15,7 @@
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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aliases {
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aliases {
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ethernet0 = &gmac;
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i2c0 = &i2c0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c2 = &i2c2;
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@ -35,6 +36,15 @@
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spi2 = &spi2;
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spi2 = &spi2;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a12-pmu";
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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cpus {
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cpus {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -45,44 +55,119 @@
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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compatible = "arm,cortex-a12";
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reg = <0x500>;
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reg = <0x500>;
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operating-points = <
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resets = <&cru SRST_CORE0>;
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/* KHz uV */
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operating-points-v2 = <&cpu_opp_table>;
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1800000 1400000
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1704000 1350000
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1608000 1300000
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1512000 1250000
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1416000 1200000
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1200000 1100000
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1008000 1050000
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816000 1000000
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696000 950000
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600000 900000
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408000 900000
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216000 900000
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126000 900000
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>;
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#cooling-cells = <2>; /* min followed by max */
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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clocks = <&cru ARMCLK>;
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resets = <&cru SRST_CORE0>;
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dynamic-power-coefficient = <370>;
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};
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};
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cpu@501 {
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cpu1: cpu@501 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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compatible = "arm,cortex-a12";
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reg = <0x501>;
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reg = <0x501>;
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resets = <&cru SRST_CORE1>;
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resets = <&cru SRST_CORE1>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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dynamic-power-coefficient = <370>;
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};
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};
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cpu@502 {
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cpu2: cpu@502 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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compatible = "arm,cortex-a12";
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reg = <0x502>;
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reg = <0x502>;
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resets = <&cru SRST_CORE2>;
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resets = <&cru SRST_CORE2>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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dynamic-power-coefficient = <370>;
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};
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};
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cpu@503 {
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cpu3: cpu@503 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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compatible = "arm,cortex-a12";
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reg = <0x503>;
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reg = <0x503>;
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resets = <&cru SRST_CORE3>;
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resets = <&cru SRST_CORE3>;
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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dynamic-power-coefficient = <370>;
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};
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};
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cpu_opp_table: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-126000000 {
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opp-hz = /bits/ 64 <126000000>;
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opp-microvolt = <900000>;
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};
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opp-216000000 {
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opp-hz = /bits/ 64 <216000000>;
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opp-microvolt = <900000>;
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};
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opp-312000000 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <900000>;
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};
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <900000>;
|
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|
};
|
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|
opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
|
||||||
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opp-microvolt = <900000>;
|
||||||
|
};
|
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opp-696000000 {
|
||||||
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opp-hz = /bits/ 64 <696000000>;
|
||||||
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opp-microvolt = <950000>;
|
||||||
|
};
|
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opp-816000000 {
|
||||||
|
opp-hz = /bits/ 64 <816000000>;
|
||||||
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opp-microvolt = <1000000>;
|
||||||
|
};
|
||||||
|
opp-1008000000 {
|
||||||
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opp-hz = /bits/ 64 <1008000000>;
|
||||||
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opp-microvolt = <1050000>;
|
||||||
|
};
|
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opp-1200000000 {
|
||||||
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opp-hz = /bits/ 64 <1200000000>;
|
||||||
|
opp-microvolt = <1100000>;
|
||||||
|
};
|
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|
opp-1416000000 {
|
||||||
|
opp-hz = /bits/ 64 <1416000000>;
|
||||||
|
opp-microvolt = <1200000>;
|
||||||
|
};
|
||||||
|
opp-1512000000 {
|
||||||
|
opp-hz = /bits/ 64 <1512000000>;
|
||||||
|
opp-microvolt = <1300000>;
|
||||||
|
};
|
||||||
|
opp-1608000000 {
|
||||||
|
opp-hz = /bits/ 64 <1608000000>;
|
||||||
|
opp-microvolt = <1350000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
reserved-memory {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The rk3288 cannot use the memory area above 0xfe000000
|
||||||
|
* for dma operations for some reason. While there is
|
||||||
|
* probably a better solution available somewhere, we
|
||||||
|
* haven't found it yet and while devices with 2GB of ram
|
||||||
|
* are not affected, this issue prevents 4GB from booting.
|
||||||
|
* So to make these devices at least bootable, block
|
||||||
|
* this area for the time being until the real solution
|
||||||
|
* is found.
|
||||||
|
*/
|
||||||
|
dma-unusable@fe000000 {
|
||||||
|
reg = <0xfe000000 0x1000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -94,14 +179,22 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
timer {
|
timer {
|
||||||
arm,use-physical-timer;
|
|
||||||
compatible = "arm,armv7-timer";
|
compatible = "arm,armv7-timer";
|
||||||
|
arm,cpu-registers-not-fw-configured;
|
||||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||||
clock-frequency = <24000000>;
|
clock-frequency = <24000000>;
|
||||||
always-on;
|
arm,no-tick-in-suspend;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer: timer@ff810000 {
|
||||||
|
compatible = "rockchip,rk3288-timer";
|
||||||
|
reg = <0x0 0xff810000 0x0 0x20>;
|
||||||
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cru PCLK_TIMER>, <&xin24m>;
|
||||||
|
clock-names = "pclk", "timer";
|
||||||
};
|
};
|
||||||
|
|
||||||
display-subsystem {
|
display-subsystem {
|
||||||
|
|
@ -118,6 +211,8 @@
|
||||||
fifo-depth = <0x100>;
|
fifo-depth = <0x100>;
|
||||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
reg = <0xff0c0000 0x4000>;
|
reg = <0xff0c0000 0x4000>;
|
||||||
|
resets = <&cru SRST_MMC0>;
|
||||||
|
reset-names = "reset";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -130,6 +225,8 @@
|
||||||
fifo-depth = <0x100>;
|
fifo-depth = <0x100>;
|
||||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
reg = <0xff0d0000 0x4000>;
|
reg = <0xff0d0000 0x4000>;
|
||||||
|
resets = <&cru SRST_SDIO0>;
|
||||||
|
reset-names = "reset";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -142,6 +239,8 @@
|
||||||
fifo-depth = <0x100>;
|
fifo-depth = <0x100>;
|
||||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
reg = <0xff0e0000 0x4000>;
|
reg = <0xff0e0000 0x4000>;
|
||||||
|
resets = <&cru SRST_SDIO1>;
|
||||||
|
reset-names = "reset";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -154,6 +253,8 @@
|
||||||
fifo-depth = <0x100>;
|
fifo-depth = <0x100>;
|
||||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
reg = <0xff0f0000 0x4000>;
|
reg = <0xff0f0000 0x4000>;
|
||||||
|
resets = <&cru SRST_EMMC>;
|
||||||
|
reset-names = "reset";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -164,6 +265,8 @@
|
||||||
#io-channel-cells = <1>;
|
#io-channel-cells = <1>;
|
||||||
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
|
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
|
||||||
clock-names = "saradc", "apb_pclk";
|
clock-names = "saradc", "apb_pclk";
|
||||||
|
resets = <&cru SRST_SARADC>;
|
||||||
|
reset-names = "saradc-apb";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -263,6 +366,7 @@
|
||||||
pinctrl-0 = <&i2c5_xfer>;
|
pinctrl-0 = <&i2c5_xfer>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
uart0: serial@ff180000 {
|
uart0: serial@ff180000 {
|
||||||
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
|
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
|
||||||
reg = <0xff180000 0x100>;
|
reg = <0xff180000 0x100>;
|
||||||
|
|
@ -271,6 +375,8 @@
|
||||||
reg-io-width = <4>;
|
reg-io-width = <4>;
|
||||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||||
clock-names = "baudclk", "apb_pclk";
|
clock-names = "baudclk", "apb_pclk";
|
||||||
|
dmas = <&dmac_peri 1>, <&dmac_peri 2>;
|
||||||
|
dma-names = "tx", "rx";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&uart0_xfer>;
|
pinctrl-0 = <&uart0_xfer>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -284,6 +390,8 @@
|
||||||
reg-io-width = <4>;
|
reg-io-width = <4>;
|
||||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||||
clock-names = "baudclk", "apb_pclk";
|
clock-names = "baudclk", "apb_pclk";
|
||||||
|
dmas = <&dmac_peri 3>, <&dmac_peri 4>;
|
||||||
|
dma-names = "tx", "rx";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&uart1_xfer>;
|
pinctrl-0 = <&uart1_xfer>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -301,6 +409,7 @@
|
||||||
pinctrl-0 = <&uart2_xfer>;
|
pinctrl-0 = <&uart2_xfer>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
uart3: serial@ff1b0000 {
|
uart3: serial@ff1b0000 {
|
||||||
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
|
compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
|
||||||
reg = <0xff1b0000 0x100>;
|
reg = <0xff1b0000 0x100>;
|
||||||
|
|
@ -309,6 +418,8 @@
|
||||||
reg-io-width = <4>;
|
reg-io-width = <4>;
|
||||||
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
||||||
clock-names = "baudclk", "apb_pclk";
|
clock-names = "baudclk", "apb_pclk";
|
||||||
|
dmas = <&dmac_peri 7>, <&dmac_peri 8>;
|
||||||
|
dma-names = "tx", "rx";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&uart3_xfer>;
|
pinctrl-0 = <&uart3_xfer>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -322,6 +433,8 @@
|
||||||
reg-io-width = <4>;
|
reg-io-width = <4>;
|
||||||
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
||||||
clock-names = "baudclk", "apb_pclk";
|
clock-names = "baudclk", "apb_pclk";
|
||||||
|
dmas = <&dmac_peri 9>, <&dmac_peri 10>;
|
||||||
|
dma-names = "tx", "rx";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&uart4_xfer>;
|
pinctrl-0 = <&uart4_xfer>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -333,13 +446,91 @@
|
||||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
#dma-cells = <1>;
|
#dma-cells = <1>;
|
||||||
broken-no-flushp;
|
arm,pl330-broken-no-flushp;
|
||||||
|
arm,pl330-periph-burst;
|
||||||
clocks = <&cru ACLK_DMAC2>;
|
clocks = <&cru ACLK_DMAC2>;
|
||||||
clock-names = "apb_pclk";
|
clock-names = "apb_pclk";
|
||||||
};
|
};
|
||||||
|
|
||||||
thermal: thermal-zones {
|
thermal: thermal-zones {
|
||||||
#include "rk3288-thermal.dtsi"
|
reserve_thermal: reserve-thermal {
|
||||||
|
polling-delay-passive = <1000>; /* milliseconds */
|
||||||
|
polling-delay = <5000>; /* milliseconds */
|
||||||
|
|
||||||
|
thermal-sensors = <&tsadc 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_thermal: cpu-thermal {
|
||||||
|
polling-delay-passive = <100>; /* milliseconds */
|
||||||
|
polling-delay = <5000>; /* milliseconds */
|
||||||
|
|
||||||
|
thermal-sensors = <&tsadc 1>;
|
||||||
|
|
||||||
|
trips {
|
||||||
|
cpu_alert0: cpu_alert0 {
|
||||||
|
temperature = <70000>; /* millicelsius */
|
||||||
|
hysteresis = <2000>; /* millicelsius */
|
||||||
|
type = "passive";
|
||||||
|
};
|
||||||
|
cpu_alert1: cpu_alert1 {
|
||||||
|
temperature = <75000>; /* millicelsius */
|
||||||
|
hysteresis = <2000>; /* millicelsius */
|
||||||
|
type = "passive";
|
||||||
|
};
|
||||||
|
cpu_crit: cpu_crit {
|
||||||
|
temperature = <90000>; /* millicelsius */
|
||||||
|
hysteresis = <2000>; /* millicelsius */
|
||||||
|
type = "critical";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cooling-maps {
|
||||||
|
map0 {
|
||||||
|
trip = <&cpu_alert0>;
|
||||||
|
cooling-device =
|
||||||
|
<&cpu0 THERMAL_NO_LIMIT 6>,
|
||||||
|
<&cpu1 THERMAL_NO_LIMIT 6>,
|
||||||
|
<&cpu2 THERMAL_NO_LIMIT 6>,
|
||||||
|
<&cpu3 THERMAL_NO_LIMIT 6>;
|
||||||
|
};
|
||||||
|
map1 {
|
||||||
|
trip = <&cpu_alert1>;
|
||||||
|
cooling-device =
|
||||||
|
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||||
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||||
|
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||||
|
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gpu_thermal: gpu-thermal {
|
||||||
|
polling-delay-passive = <100>; /* milliseconds */
|
||||||
|
polling-delay = <5000>; /* milliseconds */
|
||||||
|
|
||||||
|
thermal-sensors = <&tsadc 2>;
|
||||||
|
|
||||||
|
trips {
|
||||||
|
gpu_alert0: gpu_alert0 {
|
||||||
|
temperature = <70000>; /* millicelsius */
|
||||||
|
hysteresis = <2000>; /* millicelsius */
|
||||||
|
type = "passive";
|
||||||
|
};
|
||||||
|
gpu_crit: gpu_crit {
|
||||||
|
temperature = <90000>; /* millicelsius */
|
||||||
|
hysteresis = <2000>; /* millicelsius */
|
||||||
|
type = "critical";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cooling-maps {
|
||||||
|
map0 {
|
||||||
|
trip = <&gpu_alert0>;
|
||||||
|
cooling-device =
|
||||||
|
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
tsadc: tsadc@ff280000 {
|
tsadc: tsadc@ff280000 {
|
||||||
|
|
@ -371,6 +562,8 @@
|
||||||
"mac_clk_rx", "mac_clk_tx",
|
"mac_clk_rx", "mac_clk_tx",
|
||||||
"clk_mac_ref", "clk_mac_refout",
|
"clk_mac_ref", "clk_mac_refout",
|
||||||
"aclk_mac", "pclk_mac";
|
"aclk_mac", "pclk_mac";
|
||||||
|
resets = <&cru SRST_MAC>;
|
||||||
|
reset-names = "stmmaceth";
|
||||||
};
|
};
|
||||||
|
|
||||||
usb_host0_ehci: usb@ff500000 {
|
usb_host0_ehci: usb@ff500000 {
|
||||||
|
|
@ -384,7 +577,7 @@
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
/* NOTE: doesn't work on RK3288, but fixed on RK3288W */
|
/* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
|
||||||
usb_host0_ohci: usb@ff520000 {
|
usb_host0_ohci: usb@ff520000 {
|
||||||
compatible = "generic-ohci";
|
compatible = "generic-ohci";
|
||||||
reg = <0x0 0xff520000 0x0 0x100>;
|
reg = <0x0 0xff520000 0x0 0x100>;
|
||||||
|
|
@ -402,8 +595,10 @@
|
||||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&cru HCLK_USBHOST1>;
|
clocks = <&cru HCLK_USBHOST1>;
|
||||||
clock-names = "otg";
|
clock-names = "otg";
|
||||||
|
dr_mode = "host";
|
||||||
phys = <&usbphy2>;
|
phys = <&usbphy2>;
|
||||||
phy-names = "usb2-phy";
|
phy-names = "usb2-phy";
|
||||||
|
snps,reset-phy-on-wake;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -415,6 +610,9 @@
|
||||||
clocks = <&cru HCLK_OTG0>;
|
clocks = <&cru HCLK_OTG0>;
|
||||||
clock-names = "otg";
|
clock-names = "otg";
|
||||||
dr_mode = "otg";
|
dr_mode = "otg";
|
||||||
|
g-np-tx-fifo-size = <16>;
|
||||||
|
g-rx-fifo-size = <275>;
|
||||||
|
g-tx-fifo-size = <256 128 128 64 64 32>;
|
||||||
phys = <&usbphy0>;
|
phys = <&usbphy0>;
|
||||||
phy-names = "usb2-phy";
|
phy-names = "usb2-phy";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -435,7 +633,8 @@
|
||||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
#dma-cells = <1>;
|
#dma-cells = <1>;
|
||||||
broken-no-flushp;
|
arm,pl330-broken-no-flushp;
|
||||||
|
arm,pl330-periph-burst;
|
||||||
clocks = <&cru ACLK_DMAC1>;
|
clocks = <&cru ACLK_DMAC1>;
|
||||||
clock-names = "apb_pclk";
|
clock-names = "apb_pclk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -515,7 +714,7 @@
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
bus_intmem: bus_intmem@ff700000 {
|
bus_intmem: sram@ff700000 {
|
||||||
compatible = "mmio-sram";
|
compatible = "mmio-sram";
|
||||||
reg = <0xff700000 0x18000>;
|
reg = <0xff700000 0x18000>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -527,7 +726,7 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
sram@ff720000 {
|
pmu_sram: sram@ff720000 {
|
||||||
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
|
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
|
||||||
reg = <0xff720000 0x1000>;
|
reg = <0xff720000 0x1000>;
|
||||||
};
|
};
|
||||||
|
|
@ -569,7 +768,7 @@
|
||||||
compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
|
compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
|
||||||
reg = <0xff800000 0x100>;
|
reg = <0xff800000 0x100>;
|
||||||
clocks = <&cru PCLK_WDT>;
|
clocks = <&cru PCLK_WDT>;
|
||||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -577,11 +776,11 @@
|
||||||
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
|
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
|
||||||
reg = <0xff8b0000 0x10000>;
|
reg = <0xff8b0000 0x10000>;
|
||||||
#sound-dai-cells = <0>;
|
#sound-dai-cells = <0>;
|
||||||
clock-names = "hclk", "mclk";
|
clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
|
||||||
clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
|
clock-names = "mclk", "hclk";
|
||||||
dmas = <&dmac_bus_s 3>;
|
dmas = <&dmac_bus_s 3>;
|
||||||
dma-names = "tx";
|
dma-names = "tx";
|
||||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&spdif_tx>;
|
pinctrl-0 = <&spdif_tx>;
|
||||||
rockchip,grf = <&grf>;
|
rockchip,grf = <&grf>;
|
||||||
|
|
@ -591,50 +790,97 @@
|
||||||
i2s: i2s@ff890000 {
|
i2s: i2s@ff890000 {
|
||||||
compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
|
compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
|
||||||
reg = <0xff890000 0x10000>;
|
reg = <0xff890000 0x10000>;
|
||||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
#sound-dai-cells = <0>;
|
||||||
#address-cells = <1>;
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
#size-cells = <0>;
|
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
|
||||||
#sound-dai-cells = <1>;
|
clock-names = "i2s_clk", "i2s_hclk";
|
||||||
dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
|
dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
|
||||||
dma-names = "tx", "rx";
|
dma-names = "tx", "rx";
|
||||||
clock-names = "i2s_hclk", "i2s_clk";
|
|
||||||
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
|
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&i2s0_bus>;
|
pinctrl-0 = <&i2s0_bus>;
|
||||||
|
rockchip,playback-channels = <8>;
|
||||||
|
rockchip,capture-channels = <2>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
crypto: crypto@ff8a0000 {
|
||||||
|
compatible = "rockchip,rk3288-crypto";
|
||||||
|
reg = <0xff8a0000 0x4000>;
|
||||||
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
|
||||||
|
<&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
|
||||||
|
clock-names = "aclk", "hclk", "sclk", "apb_pclk";
|
||||||
|
resets = <&cru SRST_CRYPTO>;
|
||||||
|
reset-names = "crypto-rst";
|
||||||
|
};
|
||||||
|
|
||||||
|
iep_mmu: iommu@ff900800 {
|
||||||
|
compatible = "rockchip,iommu";
|
||||||
|
reg = <0xff900800 0x40>;
|
||||||
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
|
||||||
|
clock-names = "aclk", "iface";
|
||||||
|
#iommu-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
isp_mmu: iommu@ff914000 {
|
||||||
|
compatible = "rockchip,iommu";
|
||||||
|
reg = <0xff914000 0x100>, <0xff915000 0x100>;
|
||||||
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
|
||||||
|
clock-names = "aclk", "iface";
|
||||||
|
#iommu-cells = <0>;
|
||||||
|
rockchip,disable-mmu-reset;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
rga: rga@ff920000 {
|
||||||
|
compatible = "rockchip,rk3288-rga";
|
||||||
|
reg = <0xff920000 0x180>;
|
||||||
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
|
||||||
|
clock-names = "aclk", "hclk", "sclk";
|
||||||
|
power-domains = <&power RK3288_PD_VIO>;
|
||||||
|
resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
|
||||||
|
reset-names = "core", "axi", "ahb";
|
||||||
|
};
|
||||||
|
|
||||||
vopb: vop@ff930000 {
|
vopb: vop@ff930000 {
|
||||||
compatible = "rockchip,rk3288-vop";
|
compatible = "rockchip,rk3288-vop";
|
||||||
reg = <0xff930000 0x19c>;
|
reg = <0xff930000 0x19c>;
|
||||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
|
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
|
||||||
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
||||||
|
power-domains = <&power RK3288_PD_VIO>;
|
||||||
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
|
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
|
||||||
reset-names = "axi", "ahb", "dclk";
|
reset-names = "axi", "ahb", "dclk";
|
||||||
iommus = <&vopb_mmu>;
|
iommus = <&vopb_mmu>;
|
||||||
power-domains = <&power RK3288_PD_VIO>;
|
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
vopb_out: port {
|
vopb_out: port {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
|
||||||
vopb_out_edp: endpoint@0 {
|
vopb_out_edp: endpoint@0 {
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
remote-endpoint = <&edp_in_vopb>;
|
remote-endpoint = <&edp_in_vopb>;
|
||||||
};
|
};
|
||||||
|
|
||||||
vopb_out_hdmi: endpoint@1 {
|
vopb_out_hdmi: endpoint@1 {
|
||||||
reg = <1>;
|
reg = <1>;
|
||||||
remote-endpoint = <&hdmi_in_vopb>;
|
remote-endpoint = <&hdmi_in_vopb>;
|
||||||
};
|
};
|
||||||
|
|
||||||
vopb_out_lvds: endpoint@2 {
|
vopb_out_lvds: endpoint@2 {
|
||||||
reg = <2>;
|
reg = <2>;
|
||||||
remote-endpoint = <&lvds_in_vopb>;
|
remote-endpoint = <&lvds_in_vopb>;
|
||||||
};
|
};
|
||||||
|
|
||||||
vopb_out_mipi: endpoint@3 {
|
vopb_out_mipi: endpoint@3 {
|
||||||
reg = <3>;
|
reg = <3>;
|
||||||
remote-endpoint = <&mipi_in_vopb>;
|
remote-endpoint = <&mipi_in_vopb>;
|
||||||
};
|
};
|
||||||
|
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -642,7 +888,8 @@
|
||||||
compatible = "rockchip,iommu";
|
compatible = "rockchip,iommu";
|
||||||
reg = <0xff930300 0x100>;
|
reg = <0xff930300 0x100>;
|
||||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "vopb_mmu";
|
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
|
||||||
|
clock-names = "aclk", "iface";
|
||||||
power-domains = <&power RK3288_PD_VIO>;
|
power-domains = <&power RK3288_PD_VIO>;
|
||||||
#iommu-cells = <0>;
|
#iommu-cells = <0>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -654,31 +901,35 @@
|
||||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
|
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
|
||||||
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
||||||
|
power-domains = <&power RK3288_PD_VIO>;
|
||||||
resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
|
resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
|
||||||
reset-names = "axi", "ahb", "dclk";
|
reset-names = "axi", "ahb", "dclk";
|
||||||
iommus = <&vopl_mmu>;
|
iommus = <&vopl_mmu>;
|
||||||
power-domains = <&power RK3288_PD_VIO>;
|
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
vopl_out: port {
|
vopl_out: port {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
|
||||||
vopl_out_edp: endpoint@0 {
|
vopl_out_edp: endpoint@0 {
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
remote-endpoint = <&edp_in_vopl>;
|
remote-endpoint = <&edp_in_vopl>;
|
||||||
};
|
};
|
||||||
|
|
||||||
vopl_out_hdmi: endpoint@1 {
|
vopl_out_hdmi: endpoint@1 {
|
||||||
reg = <1>;
|
reg = <1>;
|
||||||
remote-endpoint = <&hdmi_in_vopl>;
|
remote-endpoint = <&hdmi_in_vopl>;
|
||||||
};
|
};
|
||||||
|
|
||||||
vopl_out_lvds: endpoint@2 {
|
vopl_out_lvds: endpoint@2 {
|
||||||
reg = <2>;
|
reg = <2>;
|
||||||
remote-endpoint = <&lvds_in_vopl>;
|
remote-endpoint = <&lvds_in_vopl>;
|
||||||
};
|
};
|
||||||
|
|
||||||
vopl_out_mipi: endpoint@3 {
|
vopl_out_mipi: endpoint@3 {
|
||||||
reg = <3>;
|
reg = <3>;
|
||||||
remote-endpoint = <&mipi_in_vopl>;
|
remote-endpoint = <&mipi_in_vopl>;
|
||||||
};
|
};
|
||||||
|
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -686,7 +937,8 @@
|
||||||
compatible = "rockchip,iommu";
|
compatible = "rockchip,iommu";
|
||||||
reg = <0xff940300 0x100>;
|
reg = <0xff940300 0x100>;
|
||||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "vopl_mmu";
|
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
|
||||||
|
clock-names = "aclk", "iface";
|
||||||
power-domains = <&power RK3288_PD_VIO>;
|
power-domains = <&power RK3288_PD_VIO>;
|
||||||
#iommu-cells = <0>;
|
#iommu-cells = <0>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
@ -695,16 +947,14 @@
|
||||||
mipi_dsi: mipi@ff960000 {
|
mipi_dsi: mipi@ff960000 {
|
||||||
compatible = "rockchip,rk3288_mipi_dsi";
|
compatible = "rockchip,rk3288_mipi_dsi";
|
||||||
reg = <0xff960000 0x4000>;
|
reg = <0xff960000 0x4000>;
|
||||||
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&cru PCLK_MIPI_DSI0>;
|
clocks = <&cru PCLK_MIPI_DSI0>;
|
||||||
clock-names = "pclk_mipi";
|
clock-names = "pclk_mipi";
|
||||||
/*pinctrl-names = "default";
|
power-domains = <&power RK3288_PD_VIO>;
|
||||||
pinctrl-0 = <&lcdc0_ctl>;*/
|
|
||||||
rockchip,grf = <&grf>;
|
rockchip,grf = <&grf>;
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
ports {
|
ports {
|
||||||
reg = <1>;
|
|
||||||
mipi_in: port {
|
mipi_in: port {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
|
@ -726,16 +976,21 @@
|
||||||
clocks = <&cru PCLK_LVDS_PHY>;
|
clocks = <&cru PCLK_LVDS_PHY>;
|
||||||
clock-names = "pclk_lvds";
|
clock-names = "pclk_lvds";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&lcdc0_ctl>;
|
pinctrl-0 = <&lcdc_ctl>;
|
||||||
|
power-domains = <&power RK3288_PD_VIO>;
|
||||||
rockchip,grf = <&grf>;
|
rockchip,grf = <&grf>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
ports {
|
ports {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
|
||||||
lvds_in: port@0 {
|
lvds_in: port@0 {
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
|
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
|
||||||
lvds_in_vopb: endpoint@0 {
|
lvds_in_vopb: endpoint@0 {
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
remote-endpoint = <&vopb_out_lvds>;
|
remote-endpoint = <&vopb_out_lvds>;
|
||||||
|
|
@ -753,12 +1008,13 @@
|
||||||
reg = <0xff970000 0x4000>;
|
reg = <0xff970000 0x4000>;
|
||||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
|
clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
|
||||||
rockchip,grf = <&grf>;
|
|
||||||
clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
|
clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
|
||||||
resets = <&cru 111>;
|
resets = <&cru SRST_EDP>;
|
||||||
reset-names = "edp";
|
reset-names = "edp";
|
||||||
|
rockchip,grf = <&grf>;
|
||||||
power-domains = <&power RK3288_PD_VIO>;
|
power-domains = <&power RK3288_PD_VIO>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
ports {
|
ports {
|
||||||
edp_in: port {
|
edp_in: port {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -779,12 +1035,14 @@
|
||||||
compatible = "rockchip,rk3288-dw-hdmi";
|
compatible = "rockchip,rk3288-dw-hdmi";
|
||||||
reg = <0xff980000 0x20000>;
|
reg = <0xff980000 0x20000>;
|
||||||
reg-io-width = <4>;
|
reg-io-width = <4>;
|
||||||
ddc-i2c-bus = <&i2c5>;
|
#sound-dai-cells = <0>;
|
||||||
rockchip,grf = <&grf>;
|
rockchip,grf = <&grf>;
|
||||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
|
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
|
||||||
clock-names = "iahb", "isfr";
|
clock-names = "iahb", "isfr";
|
||||||
|
power-domains = <&power RK3288_PD_VIO>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
ports {
|
ports {
|
||||||
hdmi_in: port {
|
hdmi_in: port {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
@ -801,65 +1059,155 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
hdmi_audio: hdmi_audio {
|
|
||||||
compatible = "rockchip,rk3288-hdmi-audio";
|
|
||||||
i2s-controller = <&i2s>;
|
|
||||||
status = "disable";
|
|
||||||
};
|
|
||||||
|
|
||||||
vpu: video-codec@ff9a0000 {
|
vpu: video-codec@ff9a0000 {
|
||||||
compatible = "rockchip,rk3288-vpu";
|
compatible = "rockchip,rk3288-vpu";
|
||||||
reg = <0xff9a0000 0x800>;
|
reg = <0xff9a0000 0x800>;
|
||||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "vepu", "vdpu";
|
interrupt-names = "vepu", "vdpu";
|
||||||
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
||||||
clock-names = "aclk_vcodec", "hclk_vcodec";
|
clock-names = "aclk", "hclk";
|
||||||
power-domains = <&power RK3288_PD_VIDEO>;
|
|
||||||
iommus = <&vpu_mmu>;
|
iommus = <&vpu_mmu>;
|
||||||
|
power-domains = <&power RK3288_PD_VIDEO>;
|
||||||
};
|
};
|
||||||
|
|
||||||
vpu_mmu: iommu@ff9a0800 {
|
vpu_mmu: iommu@ff9a0800 {
|
||||||
compatible = "rockchip,iommu";
|
compatible = "rockchip,iommu";
|
||||||
reg = <0xff9a0800 0x100>;
|
reg = <0xff9a0800 0x100>;
|
||||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "vpu_mmu";
|
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
||||||
power-domains = <&power RK3288_PD_VIDEO>;
|
clock-names = "aclk", "iface";
|
||||||
#iommu-cells = <0>;
|
#iommu-cells = <0>;
|
||||||
|
power-domains = <&power RK3288_PD_VIDEO>;
|
||||||
|
};
|
||||||
|
|
||||||
|
hevc_mmu: iommu@ff9c0440 {
|
||||||
|
compatible = "rockchip,iommu";
|
||||||
|
reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
|
||||||
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
|
||||||
|
clock-names = "aclk", "iface";
|
||||||
|
#iommu-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
gpu: gpu@ffa30000 {
|
gpu: gpu@ffa30000 {
|
||||||
compatible = "arm,malit764",
|
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
|
||||||
"arm,malit76x",
|
|
||||||
"arm,malit7xx",
|
|
||||||
"arm,mali-midgard";
|
|
||||||
reg = <0xffa30000 0x10000>;
|
reg = <0xffa30000 0x10000>;
|
||||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "JOB", "MMU", "GPU";
|
interrupt-names = "job", "mmu", "gpu";
|
||||||
clocks = <&cru ACLK_GPU>;
|
clocks = <&cru ACLK_GPU>;
|
||||||
clock-names = "aclk_gpu";
|
operating-points-v2 = <&gpu_opp_table>;
|
||||||
operating-points = <
|
#cooling-cells = <2>; /* min followed by max */
|
||||||
/* KHz uV */
|
|
||||||
100000 950000
|
|
||||||
200000 950000
|
|
||||||
300000 1000000
|
|
||||||
400000 1100000
|
|
||||||
/* 500000 1200000 - See crosbug.com/p/33857 */
|
|
||||||
600000 1250000
|
|
||||||
>;
|
|
||||||
power-domains = <&power RK3288_PD_GPU>;
|
power-domains = <&power RK3288_PD_GPU>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
gpu_opp_table: opp-table-1 {
|
||||||
|
compatible = "operating-points-v2";
|
||||||
|
|
||||||
|
opp-100000000 {
|
||||||
|
opp-hz = /bits/ 64 <100000000>;
|
||||||
|
opp-microvolt = <950000>;
|
||||||
|
};
|
||||||
|
opp-200000000 {
|
||||||
|
opp-hz = /bits/ 64 <200000000>;
|
||||||
|
opp-microvolt = <950000>;
|
||||||
|
};
|
||||||
|
opp-300000000 {
|
||||||
|
opp-hz = /bits/ 64 <300000000>;
|
||||||
|
opp-microvolt = <1000000>;
|
||||||
|
};
|
||||||
|
opp-400000000 {
|
||||||
|
opp-hz = /bits/ 64 <400000000>;
|
||||||
|
opp-microvolt = <1100000>;
|
||||||
|
};
|
||||||
|
opp-600000000 {
|
||||||
|
opp-hz = /bits/ 64 <600000000>;
|
||||||
|
opp-microvolt = <1250000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_gpu_r: qos@ffaa0000 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffaa0000 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_gpu_w: qos@ffaa0080 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffaa0080 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_vio1_vop: qos@ffad0000 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffad0000 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_vio1_isp_w0: qos@ffad0100 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffad0100 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_vio1_isp_w1: qos@ffad0180 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0x0 0xffad0180 0x0 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_vio0_vop: qos@ffad0400 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0x0 0xffad0400 0x0 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_vio0_vip: qos@ffad0480 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffad0480 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_vio0_iep: qos@ffad0500 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffad0500 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_vio2_rga_r: qos@ffad0800 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffad0800 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_vio2_rga_w: qos@ffad0880 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffad0880 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_vio1_isp_r: qos@ffad0900 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffad0900 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_video: qos@ffae0000 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffae0000 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_hevc_r: qos@ffaf0000 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffaf0000 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
|
qos_hevc_w: qos@ffaf0080 {
|
||||||
|
compatible = "rockchip,rk3288-qos", "syscon";
|
||||||
|
reg = <0xffaf0080 0x20>;
|
||||||
|
};
|
||||||
|
|
||||||
dmac_bus_s: dma-controller@ffb20000 {
|
dmac_bus_s: dma-controller@ffb20000 {
|
||||||
compatible = "arm,pl330", "arm,primecell";
|
compatible = "arm,pl330", "arm,primecell";
|
||||||
reg = <0xffb20000 0x4000>;
|
reg = <0xffb20000 0x4000>;
|
||||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
#dma-cells = <1>;
|
#dma-cells = <1>;
|
||||||
broken-no-flushp;
|
arm,pl330-broken-no-flushp;
|
||||||
|
arm,pl330-periph-burst;
|
||||||
clocks = <&cru ACLK_DMAC1>;
|
clocks = <&cru ACLK_DMAC1>;
|
||||||
clock-names = "apb_pclk";
|
clock-names = "apb_pclk";
|
||||||
};
|
};
|
||||||
|
|
@ -867,7 +1215,17 @@
|
||||||
efuse: efuse@ffb40000 {
|
efuse: efuse@ffb40000 {
|
||||||
compatible = "rockchip,rk3288-efuse";
|
compatible = "rockchip,rk3288-efuse";
|
||||||
reg = <0xffb40000 0x10000>;
|
reg = <0xffb40000 0x10000>;
|
||||||
status = "disabled";
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
clocks = <&cru PCLK_EFUSE256>;
|
||||||
|
clock-names = "pclk_efuse";
|
||||||
|
|
||||||
|
cpu_id: cpu-id@7 {
|
||||||
|
reg = <0x07 0x10>;
|
||||||
|
};
|
||||||
|
cpu_leakage: cpu_leakage@17 {
|
||||||
|
reg = <0x17 0x1>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
gic: interrupt-controller@ffc01000 {
|
gic: interrupt-controller@ffc01000 {
|
||||||
|
|
@ -926,7 +1284,7 @@
|
||||||
|
|
||||||
gpio0: gpio0@ff750000 {
|
gpio0: gpio0@ff750000 {
|
||||||
compatible = "rockchip,gpio-bank";
|
compatible = "rockchip,gpio-bank";
|
||||||
reg = <0xff750000 0x100>;
|
reg = <0xff750000 0x100>;
|
||||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&cru PCLK_GPIO0>;
|
clocks = <&cru PCLK_GPIO0>;
|
||||||
|
|
||||||
|
|
@ -1045,6 +1403,24 @@
|
||||||
hdmi_cec_c0: hdmi-cec-c0 {
|
hdmi_cec_c0: hdmi-cec-c0 {
|
||||||
rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
|
rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
hdmi_cec_c7: hdmi-cec-c7 {
|
||||||
|
rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
|
hdmi_ddc: hdmi-ddc {
|
||||||
|
rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
|
||||||
|
<7 RK_PC4 2 &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
|
hdmi_ddc_unwedge: hdmi-ddc-unwedge {
|
||||||
|
rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
|
||||||
|
<7 RK_PC4 2 &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pcfg_output_low: pcfg-output-low {
|
||||||
|
output-low;
|
||||||
};
|
};
|
||||||
|
|
||||||
pcfg_pull_up: pcfg-pull-up {
|
pcfg_pull_up: pcfg-pull-up {
|
||||||
|
|
@ -1064,7 +1440,7 @@
|
||||||
drive-strength = <12>;
|
drive-strength = <12>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sleep {
|
suspend {
|
||||||
global_pwroff: global-pwroff {
|
global_pwroff: global-pwroff {
|
||||||
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
|
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
|
||||||
};
|
};
|
||||||
|
|
@ -1082,6 +1458,12 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
edp {
|
||||||
|
edp_hpd: edp-hpd {
|
||||||
|
rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
i2c0 {
|
i2c0 {
|
||||||
i2c0_xfer: i2c0-xfer {
|
i2c0_xfer: i2c0-xfer {
|
||||||
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
|
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
|
||||||
|
|
@ -1135,8 +1517,8 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
lcdc0 {
|
lcdc {
|
||||||
lcdc0_ctl: lcdc0-ctl {
|
lcdc_ctl: lcdc-ctl {
|
||||||
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
|
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
|
||||||
<1 RK_PD1 1 &pcfg_pull_none>,
|
<1 RK_PD1 1 &pcfg_pull_none>,
|
||||||
<1 RK_PD2 1 &pcfg_pull_none>,
|
<1 RK_PD2 1 &pcfg_pull_none>,
|
||||||
|
|
@ -1153,7 +1535,7 @@
|
||||||
rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
|
rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sdmmc_cd: sdmcc-cd {
|
sdmmc_cd: sdmmc-cd {
|
||||||
rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
|
rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -1344,7 +1726,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
uart0_cts: uart0-cts {
|
uart0_cts: uart0-cts {
|
||||||
rockchip,pins = <4 RK_PC2 1 &pcfg_pull_none>;
|
rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
|
||||||
};
|
};
|
||||||
|
|
||||||
uart0_rts: uart0-rts {
|
uart0_rts: uart0-rts {
|
||||||
|
|
@ -1359,7 +1741,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
uart1_cts: uart1-cts {
|
uart1_cts: uart1-cts {
|
||||||
rockchip,pins = <5 RK_PB2 1 &pcfg_pull_none>;
|
rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
|
||||||
};
|
};
|
||||||
|
|
||||||
uart1_rts: uart1-rts {
|
uart1_rts: uart1-rts {
|
||||||
|
|
@ -1382,7 +1764,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
uart3_cts: uart3-cts {
|
uart3_cts: uart3-cts {
|
||||||
rockchip,pins = <7 RK_PB1 1 &pcfg_pull_none>;
|
rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
|
||||||
};
|
};
|
||||||
|
|
||||||
uart3_rts: uart3-rts {
|
uart3_rts: uart3-rts {
|
||||||
|
|
@ -1392,20 +1774,24 @@
|
||||||
|
|
||||||
uart4 {
|
uart4 {
|
||||||
uart4_xfer: uart4-xfer {
|
uart4_xfer: uart4-xfer {
|
||||||
rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>,
|
rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
|
||||||
<5 RK_PB5 3 &pcfg_pull_none>;
|
<5 RK_PB6 3 &pcfg_pull_none>;
|
||||||
};
|
};
|
||||||
|
|
||||||
uart4_cts: uart4-cts {
|
uart4_cts: uart4-cts {
|
||||||
rockchip,pins = <5 RK_PB6 3 &pcfg_pull_none>;
|
rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
|
||||||
};
|
};
|
||||||
|
|
||||||
uart4_rts: uart4-rts {
|
uart4_rts: uart4-rts {
|
||||||
rockchip,pins = <5 RK_PB7 3 &pcfg_pull_none>;
|
rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
tsadc {
|
tsadc {
|
||||||
|
otp_pin: otp-pin {
|
||||||
|
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
otp_out: otp-out {
|
otp_out: otp-out {
|
||||||
rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
|
rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
|
||||||
};
|
};
|
||||||
|
|
|
||||||
18
arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi
Normal file
18
arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,18 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2022 Andy Yan <andy.yan@gmail.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "rk3399-u-boot.dtsi"
|
||||||
|
#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial2:1500000n8";
|
||||||
|
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&vdd_log {
|
||||||
|
regulator-init-microvolt = <950000>;
|
||||||
|
};
|
||||||
939
arch/arm/dts/rk3399-eaidk-610.dts
Normal file
939
arch/arm/dts/rk3399-eaidk-610.dts
Normal file
|
|
@ -0,0 +1,939 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include <dt-bindings/input/linux-event-codes.h>
|
||||||
|
#include <dt-bindings/pwm/pwm.h>
|
||||||
|
#include <dt-bindings/usb/pd.h>
|
||||||
|
#include "rk3399.dtsi"
|
||||||
|
#include "rk3399-opp.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "OPEN AI LAB EAIDK-610";
|
||||||
|
compatible = "openailab,eaidk-610", "rockchip,rk3399";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
mmc0 = &sdio0;
|
||||||
|
mmc1 = &sdmmc;
|
||||||
|
mmc2 = &sdhci;
|
||||||
|
};
|
||||||
|
|
||||||
|
backlight: backlight {
|
||||||
|
compatible = "pwm-backlight";
|
||||||
|
pwms = <&pwm0 0 25000 0>;
|
||||||
|
brightness-levels = <
|
||||||
|
0 1 2 3 4 5 6 7
|
||||||
|
8 9 10 11 12 13 14 15
|
||||||
|
16 17 18 19 20 21 22 23
|
||||||
|
24 25 26 27 28 29 30 31
|
||||||
|
32 33 34 35 36 37 38 39
|
||||||
|
40 41 42 43 44 45 46 47
|
||||||
|
48 49 50 51 52 53 54 55
|
||||||
|
56 57 58 59 60 61 62 63
|
||||||
|
64 65 66 67 68 69 70 71
|
||||||
|
72 73 74 75 76 77 78 79
|
||||||
|
80 81 82 83 84 85 86 87
|
||||||
|
88 89 90 91 92 93 94 95
|
||||||
|
96 97 98 99 100 101 102 103
|
||||||
|
104 105 106 107 108 109 110 111
|
||||||
|
112 113 114 115 116 117 118 119
|
||||||
|
120 121 122 123 124 125 126 127
|
||||||
|
128 129 130 131 132 133 134 135
|
||||||
|
136 137 138 139 140 141 142 143
|
||||||
|
144 145 146 147 148 149 150 151
|
||||||
|
152 153 154 155 156 157 158 159
|
||||||
|
160 161 162 163 164 165 166 167
|
||||||
|
168 169 170 171 172 173 174 175
|
||||||
|
176 177 178 179 180 181 182 183
|
||||||
|
184 185 186 187 188 189 190 191
|
||||||
|
192 193 194 195 196 197 198 199
|
||||||
|
200 201 202 203 204 205 206 207
|
||||||
|
208 209 210 211 212 213 214 215
|
||||||
|
216 217 218 219 220 221 222 223
|
||||||
|
224 225 226 227 228 229 230 231
|
||||||
|
232 233 234 235 236 237 238 239
|
||||||
|
240 241 242 243 244 245 246 247
|
||||||
|
248 249 250 251 252 253 254 255>;
|
||||||
|
default-brightness-level = <200>;
|
||||||
|
};
|
||||||
|
|
||||||
|
clkin_gmac: external-gmac-clock {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <125000000>;
|
||||||
|
clock-output-names = "clkin_gmac";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dc_12v: dc-12v {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "dc_12v";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-min-microvolt = <12000000>;
|
||||||
|
regulator-max-microvolt = <12000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio-keys {
|
||||||
|
compatible = "gpio-keys";
|
||||||
|
autorepeat;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pwrbtn>;
|
||||||
|
|
||||||
|
key-power {
|
||||||
|
debounce-interval = <100>;
|
||||||
|
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||||
|
label = "GPIO Key Power";
|
||||||
|
linux,code = <KEY_POWER>;
|
||||||
|
wakeup-source;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
leds {
|
||||||
|
compatible = "gpio-leds";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&work_led_pin>, <&user_led_pin>,
|
||||||
|
<&heartbeat_led_pin>, <&wlan_active_led_pin>,
|
||||||
|
<&bt_active_led_pin>;
|
||||||
|
|
||||||
|
work_led: led-0 {
|
||||||
|
label = "blue:work";
|
||||||
|
default-state = "on";
|
||||||
|
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
user_led: led-1 {
|
||||||
|
label = "read:user";
|
||||||
|
default-state = "off";
|
||||||
|
gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
heartbeat_led: led-2 {
|
||||||
|
label = "green:heartbeat";
|
||||||
|
linux,default-trigger = "heartbeat";
|
||||||
|
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wlan_active_led: led-3 {
|
||||||
|
label = "yellow:wlan";
|
||||||
|
gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
|
||||||
|
linux,default-trigger = "phy0tx";
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
|
||||||
|
bt_active_led: led-4 {
|
||||||
|
label = "blue:bt";
|
||||||
|
gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||||
|
linux,default-trigger = "hci0-power";
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
rt5651-sound {
|
||||||
|
compatible = "simple-audio-card";
|
||||||
|
simple-audio-card,name = "realtek,rt5651-codec";
|
||||||
|
simple-audio-card,format = "i2s";
|
||||||
|
simple-audio-card,mclk-fs = <256>;
|
||||||
|
simple-audio-card,widgets =
|
||||||
|
"Microphone", "Mic Jack",
|
||||||
|
"Headphone", "Headphone Jack";
|
||||||
|
simple-audio-card,routing =
|
||||||
|
"Mic Jack", "MICBIAS1",
|
||||||
|
"IN1P", "Mic Jack",
|
||||||
|
"Headphone Jack", "HPOL",
|
||||||
|
"Headphone Jack", "HPOR";
|
||||||
|
simple-audio-card,cpu {
|
||||||
|
sound-dai = <&i2s1>;
|
||||||
|
};
|
||||||
|
simple-audio-card,codec {
|
||||||
|
sound-dai = <&rt5651>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdio_pwrseq: sdio-pwrseq {
|
||||||
|
compatible = "mmc-pwrseq-simple";
|
||||||
|
clocks = <&rk808 1>;
|
||||||
|
clock-names = "ext_clock";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&wifi_enable_h>;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* On the module itself this is one of these (depending
|
||||||
|
* on the actual card populated):
|
||||||
|
* - SDIO_RESET_L_WL_REG_ON
|
||||||
|
* - PDN (power down when low)
|
||||||
|
*/
|
||||||
|
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* switched by pmic_sleep */
|
||||||
|
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "vcc1v8_s3";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
vin-supply = <&vcc_1v8>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc3v3_sys: vcc3v3-sys {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "vcc3v3_sys";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-min-microvolt = <3300000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
vin-supply = <&dc_12v>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc5v0_sys: vcc5v0-sys {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "vcc5v0_sys";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-min-microvolt = <5000000>;
|
||||||
|
regulator-max-microvolt = <5000000>;
|
||||||
|
vin-supply = <&dc_12v>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* For USB3.0 Port1/2 */
|
||||||
|
vcc5v0_host1: vcc5v0-host1-regulator {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
enable-active-high;
|
||||||
|
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&vcc5v0_host1_en>;
|
||||||
|
regulator-name = "vcc5v0_host1";
|
||||||
|
regulator-always-on;
|
||||||
|
vin-supply = <&vcc5v0_sys>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* For USB2.0 Port1/2 */
|
||||||
|
vcc5v0_host3: vcc5v0-host3-regulator {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
enable-active-high;
|
||||||
|
gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&vcc5v0_host3_en>;
|
||||||
|
regulator-name = "vcc5v0_host3";
|
||||||
|
regulator-always-on;
|
||||||
|
vin-supply = <&vcc5v0_sys>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc5v0_typec: vcc5v0-typec-regulator {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
enable-active-high;
|
||||||
|
gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&vcc5v0_typec_en>;
|
||||||
|
regulator-name = "vcc5v0_typec";
|
||||||
|
regulator-always-on;
|
||||||
|
vin-supply = <&vcc3v3_sys>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vdd_log: vdd-log {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "vdd_log";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-min-microvolt = <900000>;
|
||||||
|
regulator-max-microvolt = <900000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu_l0 {
|
||||||
|
cpu-supply = <&vdd_cpu_l>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu_l1 {
|
||||||
|
cpu-supply = <&vdd_cpu_l>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu_l2 {
|
||||||
|
cpu-supply = <&vdd_cpu_l>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu_l3 {
|
||||||
|
cpu-supply = <&vdd_cpu_l>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu_b0 {
|
||||||
|
cpu-supply = <&vdd_cpu_b>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu_b1 {
|
||||||
|
cpu-supply = <&vdd_cpu_b>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&emmc_phy {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gmac {
|
||||||
|
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||||
|
assigned-clock-parents = <&clkin_gmac>;
|
||||||
|
clock_in_out = "input";
|
||||||
|
phy-supply = <&vcc_lan>;
|
||||||
|
phy-mode = "rgmii";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&rgmii_pins>;
|
||||||
|
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||||
|
snps,reset-active-low;
|
||||||
|
snps,reset-delays-us = <0 10000 50000>;
|
||||||
|
tx_delay = <0x28>;
|
||||||
|
rx_delay = <0x11>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpu {
|
||||||
|
mali-supply = <&vdd_gpu>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&hdmi {
|
||||||
|
ddc-i2c-bus = <&i2c3>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&hdmi_cec>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c0 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
rk808: pmic@1b {
|
||||||
|
compatible = "rockchip,rk808";
|
||||||
|
reg = <0x1b>;
|
||||||
|
interrupt-parent = <&gpio1>;
|
||||||
|
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pmic_int_l>;
|
||||||
|
rockchip,system-power-controller;
|
||||||
|
wakeup-source;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
clock-output-names = "xin32k", "rk808-clkout2";
|
||||||
|
|
||||||
|
vcc1-supply = <&vcc3v3_sys>;
|
||||||
|
vcc2-supply = <&vcc3v3_sys>;
|
||||||
|
vcc3-supply = <&vcc3v3_sys>;
|
||||||
|
vcc4-supply = <&vcc3v3_sys>;
|
||||||
|
vcc6-supply = <&vcc3v3_sys>;
|
||||||
|
vcc7-supply = <&vcc3v3_sys>;
|
||||||
|
vcc8-supply = <&vcc3v3_sys>;
|
||||||
|
vcc9-supply = <&vcc3v3_sys>;
|
||||||
|
vcc10-supply = <&vcc3v3_sys>;
|
||||||
|
vcc11-supply = <&vcc3v3_sys>;
|
||||||
|
vcc12-supply = <&vcc3v3_sys>;
|
||||||
|
vddio-supply = <&vcc_3v0>;
|
||||||
|
|
||||||
|
regulators {
|
||||||
|
vdd_center: DCDC_REG1 {
|
||||||
|
regulator-name = "vdd_center";
|
||||||
|
regulator-min-microvolt = <750000>;
|
||||||
|
regulator-max-microvolt = <1350000>;
|
||||||
|
regulator-ramp-delay = <6001>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-off-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vdd_cpu_l: DCDC_REG2 {
|
||||||
|
regulator-name = "vdd_cpu_l";
|
||||||
|
regulator-min-microvolt = <750000>;
|
||||||
|
regulator-max-microvolt = <1350000>;
|
||||||
|
regulator-ramp-delay = <6001>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-off-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc_ddr: DCDC_REG3 {
|
||||||
|
regulator-name = "vcc_ddr";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-on-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc_1v8: DCDC_REG4 {
|
||||||
|
regulator-name = "vcc_1v8";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-on-in-suspend;
|
||||||
|
regulator-suspend-microvolt = <1800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc1v8_dvp: LDO_REG1 {
|
||||||
|
regulator-name = "vcc1v8_dvp";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-off-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc2v8_dvp: LDO_REG2 {
|
||||||
|
regulator-name = "vcc2v8_dvp";
|
||||||
|
regulator-min-microvolt = <2800000>;
|
||||||
|
regulator-max-microvolt = <2800000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-off-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc1v8_pmu: LDO_REG3 {
|
||||||
|
regulator-name = "vcc1v8_pmu";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-on-in-suspend;
|
||||||
|
regulator-suspend-microvolt = <1800000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc_sdio: LDO_REG4 {
|
||||||
|
regulator-name = "vcc_sdio";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <3000000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-on-in-suspend;
|
||||||
|
regulator-suspend-microvolt = <3000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcca3v0_codec: LDO_REG5 {
|
||||||
|
regulator-name = "vcca3v0_codec";
|
||||||
|
regulator-min-microvolt = <3000000>;
|
||||||
|
regulator-max-microvolt = <3000000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-off-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc_1v5: LDO_REG6 {
|
||||||
|
regulator-name = "vcc_1v5";
|
||||||
|
regulator-min-microvolt = <1500000>;
|
||||||
|
regulator-max-microvolt = <1500000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-on-in-suspend;
|
||||||
|
regulator-suspend-microvolt = <1500000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcca1v8_codec: LDO_REG7 {
|
||||||
|
regulator-name = "vcca1v8_codec";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-off-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc_3v0: LDO_REG8 {
|
||||||
|
regulator-name = "vcc_3v0";
|
||||||
|
regulator-min-microvolt = <3000000>;
|
||||||
|
regulator-max-microvolt = <3000000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-on-in-suspend;
|
||||||
|
regulator-suspend-microvolt = <3000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
|
||||||
|
regulator-name = "vcc3v3_s3";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-off-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc3v3_s0: SWITCH_REG2 {
|
||||||
|
regulator-name = "vcc3v3_s0";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-off-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vdd_cpu_b: regulator@40 {
|
||||||
|
compatible = "silergy,syr827";
|
||||||
|
reg = <0x40>;
|
||||||
|
fcs,suspend-voltage-selector = <1>;
|
||||||
|
regulator-name = "vdd_cpu_b";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&vsel1_pin>;
|
||||||
|
regulator-min-microvolt = <712500>;
|
||||||
|
regulator-max-microvolt = <1500000>;
|
||||||
|
regulator-ramp-delay = <1000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
vin-supply = <&vcc3v3_sys>;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-off-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
vdd_gpu: regulator@41 {
|
||||||
|
compatible = "silergy,syr828";
|
||||||
|
reg = <0x41>;
|
||||||
|
fcs,suspend-voltage-selector = <1>;
|
||||||
|
regulator-name = "vdd_gpu";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&vsel2_pin>;
|
||||||
|
regulator-min-microvolt = <712500>;
|
||||||
|
regulator-max-microvolt = <1500000>;
|
||||||
|
regulator-ramp-delay = <1000>;
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
vin-supply = <&vcc3v3_sys>;
|
||||||
|
|
||||||
|
regulator-state-mem {
|
||||||
|
regulator-off-in-suspend;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c1 {
|
||||||
|
i2c-scl-rising-time-ns = <300>;
|
||||||
|
i2c-scl-falling-time-ns = <15>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
rt5651: audio-codec@1a {
|
||||||
|
compatible = "rockchip,rt5651";
|
||||||
|
reg = <0x1a>;
|
||||||
|
clocks = <&cru SCLK_I2S_8CH_OUT>;
|
||||||
|
clock-names = "mclk";
|
||||||
|
hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||||
|
spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||||
|
#sound-dai-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c3 {
|
||||||
|
i2c-scl-rising-time-ns = <450>;
|
||||||
|
i2c-scl-falling-time-ns = <15>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c4 {
|
||||||
|
i2c-scl-rising-time-ns = <600>;
|
||||||
|
i2c-scl-falling-time-ns = <20>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
fusb0: typec-portc@22 {
|
||||||
|
compatible = "fcs,fusb302";
|
||||||
|
reg = <0x22>;
|
||||||
|
interrupt-parent = <&gpio1>;
|
||||||
|
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&fusb0_int>;
|
||||||
|
vbus-supply = <&vcc5v0_typec>;
|
||||||
|
|
||||||
|
ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
usbc0_role_sw: endpoint@0 {
|
||||||
|
remote-endpoint = <&dwc3_0_role_switch>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
connector {
|
||||||
|
compatible = "usb-c-connector";
|
||||||
|
data-role = "dual";
|
||||||
|
label = "USB-C";
|
||||||
|
|
||||||
|
ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
|
||||||
|
usbc_hs: endpoint {
|
||||||
|
remote-endpoint = <&u2phy0_typec_hs>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
|
||||||
|
usbc_ss: endpoint {
|
||||||
|
remote-endpoint = <&tcphy0_typec_ss>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2s1 {
|
||||||
|
rockchip,playback-channels = <2>;
|
||||||
|
rockchip,capture-channels = <2>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2s2 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&io_domains {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
audio-supply = <&vcca1v8_codec>;
|
||||||
|
bt656-supply = <&vcc_3v0>;
|
||||||
|
gpio1830-supply = <&vcc_3v0>;
|
||||||
|
sdmmc-supply = <&vcc_sdio>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pmu_io_domains {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
pmu1830-supply = <&vcc_3v0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pinctrl {
|
||||||
|
buttons {
|
||||||
|
pwrbtn: pwrbtn {
|
||||||
|
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
bt {
|
||||||
|
bt_enable_h: bt-enable-h {
|
||||||
|
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
|
bt_host_wake_l: bt-host-wake-l {
|
||||||
|
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
|
bt_wake_l: bt-wake-l {
|
||||||
|
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fusb302x {
|
||||||
|
fusb0_int: fusb0-int {
|
||||||
|
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
lcd-panel {
|
||||||
|
lcd_panel_reset: lcd-panel-reset {
|
||||||
|
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
leds {
|
||||||
|
work_led_pin: work-led-pin {
|
||||||
|
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
|
user_led_pin: user-led-pin {
|
||||||
|
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
|
heartbeat_led_pin: heartbeat-led-pin {
|
||||||
|
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wlan_active_led_pin: wlan-led-pin {
|
||||||
|
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
|
bt_active_led_pin: bt-led-pin {
|
||||||
|
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
pmic {
|
||||||
|
pmic_int_l: pmic-int-l {
|
||||||
|
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vsel1_pin: vsel1-pin {
|
||||||
|
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vsel2_pin: vsel2-pin {
|
||||||
|
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
rt5651 {
|
||||||
|
rt5651_hpcon: rt5640-hpcon {
|
||||||
|
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sdio-pwrseq {
|
||||||
|
wifi_enable_h: wifi-enable-h {
|
||||||
|
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
usb-typec {
|
||||||
|
vcc5v0_typec_en: vcc5v0_typec_en {
|
||||||
|
rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
usb2 {
|
||||||
|
vcc5v0_host3_en: vcc5v0-host3-en {
|
||||||
|
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
|
||||||
|
vcc5v0_host1_en: vcc5v0-host1-en {
|
||||||
|
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
wifi {
|
||||||
|
wifi_host_wake_l: wifi-host-wake-l {
|
||||||
|
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&pwm0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&saradc {
|
||||||
|
vref-supply = <&vcca1v8_s3>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdio0 {
|
||||||
|
/* WiFi & BT combo module AMPAK AP6255 */
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
bus-width = <4>;
|
||||||
|
clock-frequency = <50000000>;
|
||||||
|
cap-sdio-irq;
|
||||||
|
cap-sd-highspeed;
|
||||||
|
keep-power-in-suspend;
|
||||||
|
mmc-pwrseq = <&sdio_pwrseq>;
|
||||||
|
non-removable;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||||
|
sd-uhs-sdr104;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
brcmf: wifi@1 {
|
||||||
|
compatible = "brcm,bcm4329-fmac";
|
||||||
|
reg = <1>;
|
||||||
|
interrupt-parent = <&gpio0>;
|
||||||
|
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||||
|
interrupt-names = "host-wake";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&wifi_host_wake_l>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc {
|
||||||
|
bus-width = <4>;
|
||||||
|
cap-mmc-highspeed;
|
||||||
|
cap-sd-highspeed;
|
||||||
|
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||||
|
disable-wp;
|
||||||
|
max-frequency = <150000000>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdhci {
|
||||||
|
bus-width = <8>;
|
||||||
|
non-removable;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&tcphy0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&tcphy0_usb3 {
|
||||||
|
orientation-switch;
|
||||||
|
port {
|
||||||
|
tcphy0_typec_ss: endpoint {
|
||||||
|
remote-endpoint = <&usbc_ss>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&tcphy1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&tsadc {
|
||||||
|
/* tshut mode 0:CRU 1:GPIO */
|
||||||
|
rockchip,hw-tshut-mode = <1>;
|
||||||
|
/* tshut polarity 0:LOW 1:HIGH */
|
||||||
|
rockchip,hw-tshut-polarity = <1>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&u2phy0 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
u2phy0_otg: otg-port {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
u2phy0_host: host-port {
|
||||||
|
phy-supply = <&vcc5v0_host3>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
port {
|
||||||
|
u2phy0_typec_hs: endpoint {
|
||||||
|
remote-endpoint = <&usbc_hs>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&u2phy1 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
u2phy1_otg: otg-port {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
u2phy1_host: host-port {
|
||||||
|
phy-supply = <&vcc5v0_host3>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
bluetooth {
|
||||||
|
compatible = "brcm,bcm4345c5";
|
||||||
|
clocks = <&rk808 1>;
|
||||||
|
clock-names = "lpo";
|
||||||
|
device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||||
|
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||||
|
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||||
|
max-speed = <1500000>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
|
||||||
|
vbat-supply = <&vcc3v3_sys>;
|
||||||
|
vddio-supply = <&vcc_1v8>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart2 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_host0_ehci {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_host0_ohci {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_host1_ehci {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_host1_ohci {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbdrd3_0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbdrd_dwc3_0 {
|
||||||
|
status = "okay";
|
||||||
|
usb-role-switch;
|
||||||
|
|
||||||
|
port {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
dwc3_0_role_switch: endpoint@0 {
|
||||||
|
reg = <0>;
|
||||||
|
remote-endpoint = <&usbc0_role_sw>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbdrd3_1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usbdrd_dwc3_1 {
|
||||||
|
status = "okay";
|
||||||
|
dr_mode = "host";
|
||||||
|
};
|
||||||
|
|
||||||
|
&vopb {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&vopb_mmu {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&vopl {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&vopl_mmu {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
@ -14,7 +14,7 @@
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
config {
|
config {
|
||||||
u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
|
u-boot,spl-payload-offset = <0x80000>; /* @ 512KB */
|
||||||
u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
|
u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
|
||||||
u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
|
u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
|
||||||
u-boot,boot-led = "module_led";
|
u-boot,boot-led = "module_led";
|
||||||
|
|
@ -31,24 +31,6 @@
|
||||||
spi5 = &spi5;
|
spi5 = &spi5;
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
|
||||||
* The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
|
|
||||||
* eMMC and SPI flash powered-down initially (in fact it keeps the
|
|
||||||
* reset signal asserted). Even though it is an enable signal, we
|
|
||||||
* model this as a regulator.
|
|
||||||
*/
|
|
||||||
bios_enable: bios_enable {
|
|
||||||
compatible = "regulator-fixed";
|
|
||||||
u-boot,dm-pre-reloc;
|
|
||||||
regulator-name = "bios_enable";
|
|
||||||
enable-active-high;
|
|
||||||
gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
|
|
||||||
regulator-always-on;
|
|
||||||
regulator-boot-on;
|
|
||||||
regulator-min-microvolt = <1800000>;
|
|
||||||
regulator-max-microvolt = <1800000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
vdd_log: vdd-log {
|
vdd_log: vdd-log {
|
||||||
compatible = "pwm-regulator";
|
compatible = "pwm-regulator";
|
||||||
pwms = <&pwm2 0 25000 1>;
|
pwms = <&pwm2 0 25000 1>;
|
||||||
|
|
@ -62,14 +44,69 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&binman {
|
||||||
|
simple-bin {
|
||||||
|
blob {
|
||||||
|
offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
|
||||||
|
simple-bin-spi {
|
||||||
|
blob {
|
||||||
|
/* same as u-boot,spl-payload-offset */
|
||||||
|
offset = <0x80000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
&gpio1 {
|
&gpio1 {
|
||||||
u-boot,dm-pre-reloc;
|
u-boot,dm-pre-reloc;
|
||||||
};
|
};
|
||||||
|
|
||||||
&gpio3 {
|
&gpio3 {
|
||||||
u-boot,dm-pre-reloc;
|
u-boot,dm-pre-reloc;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
|
||||||
|
* eMMC and SPI flash powered-down initially (in fact it keeps the
|
||||||
|
* reset signal asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable
|
||||||
|
* eMMC and SPI after the SPL has been booted from SD Card.
|
||||||
|
*/
|
||||||
|
bios_disable_override {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
gpios = <RK_PD5 GPIO_ACTIVE_LOW>;
|
||||||
|
output-high;
|
||||||
|
line-name = "bios_disable_override";
|
||||||
|
gpio-hog;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&gpio4 {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
};
|
};
|
||||||
|
|
||||||
&norflash {
|
&norflash {
|
||||||
u-boot,dm-pre-reloc;
|
u-boot,dm-pre-reloc;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&pcfg_pull_none {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&pcfg_pull_up {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc_bus4 {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc_clk {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
||||||
|
&sdmmc_cmd {
|
||||||
|
u-boot,dm-pre-reloc;
|
||||||
|
};
|
||||||
|
|
|
||||||
35
arch/arm/dts/rk3566.dtsi
Normal file
35
arch/arm/dts/rk3566.dtsi
Normal file
|
|
@ -0,0 +1,35 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||||
|
|
||||||
|
#include "rk356x.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "rockchip,rk3566";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pipegrf {
|
||||||
|
compatible = "rockchip,rk3566-pipe-grf", "syscon";
|
||||||
|
};
|
||||||
|
|
||||||
|
&power {
|
||||||
|
power-domain@RK3568_PD_PIPE {
|
||||||
|
reg = <RK3568_PD_PIPE>;
|
||||||
|
clocks = <&cru PCLK_PIPE>;
|
||||||
|
pm_qos = <&qos_pcie2x1>,
|
||||||
|
<&qos_sata1>,
|
||||||
|
<&qos_sata2>,
|
||||||
|
<&qos_usb3_0>,
|
||||||
|
<&qos_usb3_1>;
|
||||||
|
#power-domain-cells = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_host0_xhci {
|
||||||
|
phys = <&usb2phy0_otg>;
|
||||||
|
phy-names = "usb2-phy";
|
||||||
|
extcon = <&usb2phy0>;
|
||||||
|
maximum-speed = "high-speed";
|
||||||
|
};
|
||||||
|
|
||||||
|
&vop {
|
||||||
|
compatible = "rockchip,rk3566-vop";
|
||||||
|
};
|
||||||
|
|
@ -3,7 +3,7 @@
|
||||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "rk3568-u-boot.dtsi"
|
#include "rk356x-u-boot.dtsi"
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
chosen {
|
chosen {
|
||||||
|
|
|
||||||
|
|
@ -3108,4 +3108,13 @@
|
||||||
<4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
|
<4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
tsadc {
|
||||||
|
/omit-if-no-ref/
|
||||||
|
tsadc_pin: tsadc-pin {
|
||||||
|
rockchip,pins =
|
||||||
|
/* tsadc_pin */
|
||||||
|
<0 RK_PA1 0 &pcfg_pull_none>;
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -3,777 +3,141 @@
|
||||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <dt-bindings/clock/rk3568-cru.h>
|
#include "rk356x.dtsi"
|
||||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
||||||
#include <dt-bindings/interrupt-controller/irq.h>
|
|
||||||
#include <dt-bindings/phy/phy.h>
|
|
||||||
#include <dt-bindings/pinctrl/rockchip.h>
|
|
||||||
#include <dt-bindings/soc/rockchip,boot-mode.h>
|
|
||||||
#include <dt-bindings/thermal/thermal.h>
|
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
compatible = "rockchip,rk3568";
|
compatible = "rockchip,rk3568";
|
||||||
|
|
||||||
interrupt-parent = <&gic>;
|
sata0: sata@fc000000 {
|
||||||
#address-cells = <2>;
|
compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
|
||||||
#size-cells = <2>;
|
reg = <0 0xfc000000 0 0x1000>;
|
||||||
|
clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
|
||||||
aliases {
|
<&cru CLK_SATA0_RXOOB>;
|
||||||
gpio0 = &gpio0;
|
clock-names = "sata", "pmalive", "rxoob";
|
||||||
gpio1 = &gpio1;
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
gpio2 = &gpio2;
|
phys = <&combphy0 PHY_TYPE_SATA>;
|
||||||
gpio3 = &gpio3;
|
phy-names = "sata-phy";
|
||||||
gpio4 = &gpio4;
|
ports-implemented = <0x1>;
|
||||||
i2c0 = &i2c0;
|
power-domains = <&power RK3568_PD_PIPE>;
|
||||||
i2c1 = &i2c1;
|
|
||||||
i2c2 = &i2c2;
|
|
||||||
i2c3 = &i2c3;
|
|
||||||
i2c4 = &i2c4;
|
|
||||||
i2c5 = &i2c5;
|
|
||||||
serial0 = &uart0;
|
|
||||||
serial1 = &uart1;
|
|
||||||
serial2 = &uart2;
|
|
||||||
serial3 = &uart3;
|
|
||||||
serial4 = &uart4;
|
|
||||||
serial5 = &uart5;
|
|
||||||
serial6 = &uart6;
|
|
||||||
serial7 = &uart7;
|
|
||||||
serial8 = &uart8;
|
|
||||||
serial9 = &uart9;
|
|
||||||
};
|
|
||||||
|
|
||||||
cpus {
|
|
||||||
#address-cells = <2>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
|
|
||||||
cpu0: cpu@0 {
|
|
||||||
device_type = "cpu";
|
|
||||||
compatible = "arm,cortex-a55";
|
|
||||||
reg = <0x0 0x0>;
|
|
||||||
clocks = <&scmi_clk 0>;
|
|
||||||
enable-method = "psci";
|
|
||||||
operating-points-v2 = <&cpu0_opp_table>;
|
|
||||||
};
|
|
||||||
|
|
||||||
cpu1: cpu@100 {
|
|
||||||
device_type = "cpu";
|
|
||||||
compatible = "arm,cortex-a55";
|
|
||||||
reg = <0x0 0x100>;
|
|
||||||
enable-method = "psci";
|
|
||||||
operating-points-v2 = <&cpu0_opp_table>;
|
|
||||||
};
|
|
||||||
|
|
||||||
cpu2: cpu@200 {
|
|
||||||
device_type = "cpu";
|
|
||||||
compatible = "arm,cortex-a55";
|
|
||||||
reg = <0x0 0x200>;
|
|
||||||
enable-method = "psci";
|
|
||||||
operating-points-v2 = <&cpu0_opp_table>;
|
|
||||||
};
|
|
||||||
|
|
||||||
cpu3: cpu@300 {
|
|
||||||
device_type = "cpu";
|
|
||||||
compatible = "arm,cortex-a55";
|
|
||||||
reg = <0x0 0x300>;
|
|
||||||
enable-method = "psci";
|
|
||||||
operating-points-v2 = <&cpu0_opp_table>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
cpu0_opp_table: cpu0-opp-table {
|
|
||||||
compatible = "operating-points-v2";
|
|
||||||
opp-shared;
|
|
||||||
|
|
||||||
opp-408000000 {
|
|
||||||
opp-hz = /bits/ 64 <408000000>;
|
|
||||||
opp-microvolt = <900000 900000 1150000>;
|
|
||||||
clock-latency-ns = <40000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
opp-600000000 {
|
|
||||||
opp-hz = /bits/ 64 <600000000>;
|
|
||||||
opp-microvolt = <900000 900000 1150000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
opp-816000000 {
|
|
||||||
opp-hz = /bits/ 64 <816000000>;
|
|
||||||
opp-microvolt = <900000 900000 1150000>;
|
|
||||||
opp-suspend;
|
|
||||||
};
|
|
||||||
|
|
||||||
opp-1104000000 {
|
|
||||||
opp-hz = /bits/ 64 <1104000000>;
|
|
||||||
opp-microvolt = <900000 900000 1150000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
opp-1416000000 {
|
|
||||||
opp-hz = /bits/ 64 <1416000000>;
|
|
||||||
opp-microvolt = <900000 900000 1150000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
opp-1608000000 {
|
|
||||||
opp-hz = /bits/ 64 <1608000000>;
|
|
||||||
opp-microvolt = <975000 975000 1150000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
opp-1800000000 {
|
|
||||||
opp-hz = /bits/ 64 <1800000000>;
|
|
||||||
opp-microvolt = <1050000 1050000 1150000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
opp-1992000000 {
|
|
||||||
opp-hz = /bits/ 64 <1992000000>;
|
|
||||||
opp-microvolt = <1150000 1150000 1150000>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
firmware {
|
|
||||||
scmi: scmi {
|
|
||||||
compatible = "arm,scmi-smc";
|
|
||||||
arm,smc-id = <0x82000010>;
|
|
||||||
shmem = <&scmi_shmem>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
|
|
||||||
scmi_clk: protocol@14 {
|
|
||||||
reg = <0x14>;
|
|
||||||
#clock-cells = <1>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
pmu {
|
|
||||||
compatible = "arm,cortex-a55-pmu";
|
|
||||||
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
|
||||||
};
|
|
||||||
|
|
||||||
psci {
|
|
||||||
compatible = "arm,psci-1.0";
|
|
||||||
method = "smc";
|
|
||||||
};
|
|
||||||
|
|
||||||
timer {
|
|
||||||
compatible = "arm,armv8-timer";
|
|
||||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
arm,no-tick-in-suspend;
|
|
||||||
};
|
|
||||||
|
|
||||||
xin24m: xin24m {
|
|
||||||
compatible = "fixed-clock";
|
|
||||||
clock-frequency = <24000000>;
|
|
||||||
clock-output-names = "xin24m";
|
|
||||||
#clock-cells = <0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
xin32k: xin32k {
|
|
||||||
compatible = "fixed-clock";
|
|
||||||
clock-frequency = <32768>;
|
|
||||||
clock-output-names = "xin32k";
|
|
||||||
pinctrl-0 = <&clk32k_out0>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
#clock-cells = <0>;
|
|
||||||
};
|
|
||||||
|
|
||||||
sram@10f000 {
|
|
||||||
compatible = "mmio-sram";
|
|
||||||
reg = <0x0 0x0010f000 0x0 0x100>;
|
|
||||||
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
ranges = <0 0x0 0x0010f000 0x100>;
|
|
||||||
|
|
||||||
scmi_shmem: sram@0 {
|
|
||||||
compatible = "arm,scmi-shmem";
|
|
||||||
reg = <0x0 0x100>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
gic: interrupt-controller@fd400000 {
|
|
||||||
compatible = "arm,gic-v3";
|
|
||||||
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
|
||||||
<0x0 0xfd460000 0 0x80000>; /* GICR */
|
|
||||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
interrupt-controller;
|
|
||||||
#interrupt-cells = <3>;
|
|
||||||
mbi-alias = <0x0 0xfd100000>;
|
|
||||||
mbi-ranges = <296 24>;
|
|
||||||
msi-controller;
|
|
||||||
};
|
|
||||||
|
|
||||||
pmugrf: syscon@fdc20000 {
|
|
||||||
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
|
||||||
reg = <0x0 0xfdc20000 0x0 0x10000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
grf: syscon@fdc60000 {
|
|
||||||
compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
|
|
||||||
reg = <0x0 0xfdc60000 0x0 0x10000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
pmucru: clock-controller@fdd00000 {
|
|
||||||
compatible = "rockchip,rk3568-pmucru";
|
|
||||||
reg = <0x0 0xfdd00000 0x0 0x1000>;
|
|
||||||
#clock-cells = <1>;
|
|
||||||
#reset-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
cru: clock-controller@fdd20000 {
|
|
||||||
compatible = "rockchip,rk3568-cru";
|
|
||||||
reg = <0x0 0xfdd20000 0x0 0x1000>;
|
|
||||||
#clock-cells = <1>;
|
|
||||||
#reset-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
i2c0: i2c@fdd40000 {
|
|
||||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
||||||
reg = <0x0 0xfdd40000 0x0 0x1000>;
|
|
||||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
|
|
||||||
clock-names = "i2c", "pclk";
|
|
||||||
pinctrl-0 = <&i2c0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
uart0: serial@fdd50000 {
|
pipe_phy_grf0: syscon@fdc70000 {
|
||||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
|
||||||
reg = <0x0 0xfdd50000 0x0 0x100>;
|
reg = <0x0 0xfdc70000 0x0 0x1000>;
|
||||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
|
|
||||||
clock-names = "baudclk", "apb_pclk";
|
|
||||||
dmas = <&dmac0 0>, <&dmac0 1>;
|
|
||||||
pinctrl-0 = <&uart0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reg-io-width = <4>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
};
|
||||||
|
|
||||||
pwm0: pwm@fdd70000 {
|
qos_pcie3x1: qos@fe190080 {
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
compatible = "rockchip,rk3568-qos", "syscon";
|
||||||
reg = <0x0 0xfdd70000 0x0 0x10>;
|
reg = <0x0 0xfe190080 0x0 0x20>;
|
||||||
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm0m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
};
|
||||||
|
|
||||||
pwm1: pwm@fdd70010 {
|
qos_pcie3x2: qos@fe190100 {
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
compatible = "rockchip,rk3568-qos", "syscon";
|
||||||
reg = <0x0 0xfdd70010 0x0 0x10>;
|
reg = <0x0 0xfe190100 0x0 0x20>;
|
||||||
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm1m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
};
|
||||||
|
|
||||||
pwm2: pwm@fdd70020 {
|
qos_sata0: qos@fe190200 {
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
compatible = "rockchip,rk3568-qos", "syscon";
|
||||||
reg = <0x0 0xfdd70020 0x0 0x10>;
|
reg = <0x0 0xfe190200 0x0 0x20>;
|
||||||
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm2m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
};
|
||||||
|
|
||||||
pwm3: pwm@fdd70030 {
|
gmac0: ethernet@fe2a0000 {
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
||||||
reg = <0x0 0xfdd70030 0x0 0x10>;
|
reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
||||||
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
clock-names = "pwm", "pclk";
|
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
pinctrl-0 = <&pwm3_pins>;
|
interrupt-names = "macirq", "eth_wake_irq";
|
||||||
pinctrl-names = "active";
|
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||||
#pwm-cells = <3>;
|
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||||
status = "disabled";
|
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||||
};
|
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
|
||||||
|
clock-names = "stmmaceth", "mac_clk_rx",
|
||||||
sdmmc2: mmc@fe000000 {
|
"mac_clk_tx", "clk_mac_refout",
|
||||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
"aclk_mac", "pclk_mac",
|
||||||
reg = <0x0 0xfe000000 0x0 0x4000>;
|
"clk_mac_speed", "ptp_ref";
|
||||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
resets = <&cru SRST_A_GMAC0>;
|
||||||
clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
|
reset-names = "stmmaceth";
|
||||||
<&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
|
|
||||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
||||||
fifo-depth = <0x100>;
|
|
||||||
max-frequency = <150000000>;
|
|
||||||
resets = <&cru SRST_SDMMC2>;
|
|
||||||
reset-names = "reset";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
sdmmc0: mmc@fe2b0000 {
|
|
||||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
||||||
reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
|
||||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
|
|
||||||
<&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
|
|
||||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
||||||
fifo-depth = <0x100>;
|
|
||||||
max-frequency = <150000000>;
|
|
||||||
resets = <&cru SRST_SDMMC0>;
|
|
||||||
reset-names = "reset";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
sdmmc1: mmc@fe2c0000 {
|
|
||||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
||||||
reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
|
||||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
|
|
||||||
<&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
|
|
||||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
||||||
fifo-depth = <0x100>;
|
|
||||||
max-frequency = <150000000>;
|
|
||||||
resets = <&cru SRST_SDMMC1>;
|
|
||||||
reset-names = "reset";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
sdhci: mmc@fe310000 {
|
|
||||||
compatible = "rockchip,rk3568-dwcmshc";
|
|
||||||
reg = <0x0 0xfe310000 0x0 0x10000>;
|
|
||||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
|
|
||||||
assigned-clock-rates = <200000000>, <24000000>;
|
|
||||||
clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
|
|
||||||
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
|
||||||
<&cru TCLK_EMMC>;
|
|
||||||
clock-names = "core", "bus", "axi", "block", "timer";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
dmac0: dmac@fe530000 {
|
|
||||||
compatible = "arm,pl330", "arm,primecell";
|
|
||||||
reg = <0x0 0xfe530000 0x0 0x4000>;
|
|
||||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
arm,pl330-periph-burst;
|
|
||||||
clocks = <&cru ACLK_BUS>;
|
|
||||||
clock-names = "apb_pclk";
|
|
||||||
#dma-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
dmac1: dmac@fe550000 {
|
|
||||||
compatible = "arm,pl330", "arm,primecell";
|
|
||||||
reg = <0x0 0xfe550000 0x0 0x4000>;
|
|
||||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
||||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
arm,pl330-periph-burst;
|
|
||||||
clocks = <&cru ACLK_BUS>;
|
|
||||||
clock-names = "apb_pclk";
|
|
||||||
#dma-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
i2c1: i2c@fe5a0000 {
|
|
||||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
||||||
reg = <0x0 0xfe5a0000 0x0 0x1000>;
|
|
||||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
|
||||||
clock-names = "i2c", "pclk";
|
|
||||||
pinctrl-0 = <&i2c1_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
i2c2: i2c@fe5b0000 {
|
|
||||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
||||||
reg = <0x0 0xfe5b0000 0x0 0x1000>;
|
|
||||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
|
||||||
clock-names = "i2c", "pclk";
|
|
||||||
pinctrl-0 = <&i2c2m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
i2c3: i2c@fe5c0000 {
|
|
||||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
||||||
reg = <0x0 0xfe5c0000 0x0 0x1000>;
|
|
||||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
|
||||||
clock-names = "i2c", "pclk";
|
|
||||||
pinctrl-0 = <&i2c3m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
i2c4: i2c@fe5d0000 {
|
|
||||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
||||||
reg = <0x0 0xfe5d0000 0x0 0x1000>;
|
|
||||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
|
||||||
clock-names = "i2c", "pclk";
|
|
||||||
pinctrl-0 = <&i2c4m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
i2c5: i2c@fe5e0000 {
|
|
||||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
||||||
reg = <0x0 0xfe5e0000 0x0 0x1000>;
|
|
||||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
|
||||||
clock-names = "i2c", "pclk";
|
|
||||||
pinctrl-0 = <&i2c5m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
wdt: watchdog@fe600000 {
|
|
||||||
compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
|
|
||||||
reg = <0x0 0xfe600000 0x0 0x100>;
|
|
||||||
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
|
|
||||||
clock-names = "tclk", "pclk";
|
|
||||||
};
|
|
||||||
|
|
||||||
uart1: serial@fe650000 {
|
|
||||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
||||||
reg = <0x0 0xfe650000 0x0 0x100>;
|
|
||||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
||||||
clock-names = "baudclk", "apb_pclk";
|
|
||||||
dmas = <&dmac0 2>, <&dmac0 3>;
|
|
||||||
pinctrl-0 = <&uart1m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reg-io-width = <4>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
uart2: serial@fe660000 {
|
|
||||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
||||||
reg = <0x0 0xfe660000 0x0 0x100>;
|
|
||||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
||||||
clock-names = "baudclk", "apb_pclk";
|
|
||||||
dmas = <&dmac0 4>, <&dmac0 5>;
|
|
||||||
pinctrl-0 = <&uart2m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reg-io-width = <4>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
uart3: serial@fe670000 {
|
|
||||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
||||||
reg = <0x0 0xfe670000 0x0 0x100>;
|
|
||||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
||||||
clock-names = "baudclk", "apb_pclk";
|
|
||||||
dmas = <&dmac0 6>, <&dmac0 7>;
|
|
||||||
pinctrl-0 = <&uart3m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reg-io-width = <4>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
uart4: serial@fe680000 {
|
|
||||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
||||||
reg = <0x0 0xfe680000 0x0 0x100>;
|
|
||||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
||||||
clock-names = "baudclk", "apb_pclk";
|
|
||||||
dmas = <&dmac0 8>, <&dmac0 9>;
|
|
||||||
pinctrl-0 = <&uart4m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reg-io-width = <4>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
uart5: serial@fe690000 {
|
|
||||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
||||||
reg = <0x0 0xfe690000 0x0 0x100>;
|
|
||||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
|
||||||
clock-names = "baudclk", "apb_pclk";
|
|
||||||
dmas = <&dmac0 10>, <&dmac0 11>;
|
|
||||||
pinctrl-0 = <&uart5m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reg-io-width = <4>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
uart6: serial@fe6a0000 {
|
|
||||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
||||||
reg = <0x0 0xfe6a0000 0x0 0x100>;
|
|
||||||
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
|
||||||
clock-names = "baudclk", "apb_pclk";
|
|
||||||
dmas = <&dmac0 12>, <&dmac0 13>;
|
|
||||||
pinctrl-0 = <&uart6m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reg-io-width = <4>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
uart7: serial@fe6b0000 {
|
|
||||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
||||||
reg = <0x0 0xfe6b0000 0x0 0x100>;
|
|
||||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
|
||||||
clock-names = "baudclk", "apb_pclk";
|
|
||||||
dmas = <&dmac0 14>, <&dmac0 15>;
|
|
||||||
pinctrl-0 = <&uart7m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reg-io-width = <4>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
uart8: serial@fe6c0000 {
|
|
||||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
||||||
reg = <0x0 0xfe6c0000 0x0 0x100>;
|
|
||||||
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
|
||||||
clock-names = "baudclk", "apb_pclk";
|
|
||||||
dmas = <&dmac0 16>, <&dmac0 17>;
|
|
||||||
pinctrl-0 = <&uart8m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reg-io-width = <4>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
uart9: serial@fe6d0000 {
|
|
||||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
||||||
reg = <0x0 0xfe6d0000 0x0 0x100>;
|
|
||||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
|
||||||
clock-names = "baudclk", "apb_pclk";
|
|
||||||
dmas = <&dmac0 18>, <&dmac0 19>;
|
|
||||||
pinctrl-0 = <&uart9m0_xfer>;
|
|
||||||
pinctrl-names = "default";
|
|
||||||
reg-io-width = <4>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm4: pwm@fe6e0000 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe6e0000 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm4_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm5: pwm@fe6e0010 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe6e0010 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm5_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm6: pwm@fe6e0020 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe6e0020 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm6_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm7: pwm@fe6e0030 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe6e0030 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm7_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm8: pwm@fe6f0000 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe6f0000 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm8m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm9: pwm@fe6f0010 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe6f0010 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm9m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm10: pwm@fe6f0020 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe6f0020 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm10m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm11: pwm@fe6f0030 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe6f0030 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm11m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm12: pwm@fe700000 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe700000 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm12m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm13: pwm@fe700010 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe700010 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm13m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm14: pwm@fe700020 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe700020 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm14m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm15: pwm@fe700030 {
|
|
||||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
||||||
reg = <0x0 0xfe700030 0x0 0x10>;
|
|
||||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
||||||
clock-names = "pwm", "pclk";
|
|
||||||
pinctrl-0 = <&pwm15m0_pins>;
|
|
||||||
pinctrl-names = "active";
|
|
||||||
#pwm-cells = <3>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pinctrl: pinctrl {
|
|
||||||
compatible = "rockchip,rk3568-pinctrl";
|
|
||||||
rockchip,grf = <&grf>;
|
rockchip,grf = <&grf>;
|
||||||
rockchip,pmu = <&pmugrf>;
|
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||||
#address-cells = <2>;
|
snps,mixed-burst;
|
||||||
#size-cells = <2>;
|
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||||
ranges;
|
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||||
|
snps,tso;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
gpio0: gpio@fdd60000 {
|
mdio0: mdio {
|
||||||
compatible = "rockchip,gpio-bank";
|
compatible = "snps,dwmac-mdio";
|
||||||
reg = <0x0 0xfdd60000 0x0 0x100>;
|
#address-cells = <0x1>;
|
||||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
#size-cells = <0x0>;
|
||||||
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
|
|
||||||
gpio-controller;
|
|
||||||
#gpio-cells = <2>;
|
|
||||||
interrupt-controller;
|
|
||||||
#interrupt-cells = <2>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio1: gpio@fe740000 {
|
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||||
compatible = "rockchip,gpio-bank";
|
snps,blen = <0 0 0 0 16 8 4>;
|
||||||
reg = <0x0 0xfe740000 0x0 0x100>;
|
snps,rd_osr_lmt = <8>;
|
||||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
snps,wr_osr_lmt = <4>;
|
||||||
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
|
||||||
gpio-controller;
|
|
||||||
#gpio-cells = <2>;
|
|
||||||
interrupt-controller;
|
|
||||||
#interrupt-cells = <2>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio2: gpio@fe750000 {
|
gmac0_mtl_rx_setup: rx-queues-config {
|
||||||
compatible = "rockchip,gpio-bank";
|
snps,rx-queues-to-use = <1>;
|
||||||
reg = <0x0 0xfe750000 0x0 0x100>;
|
queue0 {};
|
||||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
|
||||||
gpio-controller;
|
|
||||||
#gpio-cells = <2>;
|
|
||||||
interrupt-controller;
|
|
||||||
#interrupt-cells = <2>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
gpio3: gpio@fe760000 {
|
gmac0_mtl_tx_setup: tx-queues-config {
|
||||||
compatible = "rockchip,gpio-bank";
|
snps,tx-queues-to-use = <1>;
|
||||||
reg = <0x0 0xfe760000 0x0 0x100>;
|
queue0 {};
|
||||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
|
||||||
gpio-controller;
|
|
||||||
#gpio-cells = <2>;
|
|
||||||
interrupt-controller;
|
|
||||||
#interrupt-cells = <2>;
|
|
||||||
};
|
};
|
||||||
|
};
|
||||||
|
|
||||||
gpio4: gpio@fe770000 {
|
combphy0: phy@fe820000 {
|
||||||
compatible = "rockchip,gpio-bank";
|
compatible = "rockchip,rk3568-naneng-combphy";
|
||||||
reg = <0x0 0xfe770000 0x0 0x100>;
|
reg = <0x0 0xfe820000 0x0 0x100>;
|
||||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
clocks = <&pmucru CLK_PCIEPHY0_REF>,
|
||||||
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
<&cru PCLK_PIPEPHY0>,
|
||||||
gpio-controller;
|
<&cru PCLK_PIPE>;
|
||||||
#gpio-cells = <2>;
|
clock-names = "ref", "apb", "pipe";
|
||||||
interrupt-controller;
|
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
||||||
#interrupt-cells = <2>;
|
assigned-clock-rates = <100000000>;
|
||||||
};
|
resets = <&cru SRST_PIPEPHY0>;
|
||||||
|
rockchip,pipe-grf = <&pipegrf>;
|
||||||
|
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
|
||||||
|
#phy-cells = <1>;
|
||||||
|
status = "disabled";
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
#include "rk3568-pinctrl.dtsi"
|
&cpu0_opp_table {
|
||||||
|
opp-1992000000 {
|
||||||
|
opp-hz = /bits/ 64 <1992000000>;
|
||||||
|
opp-microvolt = <1150000 1150000 1150000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&pipegrf {
|
||||||
|
compatible = "rockchip,rk3568-pipe-grf", "syscon";
|
||||||
|
};
|
||||||
|
|
||||||
|
&power {
|
||||||
|
power-domain@RK3568_PD_PIPE {
|
||||||
|
reg = <RK3568_PD_PIPE>;
|
||||||
|
clocks = <&cru PCLK_PIPE>;
|
||||||
|
pm_qos = <&qos_pcie2x1>,
|
||||||
|
<&qos_pcie3x1>,
|
||||||
|
<&qos_pcie3x2>,
|
||||||
|
<&qos_sata0>,
|
||||||
|
<&qos_sata1>,
|
||||||
|
<&qos_sata2>,
|
||||||
|
<&qos_usb3_0>,
|
||||||
|
<&qos_usb3_1>;
|
||||||
|
#power-domain-cells = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_host0_xhci {
|
||||||
|
phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
|
||||||
|
phy-names = "usb2-phy", "usb3-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
&vop {
|
||||||
|
compatible = "rockchip,rk3568-vop";
|
||||||
|
};
|
||||||
|
|
|
||||||
|
|
@ -42,15 +42,12 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&sdhci {
|
||||||
|
u-boot,dm-spl;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
&sdmmc0 {
|
&sdmmc0 {
|
||||||
u-boot,dm-spl;
|
u-boot,dm-spl;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
&sdhci {
|
|
||||||
bus-width = <8>;
|
|
||||||
u-boot,dm-spl;
|
|
||||||
mmc-hs200-1_8v;
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
|
|
||||||
1706
arch/arm/dts/rk356x.dtsi
Normal file
1706
arch/arm/dts/rk356x.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -445,5 +445,24 @@ enum {
|
||||||
/* CRU_PMU_CLK_SEL0_CON */
|
/* CRU_PMU_CLK_SEL0_CON */
|
||||||
CLK_PMU_PCLK_DIV_SHIFT = 0,
|
CLK_PMU_PCLK_DIV_SHIFT = 0,
|
||||||
CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT,
|
CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT,
|
||||||
|
|
||||||
|
/* CRU_PMU_CLKSEL3_CON */
|
||||||
|
UART0_PLL_SEL_SHIFT = 14,
|
||||||
|
UART0_PLL_SEL_MASK = 3 << UART0_PLL_SEL_SHIFT,
|
||||||
|
UART0_PLL_SEL_GPLL = 0,
|
||||||
|
UART0_PLL_SEL_24M,
|
||||||
|
UART0_PLL_SEL_480M,
|
||||||
|
UART0_PLL_SEL_NPLL,
|
||||||
|
UART0_DIV_CON_SHIFT = 0,
|
||||||
|
UART0_DIV_CON_MASK = 0x1f << UART0_DIV_CON_SHIFT,
|
||||||
|
|
||||||
|
/* CRU_PMU_CLKSEL4_CON */
|
||||||
|
UART0_CLK_SEL_SHIFT = 14,
|
||||||
|
UART0_CLK_SEL_MASK = 3 << UART0_PLL_SEL_SHIFT,
|
||||||
|
UART0_CLK_SEL_UART0 = 0,
|
||||||
|
UART0_CLK_SEL_UART0_NP5,
|
||||||
|
UART0_CLK_SEL_UART0_FRAC,
|
||||||
|
UART0_DIVNP5_SHIFT = 0,
|
||||||
|
UART0_DIVNP5_MASK = 0x1f << UART0_DIVNP5_SHIFT,
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -41,6 +41,7 @@ struct mm_region *mem_map = px30_mem_map;
|
||||||
#define PMUGRF_BASE 0xff010000
|
#define PMUGRF_BASE 0xff010000
|
||||||
#define GRF_BASE 0xff140000
|
#define GRF_BASE 0xff140000
|
||||||
#define CRU_BASE 0xff2b0000
|
#define CRU_BASE 0xff2b0000
|
||||||
|
#define PMUCRU_BASE 0xff2bc000
|
||||||
#define VIDEO_PHY_BASE 0xff2e0000
|
#define VIDEO_PHY_BASE 0xff2e0000
|
||||||
#define SERVICE_CORE_ADDR 0xff508000
|
#define SERVICE_CORE_ADDR 0xff508000
|
||||||
#define DDR_FW_BASE 0xff534000
|
#define DDR_FW_BASE 0xff534000
|
||||||
|
|
@ -198,6 +199,21 @@ enum {
|
||||||
GPIO3A1_UART5_RX = 4,
|
GPIO3A1_UART5_RX = 4,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* PMUGRF_GPIO0BL_IOMUX */
|
||||||
|
enum {
|
||||||
|
GPIO0B3_SHIFT = 6,
|
||||||
|
GPIO0B3_MASK = 0x3 << GPIO0B3_SHIFT,
|
||||||
|
GPIO0B3_GPIO = 0,
|
||||||
|
GPIO0B3_UART0_RX,
|
||||||
|
GPIO0B3_PMU_DEBUG1,
|
||||||
|
|
||||||
|
GPIO0B2_SHIFT = 4,
|
||||||
|
GPIO0B2_MASK = 0x3 << GPIO0B2_SHIFT,
|
||||||
|
GPIO0B2_GPIO = 0,
|
||||||
|
GPIO0B2_UART0_TX,
|
||||||
|
GPIO0B2_PMU_DEBUG0,
|
||||||
|
};
|
||||||
|
|
||||||
/* PMUGRF_GPIO0CL_IOMUX */
|
/* PMUGRF_GPIO0CL_IOMUX */
|
||||||
enum {
|
enum {
|
||||||
GPIO0C1_SHIFT = 2,
|
GPIO0C1_SHIFT = 2,
|
||||||
|
|
@ -276,12 +292,16 @@ int arch_cpu_init(void)
|
||||||
void board_debug_uart_init(void)
|
void board_debug_uart_init(void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_DEBUG_UART_BASE) && \
|
#if defined(CONFIG_DEBUG_UART_BASE) && \
|
||||||
(CONFIG_DEBUG_UART_BASE == 0xff168000) && \
|
(((CONFIG_DEBUG_UART_BASE == 0xff168000) && \
|
||||||
(CONFIG_DEBUG_UART_CHANNEL != 1)
|
(CONFIG_DEBUG_UART_CHANNEL != 1)) || \
|
||||||
|
CONFIG_DEBUG_UART_BASE == 0xff030000)
|
||||||
static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
|
static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
|
||||||
#endif
|
#endif
|
||||||
static struct px30_grf * const grf = (void *)GRF_BASE;
|
static struct px30_grf * const grf = (void *)GRF_BASE;
|
||||||
static struct px30_cru * const cru = (void *)CRU_BASE;
|
static struct px30_cru * const cru = (void *)CRU_BASE;
|
||||||
|
#if defined(CONFIG_DEBUG_UART_BASE) && CONFIG_DEBUG_UART_BASE == 0xff030000
|
||||||
|
static struct px30_pmucru * const pmucru = (void *)PMUCRU_BASE;
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
|
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
|
||||||
/* uart_sel_clk default select 24MHz */
|
/* uart_sel_clk default select 24MHz */
|
||||||
|
|
@ -346,6 +366,19 @@ void board_debug_uart_init(void)
|
||||||
GPIO3A2_MASK | GPIO3A1_MASK,
|
GPIO3A2_MASK | GPIO3A1_MASK,
|
||||||
GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
|
GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
|
||||||
GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
|
GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
|
||||||
|
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff030000)
|
||||||
|
/* uart_sel_clk default select 24MHz */
|
||||||
|
rk_clrsetreg(&pmucru->pmu_clksel_con[3],
|
||||||
|
UART0_PLL_SEL_MASK | UART0_DIV_CON_MASK,
|
||||||
|
UART0_PLL_SEL_24M << UART0_PLL_SEL_SHIFT | 0);
|
||||||
|
rk_clrsetreg(&pmucru->pmu_clksel_con[4],
|
||||||
|
UART0_CLK_SEL_MASK,
|
||||||
|
UART0_CLK_SEL_UART0 << UART0_CLK_SEL_SHIFT);
|
||||||
|
|
||||||
|
rk_clrsetreg(&pmugrf->gpio0bl_iomux,
|
||||||
|
GPIO0B3_MASK | GPIO0B2_MASK,
|
||||||
|
GPIO0B3_UART0_RX << GPIO0B3_SHIFT |
|
||||||
|
GPIO0B2_UART0_TX << GPIO0B2_SHIFT);
|
||||||
#else
|
#else
|
||||||
/* GRF_IOFUNC_CON0 */
|
/* GRF_IOFUNC_CON0 */
|
||||||
enum {
|
enum {
|
||||||
|
|
|
||||||
|
|
@ -89,7 +89,6 @@ config TARGET_MIQI_RK3288
|
||||||
config TARGET_PHYCORE_RK3288
|
config TARGET_PHYCORE_RK3288
|
||||||
bool "phyCORE-RK3288"
|
bool "phyCORE-RK3288"
|
||||||
select BOARD_LATE_INIT
|
select BOARD_LATE_INIT
|
||||||
select SPL_BOARD_INIT if SPL
|
|
||||||
help
|
help
|
||||||
Add basic support for the PCM-947 carrier board, a RK3288 based
|
Add basic support for the PCM-947 carrier board, a RK3288 based
|
||||||
development board made by PHYTEC. This board works in a combination
|
development board made by PHYTEC. This board works in a combination
|
||||||
|
|
|
||||||
|
|
@ -15,6 +15,7 @@
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/arch-rockchip/bootrom.h>
|
#include <asm/arch-rockchip/bootrom.h>
|
||||||
#include <asm/arch-rockchip/clock.h>
|
#include <asm/arch-rockchip/clock.h>
|
||||||
|
#include <asm/arch-rockchip/cru.h>
|
||||||
#include <asm/arch-rockchip/gpio.h>
|
#include <asm/arch-rockchip/gpio.h>
|
||||||
#include <asm/arch-rockchip/grf_rk3399.h>
|
#include <asm/arch-rockchip/grf_rk3399.h>
|
||||||
#include <asm/arch-rockchip/hardware.h>
|
#include <asm/arch-rockchip/hardware.h>
|
||||||
|
|
@ -221,12 +222,17 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
|
||||||
"u-boot,spl-boot-device", boot_ofpath);
|
"u-boot,spl-boot-device", boot_ofpath);
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(SPL_GPIO)
|
|
||||||
static void rk3399_force_power_on_reset(void)
|
static void rk3399_force_power_on_reset(void)
|
||||||
{
|
{
|
||||||
ofnode node;
|
ofnode node;
|
||||||
struct gpio_desc sysreset_gpio;
|
struct gpio_desc sysreset_gpio;
|
||||||
|
|
||||||
|
if (!IS_ENABLED(CONFIG_SPL_GPIO)) {
|
||||||
|
debug("%s: trying to force a power-on reset but no GPIO "
|
||||||
|
"support in SPL!\n", __func__);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
debug("%s: trying to force a power-on reset\n", __func__);
|
debug("%s: trying to force a power-on reset\n", __func__);
|
||||||
|
|
||||||
node = ofnode_path("/config");
|
node = ofnode_path("/config");
|
||||||
|
|
@ -243,7 +249,6 @@ static void rk3399_force_power_on_reset(void)
|
||||||
|
|
||||||
dm_gpio_set_value(&sysreset_gpio, 1);
|
dm_gpio_set_value(&sysreset_gpio, 1);
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
|
|
||||||
void __weak led_setup(void)
|
void __weak led_setup(void)
|
||||||
{
|
{
|
||||||
|
|
@ -253,35 +258,37 @@ void spl_board_init(void)
|
||||||
{
|
{
|
||||||
led_setup();
|
led_setup();
|
||||||
|
|
||||||
#if defined(SPL_GPIO)
|
if (IS_ENABLED(CONFIG_SPL_GPIO)) {
|
||||||
struct rockchip_cru *cru = rockchip_get_cru();
|
struct rockchip_cru *cru = rockchip_get_cru();
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The RK3399 resets only 'almost all logic' (see also in the TRM
|
* The RK3399 resets only 'almost all logic' (see also in the
|
||||||
* "3.9.4 Global software reset"), when issuing a software reset.
|
* TRM "3.9.4 Global software reset"), when issuing a software
|
||||||
* This may cause issues during boot-up for some configurations of
|
* reset. This may cause issues during boot-up for some
|
||||||
* the application software stack.
|
* configurations of the application software stack.
|
||||||
*
|
*
|
||||||
* To work around this, we test whether the last reset reason was
|
* To work around this, we test whether the last reset reason
|
||||||
* a power-on reset and (if not) issue an overtemp-reset to reset
|
* was a power-on reset and (if not) issue an overtemp-reset to
|
||||||
* the entire module.
|
* reset the entire module.
|
||||||
*
|
*
|
||||||
* While this was previously fixed by modifying the various places
|
* While this was previously fixed by modifying the various
|
||||||
* that could generate a software reset (e.g. U-Boot's sysreset
|
* places that could generate a software reset (e.g. U-Boot's
|
||||||
* driver, the ATF or Linux), we now have it here to ensure that
|
* sysreset driver, the ATF or Linux), we now have it here to
|
||||||
* we no longer have to track this through the various components.
|
* ensure that we no longer have to track this through the
|
||||||
*/
|
* various components.
|
||||||
if (cru->glb_rst_st != 0)
|
*/
|
||||||
rk3399_force_power_on_reset();
|
if (cru->glb_rst_st != 0)
|
||||||
#endif
|
rk3399_force_power_on_reset();
|
||||||
|
}
|
||||||
|
|
||||||
#if defined(SPL_DM_REGULATOR)
|
if (IS_ENABLED(CONFIG_SPL_DM_REGULATOR)) {
|
||||||
/*
|
/*
|
||||||
* Turning the eMMC and SPI back on (if disabled via the Qseven
|
* Turning the eMMC and SPI back on (if disabled via the Qseven
|
||||||
* BIOS_ENABLE) signal is done through a always-on regulator).
|
* BIOS_ENABLE) signal is done through a always-on regulator).
|
||||||
*/
|
*/
|
||||||
if (regulators_enable_boot_on(false))
|
if (regulators_enable_boot_on(false))
|
||||||
debug("%s: Cannot enable boot on regulator\n", __func__);
|
debug("%s: Cannot enable boot on regulator\n",
|
||||||
#endif
|
__func__);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -19,8 +19,6 @@
|
||||||
#include <netdev.h>
|
#include <netdev.h>
|
||||||
#include <linux/bitops.h>
|
#include <linux/bitops.h>
|
||||||
#include "som.h"
|
#include "som.h"
|
||||||
#include <power/regulator.h>
|
|
||||||
#include <power/rk8xx_pmic.h>
|
|
||||||
|
|
||||||
static int valid_rk3288_som(struct rk3288_som *som)
|
static int valid_rk3288_som(struct rk3288_som *som)
|
||||||
{
|
{
|
||||||
|
|
@ -77,47 +75,3 @@ int rk3288_board_late_init(void)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SPL_BUILD
|
|
||||||
#if !defined(CONFIG_SPL_OF_PLATDATA)
|
|
||||||
static int phycore_init(void)
|
|
||||||
{
|
|
||||||
struct udevice *pmic;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
#if defined(CONFIG_SPL_POWER)
|
|
||||||
/* Increase USB input current to 2A */
|
|
||||||
ret = rk818_spl_configure_usb_input_current(pmic, 2000);
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
/* Close charger when USB lower then 3.26V */
|
|
||||||
ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void spl_board_init(void)
|
|
||||||
{
|
|
||||||
#if !defined(CONFIG_SPL_OF_PLATDATA)
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
|
|
||||||
ret = phycore_init();
|
|
||||||
if (ret) {
|
|
||||||
debug("Failed to set up phycore power settings: %d\n",
|
|
||||||
ret);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
|
||||||
|
|
@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h
|
||||||
F: configs/evb-rk3399_defconfig
|
F: configs/evb-rk3399_defconfig
|
||||||
F: configs/firefly-rk3399_defconfig
|
F: configs/firefly-rk3399_defconfig
|
||||||
|
|
||||||
|
EAIDK-610
|
||||||
|
M: Andy Yan <andy.yan@rock-chips.com>
|
||||||
|
S: Maintained
|
||||||
|
F: configs/eaidk-610-rk3399_defconfig
|
||||||
|
F: arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi
|
||||||
|
|
||||||
KHADAS-EDGE
|
KHADAS-EDGE
|
||||||
M: Nick Xie <nick@khadas.com>
|
M: Nick Xie <nick@khadas.com>
|
||||||
S: Maintained
|
S: Maintained
|
||||||
|
|
|
||||||
|
|
@ -15,9 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
||||||
config ENV_SIZE
|
config ENV_SIZE
|
||||||
default 0x4000
|
default 0x4000
|
||||||
|
|
||||||
config ENV_OFFSET
|
|
||||||
default 0x3fc000 if ENV_IS_IN_SPI_FLASH
|
|
||||||
|
|
||||||
choice
|
choice
|
||||||
prompt "Theobroma Systems RK3399-Q7 DDR Option"
|
prompt "Theobroma Systems RK3399-Q7 DDR Option"
|
||||||
default TARGET_PUMA_RK3399_RAM_DDR3_1333
|
default TARGET_PUMA_RK3399_RAM_DDR3_1333
|
||||||
|
|
|
||||||
|
|
@ -44,26 +44,16 @@ Compile the U-Boot
|
||||||
> cd ../u-boot
|
> cd ../u-boot
|
||||||
> make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all
|
> make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all
|
||||||
|
|
||||||
Package the image
|
|
||||||
=================
|
|
||||||
|
|
||||||
The SPL image for SD-Card/eMMC is readily available in idbloader.img at the
|
|
||||||
root of U-Boot after compilation.
|
|
||||||
|
|
||||||
Creating an SPL image for SPI-NOR:
|
|
||||||
> tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader-spi.img
|
|
||||||
|
|
||||||
Flash the image
|
Flash the image
|
||||||
===============
|
===============
|
||||||
|
|
||||||
Copy the SPL to offset 32k for SD/eMMC, offset 0 for NOR-Flash and the FIT
|
Copy u-boot-rockchip.bin to offset 32k for SD/eMMC.
|
||||||
image to offset 256k.
|
Copy u-boot-rockchip-spi.bin to offset 0 for NOR-flash.
|
||||||
|
|
||||||
SD-Card
|
SD-Card
|
||||||
-------
|
-------
|
||||||
|
|
||||||
> dd if=idbloader.img of=/dev/sdb seek=64
|
> dd if=u-boot-rockchip.bin of=/dev/sdb seek=64
|
||||||
> dd if=u-boot.itb of=/dev/sdb seek=512
|
|
||||||
|
|
||||||
eMMC
|
eMMC
|
||||||
----
|
----
|
||||||
|
|
@ -79,8 +69,7 @@ help of the Rockchip loader binary.
|
||||||
> ./tools/boot_merger RKBOOT/RK3399MINIALL.ini
|
> ./tools/boot_merger RKBOOT/RK3399MINIALL.ini
|
||||||
> cd ..
|
> cd ..
|
||||||
> ./rkdeveloptool db rkbin/rk3399_loader_v1.25.126.bin
|
> ./rkdeveloptool db rkbin/rk3399_loader_v1.25.126.bin
|
||||||
> ./rkdeveloptool wl 64 ../idbloader.img
|
> ./rkdeveloptool wl 64 ../u-boot-rockchip.bin
|
||||||
> ./rkdeveloptool wl 512 ../u-boot.itb
|
|
||||||
|
|
||||||
NOR-Flash
|
NOR-Flash
|
||||||
---------
|
---------
|
||||||
|
|
@ -97,5 +86,4 @@ help of the Rockchip loader binary.
|
||||||
> cd ..
|
> cd ..
|
||||||
> ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.25.114.bin
|
> ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.25.114.bin
|
||||||
> ./rkdeveloptool ef
|
> ./rkdeveloptool ef
|
||||||
> ./rkdeveloptool wl 0 ../idbloader-spi.img
|
> ./rkdeveloptool wl 0 ../u-boot-rockchip-spi.bin
|
||||||
> ./rkdeveloptool wl 512 ../u-boot.itb
|
|
||||||
|
|
|
||||||
|
|
@ -6,6 +6,7 @@
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <dm.h>
|
#include <dm.h>
|
||||||
#include <env.h>
|
#include <env.h>
|
||||||
|
#include <env_internal.h>
|
||||||
#include <init.h>
|
#include <init.h>
|
||||||
#include <log.h>
|
#include <log.h>
|
||||||
#include <misc.h>
|
#include <misc.h>
|
||||||
|
|
@ -77,18 +78,16 @@ static int setup_boottargets(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Only run, if booting from mmc1 (i.e. /mmc@fe320000) and
|
* Make the default boot medium between SD Card and eMMC, the one that
|
||||||
* only consider cases where the default boot-order first
|
* was used to load U-Boot proper. If SPI-NOR flash was used, keep
|
||||||
* tries to boot from mmc0 (eMMC) and then from mmc1
|
* original default order.
|
||||||
* (i.e. external SD).
|
|
||||||
*
|
|
||||||
* In other words: the SD card will be moved to earlier in the
|
|
||||||
* order, if U-Boot was also loaded from the SD-card.
|
|
||||||
*/
|
*/
|
||||||
if (!strcmp(boot_device, "/mmc@fe320000")) {
|
if (strcmp(boot_device, "/spi@ff1d0000/flash@0")) {
|
||||||
|
bool sd_booted = !strcmp(boot_device, "/mmc@fe320000");
|
||||||
char *mmc0, *mmc1;
|
char *mmc0, *mmc1;
|
||||||
|
|
||||||
debug("%s: booted from SD-Card\n", __func__);
|
debug("%s: booted from %s\n", __func__,
|
||||||
|
sd_booted ? "SD-Card" : "eMMC");
|
||||||
mmc0 = strstr(env, "mmc0");
|
mmc0 = strstr(env, "mmc0");
|
||||||
mmc1 = strstr(env, "mmc1");
|
mmc1 = strstr(env, "mmc1");
|
||||||
|
|
||||||
|
|
@ -98,10 +97,13 @@ static int setup_boottargets(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* If mmc0 comes first in the boot order, we need to change
|
* If mmc0 comes first in the boot order and U-Boot proper was
|
||||||
* the strings to make mmc1 first.
|
* loaded from mmc1, swap mmc0 and mmc1 in the list.
|
||||||
|
* If mmc1 comes first in the boot order and U-Boot proper was
|
||||||
|
* loaded from mmc0, swap mmc0 and mmc1 in the list.
|
||||||
*/
|
*/
|
||||||
if (mmc0 < mmc1) {
|
if ((mmc0 < mmc1 && sd_booted) ||
|
||||||
|
(mmc0 > mmc1 && !sd_booted)) {
|
||||||
mmc0[3] = '1';
|
mmc0[3] = '1';
|
||||||
mmc1[3] = '0';
|
mmc1[3] = '0';
|
||||||
debug("%s: set boot_targets to: %s\n", __func__, env);
|
debug("%s: set boot_targets to: %s\n", __func__, env);
|
||||||
|
|
@ -112,6 +114,64 @@ static int setup_boottargets(void)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int mmc_get_env_dev(void)
|
||||||
|
{
|
||||||
|
const char *boot_device =
|
||||||
|
ofnode_read_chosen_string("u-boot,spl-boot-device");
|
||||||
|
|
||||||
|
if (!boot_device) {
|
||||||
|
debug("%s: /chosen/u-boot,spl-boot-device not set\n",
|
||||||
|
__func__);
|
||||||
|
return CONFIG_SYS_MMC_ENV_DEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
debug("%s: booted from %s\n", __func__, boot_device);
|
||||||
|
|
||||||
|
if (!strcmp(boot_device, "/mmc@fe320000"))
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
if (!strcmp(boot_device, "/mmc@fe330000"))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return CONFIG_SYS_MMC_ENV_DEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if !IS_ENABLED(CONFIG_ENV_IS_NOWHERE)
|
||||||
|
#error Please enable CONFIG_ENV_IS_NOWHERE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
enum env_location arch_env_get_location(enum env_operation op, int prio)
|
||||||
|
{
|
||||||
|
const char *boot_device =
|
||||||
|
ofnode_read_chosen_string("u-boot,spl-boot-device");
|
||||||
|
|
||||||
|
if (prio > 0)
|
||||||
|
return ENVL_UNKNOWN;
|
||||||
|
|
||||||
|
if (!boot_device) {
|
||||||
|
debug("%s: /chosen/u-boot,spl-boot-device not set\n",
|
||||||
|
__func__);
|
||||||
|
return ENVL_NOWHERE;
|
||||||
|
}
|
||||||
|
|
||||||
|
debug("%s: booted from %s\n", __func__, boot_device);
|
||||||
|
|
||||||
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) &&
|
||||||
|
!strcmp(boot_device, "/spi@ff1d0000/flash@0"))
|
||||||
|
return ENVL_SPI_FLASH;
|
||||||
|
|
||||||
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) &&
|
||||||
|
(!strcmp(boot_device, "/mmc@fe320000") ||
|
||||||
|
!strcmp(boot_device, "/mmc@fe330000")))
|
||||||
|
return ENVL_MMC;
|
||||||
|
|
||||||
|
printf("%s: No environment available: booted from %s but U-Boot "
|
||||||
|
"config does not allow loading environment from it.",
|
||||||
|
__func__, boot_device);
|
||||||
|
|
||||||
|
return ENVL_NOWHERE;
|
||||||
|
}
|
||||||
|
|
||||||
int misc_init_r(void)
|
int misc_init_r(void)
|
||||||
{
|
{
|
||||||
const u32 cpuid_offset = 0x7;
|
const u32 cpuid_offset = 0x7;
|
||||||
|
|
@ -136,19 +196,3 @@ int misc_init_r(void)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SERIAL_TAG
|
|
||||||
void get_board_serial(struct tag_serialnr *serialnr)
|
|
||||||
{
|
|
||||||
char *serial_string;
|
|
||||||
u64 serial = 0;
|
|
||||||
|
|
||||||
serial_string = env_get("serial#");
|
|
||||||
|
|
||||||
if (serial_string)
|
|
||||||
serial = simple_strtoull(serial_string, NULL, 16);
|
|
||||||
|
|
||||||
serialnr->high = (u32)(serial >> 32);
|
|
||||||
serialnr->low = (u32)(serial & 0xffffffff);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
|
||||||
|
|
@ -95,6 +95,7 @@ CONFIG_REGULATOR_RK8XX=y
|
||||||
CONFIG_PWM_ROCKCHIP=y
|
CONFIG_PWM_ROCKCHIP=y
|
||||||
CONFIG_RAM=y
|
CONFIG_RAM=y
|
||||||
CONFIG_SPL_RAM=y
|
CONFIG_SPL_RAM=y
|
||||||
|
CONFIG_DM_RESET=y
|
||||||
CONFIG_DEBUG_UART_SHIFT=2
|
CONFIG_DEBUG_UART_SHIFT=2
|
||||||
CONFIG_ROCKCHIP_SERIAL=y
|
CONFIG_ROCKCHIP_SERIAL=y
|
||||||
CONFIG_SOUND=y
|
CONFIG_SOUND=y
|
||||||
|
|
|
||||||
61
configs/eaidk-610-rk3399_defconfig
Normal file
61
configs/eaidk-610-rk3399_defconfig
Normal file
|
|
@ -0,0 +1,61 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||||
|
CONFIG_COUNTER_FREQUENCY=24000000
|
||||||
|
CONFIG_ARCH_ROCKCHIP=y
|
||||||
|
CONFIG_SYS_TEXT_BASE=0x00200000
|
||||||
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
CONFIG_ENV_OFFSET=0x3F8000
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="rk3399-eaidk-610"
|
||||||
|
CONFIG_ROCKCHIP_RK3399=y
|
||||||
|
CONFIG_TARGET_EVB_RK3399=y
|
||||||
|
CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||||
|
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||||
|
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||||
|
CONFIG_DEBUG_UART=y
|
||||||
|
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||||
|
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
||||||
|
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb"
|
||||||
|
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||||
|
CONFIG_SPL_MAX_SIZE=0x2e000
|
||||||
|
CONFIG_SPL_PAD_TO=0x7f8000
|
||||||
|
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||||
|
CONFIG_SPL_BSS_START_ADDR=0x400000
|
||||||
|
CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||||
|
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||||
|
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||||
|
CONFIG_SPL_STACK=0x400000
|
||||||
|
CONFIG_SPL_STACK_R=y
|
||||||
|
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||||
|
CONFIG_TPL=y
|
||||||
|
CONFIG_CMD_BOOTZ=y
|
||||||
|
CONFIG_CMD_GPT=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_USB=y
|
||||||
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
|
CONFIG_CMD_TIME=y
|
||||||
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||||
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
|
CONFIG_ROCKCHIP_GPIO=y
|
||||||
|
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||||
|
CONFIG_MMC_DW=y
|
||||||
|
CONFIG_MMC_DW_ROCKCHIP=y
|
||||||
|
CONFIG_MMC_SDHCI=y
|
||||||
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||||
|
CONFIG_ETH_DESIGNWARE=y
|
||||||
|
CONFIG_GMAC_ROCKCHIP=y
|
||||||
|
CONFIG_PMIC_RK8XX=y
|
||||||
|
CONFIG_REGULATOR_PWM=y
|
||||||
|
CONFIG_REGULATOR_RK8XX=y
|
||||||
|
CONFIG_PWM_ROCKCHIP=y
|
||||||
|
CONFIG_BAUDRATE=1500000
|
||||||
|
CONFIG_DEBUG_UART_SHIFT=2
|
||||||
|
CONFIG_SYSRESET=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_USB_XHCI_HCD=y
|
||||||
|
CONFIG_USB_XHCI_DWC3=y
|
||||||
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
CONFIG_USB_EHCI_GENERIC=y
|
||||||
|
CONFIG_SPL_TINY_MEMSET=y
|
||||||
|
CONFIG_ERRNO_STR=y
|
||||||
|
|
@ -42,6 +42,7 @@ CONFIG_CMD_CACHE=y
|
||||||
CONFIG_CMD_TIME=y
|
CONFIG_CMD_TIME=y
|
||||||
CONFIG_CMD_PMIC=y
|
CONFIG_CMD_PMIC=y
|
||||||
CONFIG_CMD_REGULATOR=y
|
CONFIG_CMD_REGULATOR=y
|
||||||
|
# CONFIG_SPL_PARTITIONS is not set
|
||||||
# CONFIG_SPL_DOS_PARTITION is not set
|
# CONFIG_SPL_DOS_PARTITION is not set
|
||||||
# CONFIG_SPL_EFI_PARTITION is not set
|
# CONFIG_SPL_EFI_PARTITION is not set
|
||||||
CONFIG_SPL_OF_CONTROL=y
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
|
|
||||||
|
|
@ -7,9 +7,9 @@ CONFIG_SPL_GPIO=y
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
CONFIG_ENV_OFFSET=0x3F8000
|
CONFIG_ENV_OFFSET=0x3F8000
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
|
CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
|
||||||
CONFIG_SPL_TEXT_BASE=0xff8c2000
|
|
||||||
CONFIG_ROCKCHIP_RK3399=y
|
CONFIG_ROCKCHIP_RK3399=y
|
||||||
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
|
CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
|
||||||
|
CONFIG_ROCKCHIP_SPI_IMAGE=y
|
||||||
CONFIG_TARGET_PUMA_RK3399=y
|
CONFIG_TARGET_PUMA_RK3399=y
|
||||||
CONFIG_DEBUG_UART_BASE=0xFF180000
|
CONFIG_DEBUG_UART_BASE=0xFF180000
|
||||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||||
|
|
@ -31,12 +31,12 @@ CONFIG_SPL_BSS_MAX_SIZE=0x10000
|
||||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||||
CONFIG_SPL_STACK=0xff8effff
|
CONFIG_SPL_STACK=0xff8effff
|
||||||
CONFIG_SPL_STACK_R=y
|
CONFIG_SPL_STACK_R=y
|
||||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
|
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
|
||||||
CONFIG_SPL_I2C=y
|
CONFIG_SPL_I2C=y
|
||||||
CONFIG_SPL_POWER=y
|
CONFIG_SPL_POWER=y
|
||||||
CONFIG_SPL_SPI_LOAD=y
|
CONFIG_SPL_SPI_LOAD=y
|
||||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
|
CONFIG_TPL=y
|
||||||
CONFIG_CMD_BOOTZ=y
|
CONFIG_CMD_BOOTZ=y
|
||||||
CONFIG_CMD_GPT=y
|
CONFIG_CMD_GPT=y
|
||||||
CONFIG_CMD_I2C=y
|
CONFIG_CMD_I2C=y
|
||||||
|
|
@ -51,13 +51,18 @@ CONFIG_CMD_PMIC=y
|
||||||
CONFIG_CMD_REGULATOR=y
|
CONFIG_CMD_REGULATOR=y
|
||||||
CONFIG_SPL_OF_CONTROL=y
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
CONFIG_OF_LIVE=y
|
CONFIG_OF_LIVE=y
|
||||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||||
CONFIG_ENV_OVERWRITE=y
|
CONFIG_ENV_OVERWRITE=y
|
||||||
|
CONFIG_ENV_IS_NOWHERE=y
|
||||||
CONFIG_ENV_IS_IN_MMC=y
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||||
|
CONFIG_ENV_SPI_MAX_HZ=50000000
|
||||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
CONFIG_SYS_MMC_ENV_DEV=1
|
CONFIG_SYS_MMC_ENV_DEV=1
|
||||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
|
CONFIG_GPIO_HOG=y
|
||||||
|
CONFIG_SPL_GPIO_HOG=y
|
||||||
CONFIG_ROCKCHIP_GPIO=y
|
CONFIG_ROCKCHIP_GPIO=y
|
||||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||||
CONFIG_MISC=y
|
CONFIG_MISC=y
|
||||||
|
|
@ -80,10 +85,7 @@ CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||||
CONFIG_DM_PMIC_FAN53555=y
|
CONFIG_DM_PMIC_FAN53555=y
|
||||||
CONFIG_PMIC_RK8XX=y
|
CONFIG_PMIC_RK8XX=y
|
||||||
CONFIG_SPL_PMIC_RK8XX=y
|
CONFIG_SPL_PMIC_RK8XX=y
|
||||||
CONFIG_SPL_DM_REGULATOR=y
|
|
||||||
CONFIG_REGULATOR_PWM=y
|
CONFIG_REGULATOR_PWM=y
|
||||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
|
||||||
CONFIG_DM_REGULATOR_GPIO=y
|
|
||||||
CONFIG_REGULATOR_RK8XX=y
|
CONFIG_REGULATOR_RK8XX=y
|
||||||
CONFIG_PWM_ROCKCHIP=y
|
CONFIG_PWM_ROCKCHIP=y
|
||||||
CONFIG_DM_RESET=y
|
CONFIG_DM_RESET=y
|
||||||
|
|
|
||||||
|
|
@ -856,7 +856,7 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
|
||||||
switch (set_rate) {
|
switch (set_rate) {
|
||||||
case 50 * MHz:
|
case 50 * MHz:
|
||||||
dpll_cfg = (struct pll_div)
|
dpll_cfg = (struct pll_div)
|
||||||
{.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
|
{.refdiv = 2, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 6};
|
||||||
break;
|
break;
|
||||||
case 200 * MHz:
|
case 200 * MHz:
|
||||||
dpll_cfg = (struct pll_div)
|
dpll_cfg = (struct pll_div)
|
||||||
|
|
|
||||||
|
|
@ -23,7 +23,7 @@ config RAM_ROCKCHIP_DEBUG
|
||||||
initialization, configurations and etc.
|
initialization, configurations and etc.
|
||||||
|
|
||||||
config RAM_PX30_DDR4
|
config RAM_PX30_DDR4
|
||||||
bool "DDR3 support for Rockchip PX30"
|
bool "DDR4 support for Rockchip PX30"
|
||||||
depends on RAM_ROCKCHIP && ROCKCHIP_PX30
|
depends on RAM_ROCKCHIP && ROCKCHIP_PX30
|
||||||
help
|
help
|
||||||
This enables DDR4 sdram support instead of the default DDR3 support
|
This enables DDR4 sdram support instead of the default DDR3 support
|
||||||
|
|
|
||||||
32
include/dt-bindings/power/rk3568-power.h
Normal file
32
include/dt-bindings/power/rk3568-power.h
Normal file
|
|
@ -0,0 +1,32 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
|
||||||
|
#define __DT_BINDINGS_POWER_RK3568_POWER_H__
|
||||||
|
|
||||||
|
/* VD_CORE */
|
||||||
|
#define RK3568_PD_CPU_0 0
|
||||||
|
#define RK3568_PD_CPU_1 1
|
||||||
|
#define RK3568_PD_CPU_2 2
|
||||||
|
#define RK3568_PD_CPU_3 3
|
||||||
|
#define RK3568_PD_CORE_ALIVE 4
|
||||||
|
|
||||||
|
/* VD_PMU */
|
||||||
|
#define RK3568_PD_PMU 5
|
||||||
|
|
||||||
|
/* VD_NPU */
|
||||||
|
#define RK3568_PD_NPU 6
|
||||||
|
|
||||||
|
/* VD_GPU */
|
||||||
|
#define RK3568_PD_GPU 7
|
||||||
|
|
||||||
|
/* VD_LOGIC */
|
||||||
|
#define RK3568_PD_VI 8
|
||||||
|
#define RK3568_PD_VO 9
|
||||||
|
#define RK3568_PD_RGA 10
|
||||||
|
#define RK3568_PD_VPU 11
|
||||||
|
#define RK3568_PD_CENTER 12
|
||||||
|
#define RK3568_PD_RKVDEC 13
|
||||||
|
#define RK3568_PD_RKVENC 14
|
||||||
|
#define RK3568_PD_PIPE 15
|
||||||
|
#define RK3568_PD_LOGIC_ALIVE 16
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in a new issue