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SPEAr : nand driver support for SPEAr SoCs
SPEAr SoCs contain an FSMC controller which can be used to interface with a range of memories eg. NAND, SRAM, NOR. Currently, this driver supports interfacing FSMC with NAND memories Signed-off-by: Vipin <vipin.kumar@st.com>
This commit is contained in:
Vipin KUMAR
Tom Rix
parent
1ebdb24159
commit
13229557c1
3 changed files with 182 additions and 0 deletions
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@ -47,6 +47,7 @@ COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
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COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
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COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
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COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
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COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
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COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
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COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
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COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
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COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
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COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
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COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
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COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
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endif
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endif
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124
drivers/mtd/nand/spr_nand.c
Executable file
124
drivers/mtd/nand/spr_nand.c
Executable file
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@ -0,0 +1,124 @@
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_nand.h>
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static struct fsmc_regs *const fsmc_regs_p =
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(struct fsmc_regs *)CONFIG_SPEAR_FSMCBASE;
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static struct nand_ecclayout spear_nand_ecclayout = {
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.eccbytes = 24,
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.eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
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66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
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.oobfree = {
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{.offset = 8, .length = 8},
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{.offset = 24, .length = 8},
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{.offset = 40, .length = 8},
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{.offset = 56, .length = 8},
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{.offset = 72, .length = 8},
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{.offset = 88, .length = 8},
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{.offset = 104, .length = 8},
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{.offset = 120, .length = 8}
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}
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};
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static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
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{
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struct nand_chip *this = mtd->priv;
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ulong IO_ADDR_W;
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if (ctrl & NAND_CTRL_CHANGE) {
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IO_ADDR_W = (ulong)this->IO_ADDR_W;
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IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
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if (ctrl & NAND_CLE)
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IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
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if (ctrl & NAND_ALE)
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IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
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if (ctrl & NAND_NCE) {
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writel(readl(&fsmc_regs_p->genmemctrl_pc) |
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FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc);
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} else {
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writel(readl(&fsmc_regs_p->genmemctrl_pc) &
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~FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc);
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}
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this->IO_ADDR_W = (void *)IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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static int spear_read_hwecc(struct mtd_info *mtd,
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const u_char *data, u_char ecc[3])
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{
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u_int ecc_tmp;
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/* read the h/w ECC */
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ecc_tmp = readl(&fsmc_regs_p->genmemctrl_ecc);
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ecc[0] = (u_char) (ecc_tmp & 0xFF);
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ecc[1] = (u_char) ((ecc_tmp & 0xFF00) >> 8);
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ecc[2] = (u_char) ((ecc_tmp & 0xFF0000) >> 16);
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return 0;
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}
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void spear_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~0x80,
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&fsmc_regs_p->genmemctrl_pc);
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writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~FSMC_ECCEN,
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&fsmc_regs_p->genmemctrl_pc);
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writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_ECCEN,
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&fsmc_regs_p->genmemctrl_pc);
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}
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int spear_nand_init(struct nand_chip *nand)
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{
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writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
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&fsmc_regs_p->genmemctrl_pc);
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writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_TCLR_1 | FSMC_TAR_1,
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&fsmc_regs_p->genmemctrl_pc);
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writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
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&fsmc_regs_p->genmemctrl_comm);
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writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
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&fsmc_regs_p->genmemctrl_attrib);
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nand->options = 0;
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.layout = &spear_nand_ecclayout;
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nand->ecc.size = 512;
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nand->ecc.bytes = 3;
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nand->ecc.calculate = spear_read_hwecc;
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nand->ecc.hwctl = spear_enable_hwecc;
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nand->ecc.correct = nand_correct_data;
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nand->cmd_ctrl = spear_nand_hwcontrol;
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return 0;
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}
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57
include/asm-arm/arch-spear/spr_nand.h
Normal file
57
include/asm-arm/arch-spear/spr_nand.h
Normal file
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@ -0,0 +1,57 @@
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __SPR_NAND_H__
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#define __SPR_NAND_H__
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struct fsmc_regs {
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u32 reserved_1[0x10];
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u32 genmemctrl_pc;
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u32 reserved_2;
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u32 genmemctrl_comm;
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u32 genmemctrl_attrib;
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u32 reserved_3;
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u32 genmemctrl_ecc;
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};
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/* genmemctrl_pc register definitions */
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#define FSMC_RESET (1 << 0)
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#define FSMC_WAITON (1 << 1)
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#define FSMC_ENABLE (1 << 2)
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#define FSMC_DEVTYPE_NAND (1 << 3)
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#define FSMC_DEVWID_8 (0 << 4)
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#define FSMC_DEVWID_16 (1 << 4)
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#define FSMC_ECCEN (1 << 6)
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#define FSMC_ECCPLEN_512 (0 << 7)
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#define FSMC_ECCPLEN_256 (1 << 7)
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#define FSMC_TCLR_1 (1 << 9)
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#define FSMC_TAR_1 (1 << 13)
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/* genmemctrl_comm register definitions */
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#define FSMC_TSET_0 (0 << 0)
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#define FSMC_TWAIT_6 (6 << 8)
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#define FSMC_THOLD_4 (4 << 16)
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#define FSMC_THIZ_1 (1 << 24)
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extern int spear_nand_init(struct nand_chip *nand);
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#endif
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