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Revert "spi: add config option to enable the WP pin function on st micron flashes"

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This reverts commit 562f8df18d.

Note: Even un-reverting this patch couldn't works as expected, based
on the latest testing from Heiko Schocher.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
This commit is contained in:
Jagannadha Sutradharudu Teki 2015-04-23 19:52:11 +05:30
parent 9694b72442
commit 122d805fd4
3 changed files with 0 additions and 45 deletions
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11
README
View file

@ -3086,17 +3086,6 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line. memories can be connected with a given cs line.
Currently Xilinx Zynq qspi supports these type of connections. Currently Xilinx Zynq qspi supports these type of connections.
CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
enable the W#/Vpp signal to disable writing to the status
register on ST MICRON flashes like the N25Q128.
The status register write enable/disable bit, combined with
the W#/VPP signal provides hardware data protection for the
device as follows: When the enable/disable bit is set to 1,
and the W#/VPP signal is driven LOW, the status register
nonvolatile bits become read-only and the WRITE STATUS REGISTER
operation will not execute. The only way to exit this
hardware-protected mode is to drive W#/VPP HIGH.
- SystemACE Support: - SystemACE Support:
CONFIG_SYSTEMACE CONFIG_SYSTEMACE

4
drivers/mtd/spi/sf_internal.h
View file

@ -97,10 +97,6 @@ enum {
#define STATUS_QEB_MXIC (1 << 6) #define STATUS_QEB_MXIC (1 << 6)
#define STATUS_PEC (1 << 7) #define STATUS_PEC (1 << 7)
#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
#define STATUS_SRWD (1 << 7) /* SR write protect */
#endif
/* Flash timeout values */ /* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)

30
drivers/mtd/spi/sf_probe.c
View file

@ -288,34 +288,6 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
} }
#endif /* CONFIG_OF_CONTROL */ #endif /* CONFIG_OF_CONTROL */
#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
/* enable the W#/Vpp signal to disable writing to the status register */
static int spi_enable_wp_pin(struct spi_flash *flash)
{
u8 status;
int ret;
ret = spi_flash_cmd_read_status(flash, &status);
if (ret < 0)
return ret;
ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
if (ret < 0)
return ret;
ret = spi_flash_cmd_write_disable(flash);
if (ret < 0)
return ret;
return 0;
}
#else
static int spi_enable_wp_pin(struct spi_flash *flash)
{
return 0;
}
#endif
/** /**
* spi_flash_probe_slave() - Probe for a SPI flash device on a bus * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
* *
@ -394,8 +366,6 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
} }
#endif #endif
if (spi_enable_wp_pin(flash))
puts("Enable WP pin failed\n");
/* Release spi bus */ /* Release spi bus */
spi_release_bus(spi); spi_release_bus(spi);