Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-12-01 17:10:11 +00:00
Code Issues Projects Releases Packages Wiki Activity

spi: exynos: Minimise access to SPI FIFO level

Browse source 
Accessing SPI registers is slow, but access to the FIFO level register
in particular seems to be extraordinarily expensive (I measure up to
600ns). Perhaps it is required to synchronise with the SPI byte output
logic which might run at 1/8th of the 40MHz SPI speed (just a guess).

Reduce access to this register by filling up and emptying FIFOs
more completely, rather than just one word each time around the inner
loop.

Since the rxfifo value will now likely be much greater that what we read
before we fill the txfifo, we only fill the txfifo halfway. This is
because if the txfifo is empty, but the rxfifo has data in it, then writing
too much data to the txfifo may overflow the rxfifo as data arrives.

This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This commit is contained in:
Rajeshwari Shinde 2013-10-08 16:20:05 +05:30 committed by Jagannadha Sutradharudu Teki
parent 8d203afdd3
commit 120af1572a
1 changed files with 15 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
drivers/spi/exynos_spi.c
View file

@ -247,12 +247,14 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
/* Keep the fifos full/empty. */ /* Keep the fifos full/empty. */
spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl); spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
if (tx_lvl < spi_slave->fifo_size && out_bytes) { while (tx_lvl < spi_slave->fifo_size/2 && out_bytes) {
temp = txp ? *txp++ : 0xff; temp = txp ? *txp++ : 0xff;
writel(temp, &regs->tx_data); writel(temp, &regs->tx_data);
out_bytes--; out_bytes--;
tx_lvl++;
} }
if (rx_lvl > 0) { if (rx_lvl > 0) {
while (rx_lvl > 0) {
temp = readl(&regs->rx_data); temp = readl(&regs->rx_data);
if (spi_slave->skip_preamble) { if (spi_slave->skip_preamble) {
if (temp == SPI_PREAMBLE_END_BYTE) { if (temp == SPI_PREAMBLE_END_BYTE) {
@ -265,6 +267,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
in_bytes--; in_bytes--;
} }
toread--; toread--;
rx_lvl--;
} else if (!toread) { } else if (!toread) {
/* /*
* We have run out of input data, but haven't read * We have run out of input data, but haven't read