arm64: zynqmp: Add DT description for si5328 for zcu102/zcu106

Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu106 to cover latest
binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/db66a4bb501183ffbd033da4dd263afdb214f8ec.1652262769.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2022-05-11 11:52:54 +02:00 committed by Michal Simek
parent d5b9b22f7b
commit 11ed38f5dc
2 changed files with 40 additions and 2 deletions

View file

@ -604,7 +604,26 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <4>; reg = <4>;
/* SI5328 - u20 */ si5328: clock-generator@69 {/* SI5328 - u20 */
compatible = "silabs,si5328";
reg = <0x69>;
/*
* Chip has interrupt present connected to PL
* interrupt-parent = <&>;
* interrupts = <>;
*/
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&refhdmi>;
clock-names = "xtal";
clock-output-names = "si5328";
si5328_clk: clk0@0 {
reg = <0>;
clock-frequency = <27000000>;
};
};
}; };
/* 5 - 7 unconnected */ /* 5 - 7 unconnected */
}; };

View file

@ -593,7 +593,26 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <4>; reg = <4>;
/* SI5328 - u20 */ si5328: clock-generator@69 {/* SI5328 - u20 */
compatible = "silabs,si5328";
reg = <0x69>;
/*
* Chip has interrupt present connected to PL
* interrupt-parent = <&>;
* interrupts = <>;
*/
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&refhdmi>;
clock-names = "xtal";
clock-output-names = "si5328";
si5328_clk: clk0@0 {
reg = <0>;
clock-frequency = <27000000>;
};
};
}; };
i2c@5 { i2c@5 {
#address-cells = <1>; #address-cells = <1>;