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colibri-imx6: use dynamic DDR calibration

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Enable dynamic DDR calibration to have a reliable behavior on edge
temperatures conditions.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
This commit is contained in:
Francesco Dolcini 2021-08-31 11:46:05 +02:00 committed by Stefano Babic
parent fa0223a759
commit 1194d17117
2 changed files with 23 additions and 0 deletions
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22
board/toradex/colibri_imx6/colibri_imx6.c
View file

@ -997,9 +997,28 @@ static void ddr_init(int *table, int size)
writel(table[2 * i + 1], table[2 * i]); writel(table[2 * i + 1], table[2 * i]);
} }
/* Perform DDR DRAM calibration */
static void spl_dram_perform_cal(u8 dsize)
{
#ifdef CONFIG_MX6_DDRCAL
int err;
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = dsize,
};
err = mmdc_do_write_level_calibration(&ddr_sysinfo);
if (err)
printf("error %d from write level calibration\n", err);
err = mmdc_do_dqs_calibration(&ddr_sysinfo);
if (err)
printf("error %d from dqs calibration\n", err);
#endif
}
static void spl_dram_init(void) static void spl_dram_init(void)
{ {
int minc, maxc; int minc, maxc;
u8 dsize = 2;
switch (get_cpu_temp_grade(&minc, &maxc)) { switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_COMMERCIAL: case TEMP_COMMERCIAL:
@ -1009,6 +1028,7 @@ static void spl_dram_init(void)
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else { } else {
puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n"); puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
} }
break; break;
@ -1020,11 +1040,13 @@ static void spl_dram_init(void)
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else { } else {
puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n"); puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table)); ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
} }
break; break;
}; };
udelay(100); udelay(100);
spl_dram_perform_cal(dsize);
} }
static iomux_v3_cfg_t const gpio_reset_pad[] = { static iomux_v3_cfg_t const gpio_reset_pad[] = {

1
configs/colibri_imx6_defconfig
View file

@ -10,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x10010000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6DL=y CONFIG_MX6DL=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_COLIBRI_IMX6=y CONFIG_TARGET_COLIBRI_IMX6=y
CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C2=y