From 17b45e684af98c1cf37648ad05a98d500b367c5a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 28 Mar 2023 08:34:13 +1300 Subject: [PATCH 001/805] cli: Correct several bugs in cli_getch() This function does not behave as expected when unknown escape sequences are sent to it: - it fails to store (and thus echo) the last character of the invalid sequence - it fails to set esc_len to 0 when it finishes emitting the invalid sequence, meaning that the following character will appear to be part of a new escape sequence - it processes the first character of the rejected sequence as a valid character, just starting the sequence all over again The last two bugs conspire to produce an "impossible condition #876" message which is the main symptom of this behaviour. Fix these bugs and add a test to verify the behaviour. Signed-off-by: Simon Glass Reported-by: Heinrich Schuchardt --- common/cli_getch.c | 5 +++-- test/common/Makefile | 1 + test/common/cread.c | 48 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+), 2 deletions(-) create mode 100644 test/common/cread.c diff --git a/common/cli_getch.c b/common/cli_getch.c index 87c23edcf4..61d4cb261b 100644 --- a/common/cli_getch.c +++ b/common/cli_getch.c @@ -129,7 +129,7 @@ static int cli_ch_esc(struct cli_ch_state *cch, int ichar, *actp = act; - return act == ESC_CONVERTED ? ichar : 0; + return ichar; } int cli_ch_process(struct cli_ch_state *cch, int ichar) @@ -145,6 +145,7 @@ int cli_ch_process(struct cli_ch_state *cch, int ichar) return cch->esc_save[cch->emit_upto++]; cch->emit_upto = 0; cch->emitting = false; + cch->esc_len = 0; } return 0; } else if (ichar == -ETIMEDOUT) { @@ -185,7 +186,7 @@ int cli_ch_process(struct cli_ch_state *cch, int ichar) cch->esc_save[cch->esc_len++] = ichar; ichar = cch->esc_save[cch->emit_upto++]; cch->emitting = true; - break; + return ichar; case ESC_CONVERTED: /* valid escape sequence, return the resulting char */ cch->esc_len = 0; diff --git a/test/common/Makefile b/test/common/Makefile index cc918f64e5..a5ab10f6f6 100644 --- a/test/common/Makefile +++ b/test/common/Makefile @@ -3,3 +3,4 @@ obj-y += cmd_ut_common.o obj-$(CONFIG_AUTOBOOT) += test_autoboot.o obj-$(CONFIG_CYCLIC) += cyclic.o obj-$(CONFIG_EVENT) += event.o +obj-y += cread.o diff --git a/test/common/cread.c b/test/common/cread.c new file mode 100644 index 0000000000..3dce4bdb0e --- /dev/null +++ b/test/common/cread.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Google LLC + */ + +#include +#include +#include +#include +#include + +static int cli_ch_test(struct unit_test_state *uts) +{ + struct cli_ch_state s_cch, *cch = &s_cch; + + cli_ch_init(cch); + + /* should be nothing to return at first */ + ut_asserteq(0, cli_ch_process(cch, 0)); + + /* check normal entry */ + ut_asserteq('a', cli_ch_process(cch, 'a')); + ut_asserteq('b', cli_ch_process(cch, 'b')); + ut_asserteq('c', cli_ch_process(cch, 'c')); + ut_asserteq(0, cli_ch_process(cch, 0)); + + /* send an invalid escape sequence */ + ut_asserteq(0, cli_ch_process(cch, '\e')); + ut_asserteq(0, cli_ch_process(cch, '[')); + + /* + * with the next char it sees that the sequence is invalid, so starts + * emitting it + */ + ut_asserteq('\e', cli_ch_process(cch, 'X')); + + /* now we set 0 bytes to empty the buffer */ + ut_asserteq('[', cli_ch_process(cch, 0)); + ut_asserteq('X', cli_ch_process(cch, 0)); + ut_asserteq(0, cli_ch_process(cch, 0)); + + /* things are normal again */ + ut_asserteq('a', cli_ch_process(cch, 'a')); + ut_asserteq(0, cli_ch_process(cch, 0)); + + return 0; +} +COMMON_TEST(cli_ch_test, 0); From be0169f07e38b81dd96bca2e80610592d89f8550 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 28 Mar 2023 08:34:14 +1300 Subject: [PATCH 002/805] cli: Correct handling of invalid escape sequences in cread_line() The second call to cli_ch_process() is in the wrong place, meaning that the one of the characters of an invalid escape sequence is swallowed instead of being returned. Fix the bug and add a test to cover this. This behaviour matches that of the code before cli_getch() was introduced. This was verified on the commit before b08e9d4b66 i.e.: 7d850f85aad ("sandbox: Enable mmc command and legacy images") Signed-off-by: Simon Glass Reported-by: Heinrich Schuchardt --- common/cli_readline.c | 3 +-- include/cli.h | 4 ++-- test/common/cread.c | 45 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 48 insertions(+), 4 deletions(-) diff --git a/common/cli_readline.c b/common/cli_readline.c index 709e9c3d38..e83743e90c 100644 --- a/common/cli_readline.c +++ b/common/cli_readline.c @@ -284,10 +284,9 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len, } ichar = getcmd_getch(); + ichar = cli_ch_process(cch, ichar); } - ichar = cli_ch_process(cch, ichar); - /* ichar=0x0 when error occurs in U-Boot getc */ if (!ichar) continue; diff --git a/include/cli.h b/include/cli.h index c777c90313..094a6602d7 100644 --- a/include/cli.h +++ b/include/cli.h @@ -98,8 +98,8 @@ int cli_readline(const char *const prompt); * * @prompt: Prompt to display * @buffer: Place to put the line that is entered - * @timeout: Timeout in milliseconds, 0 if none - * Return: command line length excluding terminator, or -ve on error: of the + * @timeout: Timeout in seconds, 0 if none + * Return: command line length excluding terminator, or -ve on error: if the * timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout * parameter), then -2 is returned. If a break is detected (Ctrl-C) then * -1 is returned. diff --git a/test/common/cread.c b/test/common/cread.c index 3dce4bdb0e..2fdd29a265 100644 --- a/test/common/cread.c +++ b/test/common/cread.c @@ -46,3 +46,48 @@ static int cli_ch_test(struct unit_test_state *uts) return 0; } COMMON_TEST(cli_ch_test, 0); + +static int cread_test(struct unit_test_state *uts) +{ + int duration; + ulong start; + char buf[10]; + + /* + * useful for debugging + * + * gd->flags &= ~GD_FLG_RECORD; + * print_buffer(0, buf, 1, 7, 0); + */ + + console_record_reset_enable(); + + /* simple input */ + *buf = '\0'; + ut_asserteq(4, console_in_puts("abc\n")); + ut_asserteq(3, cli_readline_into_buffer("-> ", buf, 1)); + ut_asserteq_str("abc", buf); + + /* try an escape sequence (cursor left after the 'c') */ + *buf = '\0'; + ut_asserteq(8, console_in_puts("abc\e[Dx\n")); + ut_asserteq(4, cli_readline_into_buffer("-> ", buf, 1)); + ut_asserteq_str("abxc", buf); + + /* invalid escape sequence */ + *buf = '\0'; + ut_asserteq(8, console_in_puts("abc\e[Xx\n")); + ut_asserteq(7, cli_readline_into_buffer("-> ", buf, 1)); + ut_asserteq_str("abc\e[Xx", buf); + + /* check timeout, should be between 1000 and 1050ms */ + start = get_timer(0); + *buf = '\0'; + ut_asserteq(-2, cli_readline_into_buffer("-> ", buf, 1)); + duration = get_timer(start) - 1000; + ut_assert(duration >= 0); + ut_assert(duration < 50); + + return 0; +} +COMMON_TEST(cread_test, 0); From 565681e596381b5b6db59cf06931e698f2d829e5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 22 Mar 2023 16:59:31 -0300 Subject: [PATCH 003/805] imx6sx-udoo-neo-basic: Introduce the u-boot.dtsi After the conversion to DM_SERIAL in commit 01f372d8d62b ("udoo_neo: Select DM_SERIAL and drop iomux board level init") the SPL log is gone and the U-Boot proper log becomes incomplete: Core: 80 devices, 18 uclasses, devicetree: separate MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@2020000 Out: serial@2020000 Err: serial@2020000 Net: eth0: ethernet@2188000 Hit any key to stop autoboot: 0 Introduce the u-boot.dtsi file that passes the u-boot,dm-pre-reloc properties to the relevant nodes so that UART can be used early in SPL. With this change, the complete SPL and U-Boot messages are seen again. Signed-off-by: Fabio Estevam --- arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi diff --git a/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi b/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi new file mode 100644 index 0000000000..be755e125b --- /dev/null +++ b/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&soc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; From 49d8cc4cbe18c7ffdc7e9699b9b64545288ecb1f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 28 Mar 2023 10:47:37 +1300 Subject: [PATCH 004/805] buildman: Correct overwriting of settings file The toolchain test causes the settings file to be overwritten, which is annoying for local development. Fix it by passing None as the filename. Signed-off-by: Simon Glass --- tools/buildman/toolchain.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index ea1ad1bcb8..6bae913197 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -420,7 +420,7 @@ class Toolchains: Returns: Resolved string - >>> bsettings.Setup() + >>> bsettings.Setup(None) >>> tcs = Toolchains() >>> tcs.Add('fred', False) >>> var_dict = {'oblique' : 'OBLIQUE', 'first' : 'fi${second}rst', \ From a47164dfc1ef899ef9ddc6d8f2a17f0e9e90ef34 Mon Sep 17 00:00:00 2001 From: Jonathan Liu Date: Tue, 28 Mar 2023 17:44:23 +1100 Subject: [PATCH 005/805] sysreset: gpio: fix gpio_reboot_request return value It should return -EINPROGRESS if successful otherwise sysreset-uclass will continue to the next sysreset device. Signed-off-by: Jonathan Liu Reviewed-by: Simon Glass --- drivers/sysreset/sysreset_gpio.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/sysreset/sysreset_gpio.c b/drivers/sysreset/sysreset_gpio.c index dfca10ccc8..de42b59354 100644 --- a/drivers/sysreset/sysreset_gpio.c +++ b/drivers/sysreset/sysreset_gpio.c @@ -17,6 +17,7 @@ struct gpio_reboot_priv { static int gpio_reboot_request(struct udevice *dev, enum sysreset_t type) { struct gpio_reboot_priv *priv = dev_get_priv(dev); + int ret; /* * When debug log is enabled please make sure that chars won't end up @@ -26,7 +27,11 @@ static int gpio_reboot_request(struct udevice *dev, enum sysreset_t type) debug("GPIO reset\n"); /* Writing 1 respects polarity (active high/low) based on gpio->flags */ - return dm_gpio_set_value(&priv->gpio, 1); + ret = dm_gpio_set_value(&priv->gpio, 1); + if (ret < 0) + return ret; + + return -EINPROGRESS; } static struct sysreset_ops gpio_reboot_ops = { From d8aba36d741c01b1e1ea60f3bbbc33ae05fa2505 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 8 Feb 2023 09:15:39 +0100 Subject: [PATCH 006/805] configs: imx8mn_bsh_smm_s2: remove console from bootargs The Linux kernel device tree already specifies the device to be used for boot console output with a stdout-path property under /chosen. Commit 36b661dc919da ("Merge branch 'next'") re-added the console setting that commit bede82f750752 ("configs: imx8mn_bsh_smm_s2: remove console from bootargs") had previously removed. Fixes: 36b661dc919da ("Merge branch 'next'") Signed-off-by: Dario Binacchi Reviewed-by: Fabio Estevam --- include/configs/imx8mn_bsh_smm_s2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h index e97b8e871d..deeed9c2f5 100644 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@ -14,7 +14,7 @@ #include #define NANDARGS \ - "nandargs=setenv bootargs console=${console} " \ + "nandargs=setenv bootargs " \ "${optargs} " \ "mtdparts=${mtdparts} " \ "root=${nandroot} " \ From 854aaf9024fc70cae31672eb3db1583d8f88e94d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 26 Mar 2023 17:08:03 +0200 Subject: [PATCH 007/805] scsi: typo supporedt %s/supporedt/supported/ Fixes: edca8cf72130 ("Convert CONFIG_SCSI_AHCI_PLAT et al to Kconfig") Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- drivers/scsi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index ad484ce8e8..a8014129d3 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -26,7 +26,7 @@ config SCSI_AHCI_PLAT This is deprecated. An AHCI driver should be provided instead. config SYS_SCSI_MAX_SCSI_ID - int "Maximum supporedt SCSI ID" + int "Maximum supported SCSI ID" default 1 help Sets the maximum number of SCSI IDs to scan when looking for devices. From ffc1cfb8f4cbd2bd28be5877040821ccbda3e08b Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 26 Mar 2023 02:55:12 +0000 Subject: [PATCH 008/805] doc: describe skipping triggering a pipeline in Gitlab 'git push -o ci.skip' can be used to push to Gitlab without triggering a pipeline. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- doc/develop/ci_testing.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/doc/develop/ci_testing.rst b/doc/develop/ci_testing.rst index b9a9a516c1..ffaacedc3d 100644 --- a/doc/develop/ci_testing.rst +++ b/doc/develop/ci_testing.rst @@ -50,6 +50,12 @@ runners you are able to provide. While it is intended to be able to run this pipeline on the free public instances provided at https://gitlab.com/ a problem with our squashfs tests currently prevents this. +To push to Gitlab without triggering a pipeline use: + +.. code-block:: bash + + git push -o ci.skip + Docker container ---------------- From a9203b0fefca4627096779e4eb4b1efbea43ec35 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 26 Mar 2023 12:22:40 +0200 Subject: [PATCH 009/805] efi_loader: correct shortening of device-paths We use short device-paths in boot options so that a file on a block device can be found independent of the port into which the device is plugged. Usb() device-path nodes only contain port and interface information and therefore cannot identify a block device. UsbWwi() device-path nodes contain the serial number of USB devices. Signed-off-by: Heinrich Schuchardt --- include/efi_api.h | 1 + lib/efi_loader/efi_device_path.c | 21 ++++++--------------- 2 files changed, 7 insertions(+), 15 deletions(-) diff --git a/include/efi_api.h b/include/efi_api.h index c57868abbd..404e9a1171 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -610,6 +610,7 @@ struct efi_device_path_acpi_path { # define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR 0x0b # define DEVICE_PATH_SUB_TYPE_MSG_UART 0x0e # define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS 0x0f +# define DEVICE_PATH_SUB_TYPE_MSG_USB_WWI 0x10 # define DEVICE_PATH_SUB_TYPE_MSG_SATA 0x12 # define DEVICE_PATH_SUB_TYPE_MSG_NVME 0x17 # define DEVICE_PATH_SUB_TYPE_MSG_URI 0x18 diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index b6dd575b13..f35f673ce6 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -124,17 +124,13 @@ int efi_dp_match(const struct efi_device_path *a, /** * efi_dp_shorten() - shorten device-path * - * We can have device paths that start with a USB WWID or a USB Class node, - * and a few other cases which don't encode the full device path with bus - * hierarchy: + * When creating a short boot option we want to use a device-path that is + * independent of the location where the block device is plugged in. * - * * MESSAGING:USB_WWID - * * MESSAGING:USB_CLASS - * * MEDIA:FILE_PATH - * * MEDIA:HARD_DRIVE - * * MESSAGING:URI + * UsbWwi() nodes contain a serial number, hard drive paths a partition + * UUID. Both should be unique. * - * See UEFI spec (section 3.1.2, about short-form device-paths) + * See UEFI spec, section 3.1.2 for "short-form device path". * * @dp: original device-path * @Return: shortened device-path or NULL @@ -142,12 +138,7 @@ int efi_dp_match(const struct efi_device_path *a, struct efi_device_path *efi_dp_shorten(struct efi_device_path *dp) { while (dp) { - /* - * TODO: Add MESSAGING:USB_WWID and MESSAGING:URI.. - * in practice fallback.efi just uses MEDIA:HARD_DRIVE - * so not sure when we would see these other cases. - */ - if (EFI_DP_TYPE(dp, MESSAGING_DEVICE, MSG_USB) || + if (EFI_DP_TYPE(dp, MESSAGING_DEVICE, MSG_USB_WWI) || EFI_DP_TYPE(dp, MEDIA_DEVICE, HARD_DRIVE_PATH) || EFI_DP_TYPE(dp, MEDIA_DEVICE, FILE_PATH)) return dp; From dfd4288173245f0ea03df3e73cf62848c0212d98 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 1 Apr 2023 07:21:55 +0200 Subject: [PATCH 010/805] efi_loader: remove duplicate assignment Assigning the value of a variable to itself should be avoided. Addresses-Coverity-ID: 451089 ("Evaluation order violation") Fixes: 180b7118bed8 ("efi_loader: fix device-path for USB devices") Signed-off-by: Heinrich Schuchardt --- lib/efi_loader/efi_device_path.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index f35f673ce6..8a65dda883 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -740,7 +740,7 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev) #endif #if defined(CONFIG_USB) case UCLASS_MASS_STORAGE: { - struct blk_desc *desc = desc = dev_get_uclass_plat(dev); + struct blk_desc *desc = dev_get_uclass_plat(dev); struct efi_device_path_controller *dp = dp_fill(buf, dev->parent); From 86169cdcb0ec53c93e27f7a6c983c33862a1f616 Mon Sep 17 00:00:00 2001 From: David Sebek Date: Thu, 30 Mar 2023 17:51:14 -0400 Subject: [PATCH 011/805] rockchip: Fix incorrect constant name in RAM init code A condition in the rk3399 RAM initialization code used the old CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant. Reviewed-by: Simon Glass --- drivers/ram/rockchip/sdram_rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index b1fea04e84..963a05c244 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -2954,7 +2954,7 @@ static int sdram_init(struct dram_info *dram, params->ch[ch].cap_info.rank = rank; } -#if defined(CONFIG_RAM_RK3399_LPDDR4) +#if defined(CONFIG_RAM_ROCKCHIP_LPDDR4) /* LPDDR4 needs to be trained at 400MHz */ lpddr4_set_rate(dram, params, 0); params->base.ddr_freq = dfs_cfgs_lpddr4[0].base.ddr_freq / MHz; From 8b6de0545f2a33a8a28babef6cb91eb2bf7cccb6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 15 Feb 2023 15:24:44 -0300 Subject: [PATCH 012/805] pico-imx6: Pass the mmc alias to fix boot regression Originally, the mmc aliases node was present in imx6qdl-pico.dtsi. After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux"), the aliases node is gone as the upstream version does not have it. This causes a boot regression in which the eMMC card cannot be found anymore. Fix it by passing the alias node in the u-boot.dtsi file to restore the original behaviour where the eMMC (esdhc3) was mapped to mmc0. Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux") Signed-off-by: Fabio Estevam --- arch/arm/dts/imx6dl-pico-u-boot.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/arm/dts/imx6dl-pico-u-boot.dtsi diff --git a/arch/arm/dts/imx6dl-pico-u-boot.dtsi b/arch/arm/dts/imx6dl-pico-u-boot.dtsi new file mode 100644 index 0000000000..e2ef9bcc14 --- /dev/null +++ b/arch/arm/dts/imx6dl-pico-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +/ { + aliases { + mmc0 = &usdhc3; + }; +}; From 1f77f9176efeec2936763d61b6552c5c62860775 Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Mon, 3 Apr 2023 12:03:12 -0500 Subject: [PATCH 013/805] arm: dts: k3-j721e-sk-u-boot: fix boot on j721e SK J721e SK has been broken since at least March 2022. The main-navss and mcu-navss nodes were renamed and this caused the A72 SPL to fail early in the boot even before the serial port was enabled. Fix this. A later patch series between v2022.07 and v2022.10 additionally broke boot on this board by introducing hbmc nodes which are not present on this board. The right fix is to disable these by default in the SOC dtsi file, but for now we can also disable them in the u-boot dtsi. With both these fixed, we can now boot the j721e SK board fully from mainline u-boot. Fixes: 58d61fb5a77ef ("arm: dts: k3-j721e-sk: Add initial A72 specific dts support") Fixes: 297daac43afb9 ("arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node") Reported-by: Anand Gadiyar Signed-off-by: Sinthu Raja [gadiyar@ti.com: update commit description] Signed-off-by: Anand Gadiyar Cc: Bryan Brattlof --- arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi index 2d65e2db42..f529e7032a 100644 --- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi @@ -33,7 +33,7 @@ &cbass_main{ u-boot,dm-spl; - main_navss { + main_navss: bus@30000000 { u-boot,dm-spl; }; }; @@ -49,7 +49,7 @@ u-boot,dm-spl; }; - mcu-navss { + mcu_navss: bus@28380000 { u-boot,dm-spl; ringacc@2b800000 { @@ -237,6 +237,10 @@ u-boot,dm-spl; }; +&hbmc { + status = "disabled"; +}; + &ospi0 { u-boot,dm-spl; From fd4ed6b7e83ec3aea9a2ce21baea8ca9676f40dd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 3 Apr 2023 16:38:50 -0400 Subject: [PATCH 014/805] Prepare v2023.04 Signed-off-by: Tom Rini --- Makefile | 2 +- doc/develop/release_cycle.rst | 27 +- .../statistics/u-boot-stats-v2023.04.rst | 767 ++++++++++++++++++ 3 files changed, 783 insertions(+), 13 deletions(-) create mode 100644 doc/develop/statistics/u-boot-stats-v2023.04.rst diff --git a/Makefile b/Makefile index ab93f29fc5..af1408222d 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2023 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc5 +EXTRAVERSION = NAME = # *DOCUMENTATION* diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index ea584cef21..7d63cf483c 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -48,13 +48,14 @@ Examples:: Current Status -------------- -* U-Boot v2023.01 was released on Mon 09 January 2023. +* U-Boot v2023.04 was released on Mon 03 April 2023. -* The Merge Window for the next release (v2023.04) is **closed**. +* The Merge Window for the next release (v2023.07) is **open** until the -rc1 + release on Mon 24 April 2023. -* The next branch is now **open**. +* The next branch is now **closed**. -* Release "v2023.04" is scheduled for 03 April 2023. +* Release "v2023.07" is scheduled for 03 July 2023. Future Releases --------------- @@ -62,29 +63,29 @@ Future Releases .. The following commented out dates are for when release candidates are planned to be tagged. -For the next scheduled release, release candidates were made on:: +.. For the next scheduled release, release candidates were made on:: -* U-Boot v2023.04-rc1 was released on Mon 30 January 2023. +.. * U-Boot v2023.07-rc1 was released on Mon 24 April 2023. -* U-Boot v2023.04-rc2 was released on Mon 13 February 2023. +.. * U-Boot v2023.07-rc2 was released on Mon 08 May 2023. -* U-Boot v2023.04-rc3 was released on Mon 27 February 2023. +.. * U-Boot v2023.07-rc3 was released on Mon 22 May 2023. -* U-Boot v2023.04-rc4 was released on Mon 13 March 2023. +.. * U-Boot v2023.07-rc4 was released on Mon 05 June 2023. -* U-Boot v2023.04-rc5 was released on Mon 27 March 2023. +.. * U-Boot v2023.07-rc5 was released on Mon 19 June 2023. Please note that the following dates are planned only and may be deviated from as needed. -* "v2023.04": end of MW = Mon, Jan 30, 2022; release = Mon, Apr 03, 2023 - * "v2023.07": end of MW = Mon, Apr 24, 2023; release = Mon, Jul 03, 2023 * "v2023.10": end of MW = Mon, Jul 24, 2023; release = Mon, Oct 02, 2023 * "v2024.01": end of MW = Mon, Oct 23, 2023; release = Mon, Jan 08, 2024 +* "v2024.04": end of MW = Mon, Jan 29, 2024; release = Tue, Apr 02, 2024 + Previous Releases ----------------- @@ -92,6 +93,8 @@ Note: these statistics are generated by our fork of `gitdm `_, which was originally created by Jonathan Corbet. +* :doc:`statistics/u-boot-stats-v2023.04` which was released on 03 April 2023. + * :doc:`statistics/u-boot-stats-v2023.01` which was released on 09 January 2023. * :doc:`statistics/u-boot-stats-v2022.10` which was released on 03 October 2022. diff --git a/doc/develop/statistics/u-boot-stats-v2023.04.rst b/doc/develop/statistics/u-boot-stats-v2023.04.rst new file mode 100644 index 0000000000..57f2efc30e --- /dev/null +++ b/doc/develop/statistics/u-boot-stats-v2023.04.rst @@ -0,0 +1,767 @@ +:orphan: + +Release Statistics for U-Boot v2023.04 +====================================== + +* Processed 1691 changesets from 157 developers + +* 29 employers found + +* A total of 174471 lines added, 78380 removed (delta 96091) + +.. table:: Developers with the most changesets + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Simon Glass 381 (22.5%) + Tom Rini 333 (19.7%) + Marek Vasut 101 (6.0%) + Heinrich Schuchardt 70 (4.1%) + Jagan Teki 53 (3.1%) + Jonas Karlman 36 (2.1%) + Patrick Delaunay 35 (2.1%) + Hai Pham 21 (1.2%) + Michal Simek 20 (1.2%) + Maxim Cournoyer 20 (1.2%) + Svyatoslav Ryhel 17 (1.0%) + Sean Anderson 15 (0.9%) + Fabio Estevam 14 (0.8%) + Pali Rohár 14 (0.8%) + Sumit Garg 14 (0.8%) + Bryan Brattlof 14 (0.8%) + Sinthu Raja 13 (0.8%) + Andre Przywara 13 (0.8%) + Heiko Schocher 13 (0.8%) + Yu Chien Peter Lin 12 (0.7%) + Tim Harvey 12 (0.7%) + Peng Fan 12 (0.7%) + Tony Dinh 11 (0.7%) + Angelo Dureghello 11 (0.7%) + Masahisa Kojima 11 (0.7%) + Quentin Schulz 11 (0.7%) + Roger Quadros 11 (0.7%) + Marcel Ziswiler 11 (0.7%) + Holger Brunck 10 (0.6%) + Mark Kettenis 10 (0.6%) + Sergiu Moga 10 (0.6%) + Nikhil M Jain 9 (0.5%) + Jim Liu 9 (0.5%) + Christophe Leroy 9 (0.5%) + Balamanikandan Gunasundar 9 (0.5%) + Dario Binacchi 8 (0.5%) + Samuel Holland 8 (0.5%) + Frieder Schrempf 8 (0.5%) + Mikhail Ilin 8 (0.5%) + Sjoerd Simons 7 (0.4%) + Neil Armstrong 7 (0.4%) + Eugen Hristev 7 (0.4%) + Chris Morgan 7 (0.4%) + Dzmitry Sankouski 7 (0.4%) + Ioana Ciornei 7 (0.4%) + Ilias Apalodimas 6 (0.4%) + Peter Robinson 6 (0.4%) + Paweł Anikiel 6 (0.4%) + Andrejs Cainikovs 6 (0.4%) + Rob Herring 6 (0.4%) + John Keeping 5 (0.3%) + Mihai Sain 5 (0.3%) + Rick Chen 5 (0.3%) + Sergei Antonov 5 (0.3%) + Ashok Reddy Soma 5 (0.3%) + Algapally Santosh Sagar 5 (0.3%) + Dhruva Gole 5 (0.3%) + Brandon Maier 5 (0.3%) + Alexey Romanov 5 (0.3%) + Vasily Khoruzhick 4 (0.2%) + Manoj Sai 4 (0.2%) + Jan Kiszka 4 (0.2%) + Ovidiu Panait 4 (0.2%) + Takahiro Kuwano 4 (0.2%) + Enric Balletbo i Serra 4 (0.2%) + Fabrice Gasnier 4 (0.2%) + Victor Lim 4 (0.2%) + Stefan Bosch 4 (0.2%) + Vincent Stehlé 3 (0.2%) + Tam Nguyen 3 (0.2%) + Leo Yu-Chi Liang 3 (0.2%) + Mattijs Korpershoek 3 (0.2%) + Ye Li 3 (0.2%) + Oleksandr Suvorov 3 (0.2%) + Max Krummenacher 3 (0.2%) + Andrew Davis 3 (0.2%) + Michael Walle 3 (0.2%) + Andreas Kemnade 3 (0.2%) + Kshitiz Varshney 3 (0.2%) + Dai Okamura 3 (0.2%) + Stefan Roese 2 (0.1%) + Vincent Fazio 2 (0.1%) + Kamlesh Gurudasani 2 (0.1%) + Johan Jonker 2 (0.1%) + Antoine Mazeas 2 (0.1%) + Christopher Obbard 2 (0.1%) + Akash Gajjar 2 (0.1%) + Ilko Iliev 2 (0.1%) + Qu Wenruo 2 (0.1%) + Etienne Carriere 2 (0.1%) + Thomas Fitzsimmons 2 (0.1%) + Pei Yue Ho 2 (0.1%) + Ryan Chen 2 (0.1%) + Adam Ford 2 (0.1%) + Philippe Schenker 2 (0.1%) + Linus Walleij 2 (0.1%) + Sean Edmond 2 (0.1%) + Nikita Shubin 2 (0.1%) + Ying-Chun Liu (PaulLiu) 2 (0.1%) + Loic Poulain 2 (0.1%) + Pengfei Fan 2 (0.1%) + Jernej Skrabec 2 (0.1%) + Neha Malcom Francis 2 (0.1%) + Harald Seiler 2 (0.1%) + Shenlin Liang 2 (0.1%) + Martyn Welch 2 (0.1%) + Harini Katakam 2 (0.1%) + Marc Kleine-Budde 2 (0.1%) + David Sebek 1 (0.1%) + Jonathan Liu 1 (0.1%) + Vignesh Raghavendra 1 (0.1%) + Sebastian Andrzej Siewior 1 (0.1%) + annsai01 1 (0.1%) + Peter Geis 1 (0.1%) + Ralph Siemsen 1 (0.1%) + Robert Marko 1 (0.1%) + Michal Suchanek 1 (0.1%) + Jaehoon Chung 1 (0.1%) + Christian Kohlschütter 1 (0.1%) + Ramin Khonsari 1 (0.1%) + Maxim Schwalm 1 (0.1%) + Venkatesh Yadav Abbarapu 1 (0.1%) + Ivan Khoronzhuk 1 (0.1%) + Ulf Samuelsson 1 (0.1%) + Jade Lovelace 1 (0.1%) + Michael Trimarchi 1 (0.1%) + Matwey V. Kornilov 1 (0.1%) + KaDiWa 1 (0.1%) + Christian Marangi 1 (0.1%) + Ehsan Mohandesi 1 (0.1%) + Aurelien Jarno 1 (0.1%) + Mario Kicherer 1 (0.1%) + Arnaud Ferraris 1 (0.1%) + Detlev Casanova 1 (0.1%) + Igor Opaniuk 1 (0.1%) + Massimo Pegorer 1 (0.1%) + Kunihiko Hayashi 1 (0.1%) + Joost van Zwieten 1 (0.1%) + Jorge Ramirez-Ortiz 1 (0.1%) + Jay Buddhabhatti 1 (0.1%) + Andrey Dolnikov 1 (0.1%) + chenzhipeng 1 (0.1%) + Olivier Moysan 1 (0.1%) + Ville Skyttä 1 (0.1%) + David Oberhollenzer 1 (0.1%) + Haijun Qin 1 (0.1%) + Neal Frager 1 (0.1%) + Luca Ceresoli 1 (0.1%) + Viacheslav Bocharov 1 (0.1%) + Yuepeng Xing 1 (0.1%) + Cristian Birsan 1 (0.1%) + Lokanathan, Raaj 1 (0.1%) + Christian Gmeiner 1 (0.1%) + Daniel Golle 1 (0.1%) + Manuel Traut 1 (0.1%) + Ben Dooks 1 (0.1%) + Kasper Revsbech 1 (0.1%) + ==================================== ===== + + +.. table:: Developers with the most changed lines + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Bryan Brattlof 38811 (18.1%) + Tom Rini 36464 (17.0%) + Simon Glass 30090 (14.0%) + Jagan Teki 23918 (11.1%) + Marek Vasut 14720 (6.9%) + Brandon Maier 13759 (6.4%) + Tony Dinh 7399 (3.4%) + Balamanikandan Gunasundar 4239 (2.0%) + Jim Liu 4106 (1.9%) + Fabio Estevam 3264 (1.5%) + Christophe Leroy 2145 (1.0%) + Neil Armstrong 2020 (0.9%) + Nikhil M Jain 1681 (0.8%) + Sumit Garg 1671 (0.8%) + Tim Harvey 1524 (0.7%) + Jonas Karlman 1439 (0.7%) + Roger Quadros 1431 (0.7%) + Quentin Schulz 1296 (0.6%) + Heinrich Schuchardt 1277 (0.6%) + Michal Simek 1274 (0.6%) + Svyatoslav Ryhel 1259 (0.6%) + Akash Gajjar 1057 (0.5%) + Mark Kettenis 1042 (0.5%) + Sinthu Raja 967 (0.5%) + Holger Brunck 966 (0.5%) + Chris Morgan 965 (0.4%) + Peter Robinson 919 (0.4%) + Luca Ceresoli 860 (0.4%) + Hai Pham 712 (0.3%) + Andre Przywara 702 (0.3%) + Kunihiko Hayashi 695 (0.3%) + Dario Binacchi 690 (0.3%) + Patrick Delaunay 668 (0.3%) + Samuel Holland 568 (0.3%) + Dhruva Gole 527 (0.2%) + Ryan Chen 504 (0.2%) + Sergei Antonov 464 (0.2%) + Sean Anderson 439 (0.2%) + Ashok Reddy Soma 399 (0.2%) + Masahisa Kojima 391 (0.2%) + Sergiu Moga 382 (0.2%) + Maxim Cournoyer 380 (0.2%) + Massimo Pegorer 353 (0.2%) + Linus Walleij 317 (0.1%) + Eugen Hristev 295 (0.1%) + Alexey Romanov 285 (0.1%) + Yu Chien Peter Lin 267 (0.1%) + Stefan Bosch 260 (0.1%) + Dzmitry Sankouski 257 (0.1%) + Heiko Schocher 221 (0.1%) + Enric Balletbo i Serra 214 (0.1%) + Kshitiz Varshney 211 (0.1%) + Thomas Fitzsimmons 205 (0.1%) + Mihai Sain 191 (0.1%) + Angelo Dureghello 167 (0.1%) + Adam Ford 162 (0.1%) + Marcel Ziswiler 160 (0.1%) + Mattijs Korpershoek 154 (0.1%) + Etienne Carriere 154 (0.1%) + Leo Yu-Chi Liang 135 (0.1%) + Ramin Khonsari 131 (0.1%) + Pali Rohár 127 (0.1%) + Olivier Moysan 116 (0.1%) + Vincent Fazio 106 (0.0%) + Fabrice Gasnier 98 (0.0%) + Max Krummenacher 80 (0.0%) + Takahiro Kuwano 76 (0.0%) + Victor Lim 73 (0.0%) + Frieder Schrempf 72 (0.0%) + Manoj Sai 70 (0.0%) + Andrew Davis 70 (0.0%) + Mikhail Ilin 69 (0.0%) + Dai Okamura 65 (0.0%) + Tam Nguyen 63 (0.0%) + Peng Fan 61 (0.0%) + Sjoerd Simons 61 (0.0%) + Cristian Birsan 59 (0.0%) + Antoine Mazeas 51 (0.0%) + Rick Chen 49 (0.0%) + Paweł Anikiel 47 (0.0%) + Andreas Kemnade 45 (0.0%) + Jan Kiszka 43 (0.0%) + Andrejs Cainikovs 41 (0.0%) + Michael Trimarchi 41 (0.0%) + Rob Herring 40 (0.0%) + Martyn Welch 36 (0.0%) + Stefan Roese 35 (0.0%) + Neha Malcom Francis 35 (0.0%) + Algapally Santosh Sagar 34 (0.0%) + Jernej Skrabec 34 (0.0%) + Maxim Schwalm 30 (0.0%) + Qu Wenruo 29 (0.0%) + Loic Poulain 29 (0.0%) + Ioana Ciornei 28 (0.0%) + Christian Kohlschütter 28 (0.0%) + Michael Walle 23 (0.0%) + Vasily Khoruzhick 22 (0.0%) + Pei Yue Ho 22 (0.0%) + Vincent Stehlé 19 (0.0%) + Venkatesh Yadav Abbarapu 19 (0.0%) + Pengfei Fan 16 (0.0%) + Harald Seiler 16 (0.0%) + Ville Skyttä 16 (0.0%) + Sean Edmond 14 (0.0%) + Harini Katakam 14 (0.0%) + Robert Marko 14 (0.0%) + John Keeping 13 (0.0%) + Ovidiu Panait 13 (0.0%) + Kamlesh Gurudasani 13 (0.0%) + Nikita Shubin 13 (0.0%) + Marc Kleine-Budde 13 (0.0%) + Detlev Casanova 13 (0.0%) + David Oberhollenzer 11 (0.0%) + Ilias Apalodimas 10 (0.0%) + Mario Kicherer 10 (0.0%) + Yuepeng Xing 10 (0.0%) + Jaehoon Chung 9 (0.0%) + KaDiWa 9 (0.0%) + Oleksandr Suvorov 8 (0.0%) + Christian Gmeiner 8 (0.0%) + Ye Li 7 (0.0%) + Christopher Obbard 7 (0.0%) + Ying-Chun Liu (PaulLiu) 7 (0.0%) + Johan Jonker 6 (0.0%) + Jonathan Liu 6 (0.0%) + Andrey Dolnikov 6 (0.0%) + Daniel Golle 6 (0.0%) + Philippe Schenker 5 (0.0%) + Michal Suchanek 5 (0.0%) + Ivan Khoronzhuk 5 (0.0%) + Ilko Iliev 4 (0.0%) + Manuel Traut 4 (0.0%) + Shenlin Liang 3 (0.0%) + annsai01 3 (0.0%) + Ulf Samuelsson 3 (0.0%) + Matwey V. Kornilov 3 (0.0%) + Jay Buddhabhatti 3 (0.0%) + chenzhipeng 3 (0.0%) + Ben Dooks 3 (0.0%) + Peter Geis 2 (0.0%) + Ralph Siemsen 2 (0.0%) + Christian Marangi 2 (0.0%) + Jorge Ramirez-Ortiz 2 (0.0%) + David Sebek 1 (0.0%) + Vignesh Raghavendra 1 (0.0%) + Sebastian Andrzej Siewior 1 (0.0%) + Jade Lovelace 1 (0.0%) + Ehsan Mohandesi 1 (0.0%) + Aurelien Jarno 1 (0.0%) + Arnaud Ferraris 1 (0.0%) + Igor Opaniuk 1 (0.0%) + Joost van Zwieten 1 (0.0%) + Haijun Qin 1 (0.0%) + Neal Frager 1 (0.0%) + Viacheslav Bocharov 1 (0.0%) + Lokanathan, Raaj 1 (0.0%) + Kasper Revsbech 1 (0.0%) + ==================================== ===== + + +.. table:: Developers with the most lines removed + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Tom Rini 18089 (23.1%) + Simon Glass 5998 (7.7%) + Luca Ceresoli 860 (1.1%) + Holger Brunck 532 (0.7%) + Leo Yu-Chi Liang 90 (0.1%) + Mattijs Korpershoek 83 (0.1%) + Andrew Davis 43 (0.1%) + Pali Rohár 28 (0.0%) + Maxim Schwalm 27 (0.0%) + Dai Okamura 12 (0.0%) + Michael Walle 12 (0.0%) + Ovidiu Panait 10 (0.0%) + Peng Fan 7 (0.0%) + Ioana Ciornei 6 (0.0%) + Michal Suchanek 4 (0.0%) + Rob Herring 3 (0.0%) + Johan Jonker 3 (0.0%) + Ying-Chun Liu (PaulLiu) 2 (0.0%) + Ilko Iliev 1 (0.0%) + ==================================== ===== + + +.. table:: Developers with the most signoffs (total 215) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Francesco Dolcini 21 (9.8%) + Marek Vasut 21 (9.8%) + Tom 19 (8.8%) + Michal Simek 19 (8.8%) + Michael Trimarchi 8 (3.7%) + Dario Binacchi 8 (3.7%) + Neil Armstrong 8 (3.7%) + Hai Pham 7 (3.3%) + Kever Yang 6 (2.8%) + Tom Rini 5 (2.3%) + YouMin Chen 5 (2.3%) + Jianqun Xu 4 (1.9%) + Elaine Zhang 4 (1.9%) + Mike Worsfold 4 (1.9%) + Manoj Sai 4 (1.9%) + Marcel Ziswiler 4 (1.9%) + Ashok Reddy Soma 4 (1.9%) + Peter Robinson 4 (1.9%) + Peng Fan 3 (1.4%) + Andre Przywara 3 (1.4%) + Heinrich Schuchardt 3 (1.4%) + Vignesh Raghavendra 2 (0.9%) + Joseph Chen 2 (0.9%) + Finley Xiao 2 (0.9%) + Suniel Mahesh 2 (0.9%) + FUKAUMI Naoki 2 (0.9%) + Judith Mendez 2 (0.9%) + Robert Hancock 2 (0.9%) + Peter Geis 2 (0.9%) + Andrejs Cainikovs 2 (0.9%) + Samuel Holland 2 (0.9%) + Jonas Karlman 2 (0.9%) + Jagan Teki 2 (0.9%) + Simon Glass 1 (0.5%) + Mattijs Korpershoek 1 (0.5%) + Pali Rohár 1 (0.5%) + Michal Suchanek 1 (0.5%) + Anand Gadiyar 1 (0.5%) + Angelo Durgehello 1 (0.5%) + Nam Nguyen 1 (0.5%) + Steven Liu 1 (0.5%) + Sebastian Reichel 1 (0.5%) + Yifeng Zhao 1 (0.5%) + Ren Jianing 1 (0.5%) + Vladimir Oltean 1 (0.5%) + Jonas Schwöbel 1 (0.5%) + Shawn Guo 1 (0.5%) + Jason Zhu 1 (0.5%) + Jon Lin 1 (0.5%) + Sugar Zhang 1 (0.5%) + Valentine Barshak 1 (0.5%) + Jit Loon Lim 1 (0.5%) + Philippe Schenker 1 (0.5%) + Ilias Apalodimas 1 (0.5%) + Sjoerd Simons 1 (0.5%) + Tam Nguyen 1 (0.5%) + Ramin Khonsari 1 (0.5%) + Sergiu Moga 1 (0.5%) + Svyatoslav Ryhel 1 (0.5%) + Quentin Schulz 1 (0.5%) + ==================================== ===== + + +.. table:: Developers with the most reviews (total 767) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Simon Glass 225 (29.3%) + Kever Yang 112 (14.6%) + Fabio Estevam 49 (6.4%) + Tom Rini 33 (4.3%) + Patrice Chotard 33 (4.3%) + Marek Vasut 27 (3.5%) + Ramon Fried 22 (2.9%) + Stefan Roese 17 (2.2%) + Ilias Apalodimas 16 (2.1%) + Leo Yu-Chi Liang 15 (2.0%) + Rick Chen 15 (2.0%) + Heinrich Schuchardt 14 (1.8%) + Jagan Teki 14 (1.8%) + Patrick Delaunay 14 (1.8%) + Mattijs Korpershoek 13 (1.7%) + Jaehoon Chung 13 (1.7%) + Samuel Holland 12 (1.6%) + Heiko Schocher 9 (1.2%) + Neil Armstrong 8 (1.0%) + Vladimir Oltean 7 (0.9%) + Sean Anderson 7 (0.9%) + Bin Meng 6 (0.8%) + FRANJOU Stephane 6 (0.8%) + Claudiu Beznea 6 (0.8%) + Michael Trimarchi 5 (0.7%) + Peng Fan 5 (0.7%) + Jens Wiklander 5 (0.7%) + Yu Chien Peter Lin 4 (0.5%) + Andre Przywara 3 (0.4%) + Pali Rohár 3 (0.4%) + Viacheslav Mitrofanov 3 (0.4%) + Ye Li 3 (0.4%) + Dhruva Gole 3 (0.4%) + Marcel Ziswiler 2 (0.3%) + Oleksandr Suvorov 2 (0.3%) + Wei Liang Lim 2 (0.3%) + Eng Lee Teh 2 (0.3%) + Minkyu Kang 2 (0.3%) + Tudor Ambarus 2 (0.3%) + Philipp Tomsich 2 (0.3%) + Etienne Carriere 2 (0.3%) + Masahisa Kojima 2 (0.3%) + Eugen Hristev 2 (0.3%) + Francesco Dolcini 1 (0.1%) + Michal Simek 1 (0.1%) + Jonas Karlman 1 (0.1%) + Nishanth Menon 1 (0.1%) + Siddharth Vadapalli 1 (0.1%) + Matthias Brugger 1 (0.1%) + Chia-Wei Wang 1 (0.1%) + Huang Jianan 1 (0.1%) + Oliver Graute 1 (0.1%) + Pratyush Yadav 1 (0.1%) + Soeren Moch 1 (0.1%) + Sunil V L 1 (0.1%) + Miquel Raynal 1 (0.1%) + Hector Palacios 1 (0.1%) + Derald Woods 1 (0.1%) + Nick Desaulniers 1 (0.1%) + Frieder Schrempf 1 (0.1%) + Adam Ford 1 (0.1%) + Sumit Garg 1 (0.1%) + Christophe Leroy 1 (0.1%) + ==================================== ===== + + +.. table:: Developers with the most test credits (total 78) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Svyatoslav Ryhel 12 (15.4%) + Andreas Westman Dorcsak 11 (14.1%) + Thierry Reding 9 (11.5%) + Robert Eckelmann 8 (10.3%) + Samuel Holland 6 (7.7%) + Vagrant Cascadian 3 (3.8%) + Jagan Teki 2 (2.6%) + Eugen Hristev 2 (2.6%) + Jonas Schwöbel 2 (2.6%) + Quentin Schulz 2 (2.6%) + Agneli 2 (2.6%) + Lothar Waßmann 2 (2.6%) + Simon Glass 1 (1.3%) + Fabio Estevam 1 (1.3%) + Ilias Apalodimas 1 (1.3%) + Rick Chen 1 (1.3%) + Patrick Delaunay 1 (1.3%) + Mattijs Korpershoek 1 (1.3%) + Andre Przywara 1 (1.3%) + Dhruva Gole 1 (1.3%) + Jonas Karlman 1 (1.3%) + Suniel Mahesh 1 (1.3%) + Sjoerd Simons 1 (1.3%) + Matwey V. Kornilov 1 (1.3%) + Anand Moon 1 (1.3%) + Vaishnav Achath 1 (1.3%) + Karsten Merker 1 (1.3%) + Sean Nyekjaer 1 (1.3%) + Mihai Sain 1 (1.3%) + ==================================== ===== + + +.. table:: Developers who gave the most tested-by credits (total 78) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Svyatoslav Ryhel 41 (52.6%) + Andre Przywara 6 (7.7%) + Tom Rini 5 (6.4%) + Simon Glass 4 (5.1%) + Jonas Karlman 3 (3.8%) + Loic Poulain 3 (3.8%) + Ramin Khonsari 2 (2.6%) + Jagan Teki 1 (1.3%) + Patrick Delaunay 1 (1.3%) + Dhruva Gole 1 (1.3%) + Sjoerd Simons 1 (1.3%) + Michael Trimarchi 1 (1.3%) + Etienne Carriere 1 (1.3%) + Peter Geis 1 (1.3%) + Sergiu Moga 1 (1.3%) + Maxim Schwalm 1 (1.3%) + Kasper Revsbech 1 (1.3%) + Neha Malcom Francis 1 (1.3%) + Fabrice Gasnier 1 (1.3%) + Maxim Cournoyer 1 (1.3%) + Sergei Antonov 1 (1.3%) + ==================================== ===== + + +.. table:: Developers with the most report credits (total 22) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Heinrich Schuchardt 3 (13.6%) + Ilias Apalodimas 2 (9.1%) + Patrick Delaunay 1 (4.5%) + Sjoerd Simons 1 (4.5%) + Samuel Holland 1 (4.5%) + Quentin Schulz 1 (4.5%) + Karsten Merker 1 (4.5%) + Marek Vasut 1 (4.5%) + Francesco Dolcini 1 (4.5%) + Nishanth Menon 1 (4.5%) + Oliver Graute 1 (4.5%) + Anand Gadiyar 1 (4.5%) + Philippe Schenker 1 (4.5%) + Andreas Schwab 1 (4.5%) + Stefan Herbrechtsmeier 1 (4.5%) + Carlos Rafael Giani 1 (4.5%) + Dave Jones 1 (4.5%) + Serge Bazanski 1 (4.5%) + Sam Winchenbach 1 (4.5%) + ==================================== ===== + + +.. table:: Developers who gave the most report credits (total 22) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Simon Glass 6 (27.3%) + Tom Rini 5 (22.7%) + Heinrich Schuchardt 3 (13.6%) + Qu Wenruo 2 (9.1%) + Ilias Apalodimas 1 (4.5%) + Maxim Cournoyer 1 (4.5%) + Fabio Estevam 1 (4.5%) + Vignesh Raghavendra 1 (4.5%) + Harald Seiler 1 (4.5%) + Sinthu Raja 1 (4.5%) + ==================================== ===== + + +.. table:: Top changeset contributors by employer + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 524 (31.0%) + Google, Inc. 381 (22.5%) + Konsulko Group 333 (19.7%) + DENX Software Engineering 72 (4.3%) + Texas Instruments 49 (2.9%) + Linaro 47 (2.8%) + Edgeble AI Technologies Pvt. Ltd. 46 (2.7%) + ST Microelectronics 40 (2.4%) + AMD 34 (2.0%) + NXP 25 (1.5%) + Renesas Electronics 24 (1.4%) + Toradex 24 (1.4%) + Amarula Solutions 20 (1.2%) + Collabora Ltd. 20 (1.2%) + ARM 17 (1.0%) + Semihalf Embedded Systems 6 (0.4%) + Red Hat 4 (0.2%) + Siemens 4 (0.2%) + Socionext Inc. 4 (0.2%) + BayLibre SAS 3 (0.2%) + SUSE 3 (0.2%) + Pengutronix 2 (0.1%) + Ronetix 2 (0.1%) + Extreme Engineering Solutions 2 (0.1%) + Bootlin 1 (0.1%) + Intel 1 (0.1%) + linutronix 1 (0.1%) + Samsung 1 (0.1%) + Xilinx 1 (0.1%) + ==================================== ===== + + +.. table:: Top lines changed by employer + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 64681 (30.1%) + Texas Instruments 42105 (19.6%) + Konsulko Group 36464 (17.0%) + Google, Inc. 30090 (14.0%) + Edgeble AI Technologies Pvt. Ltd. 23070 (10.7%) + Linaro 4601 (2.1%) + DENX Software Engineering 4582 (2.1%) + AMD 1741 (0.8%) + Amarula Solutions 1649 (0.8%) + ST Microelectronics 882 (0.4%) + Bootlin 860 (0.4%) + Renesas Electronics 775 (0.4%) + Socionext Inc. 760 (0.4%) + ARM 724 (0.3%) + Collabora Ltd. 413 (0.2%) + NXP 307 (0.1%) + Toradex 290 (0.1%) + Red Hat 214 (0.1%) + BayLibre SAS 154 (0.1%) + Extreme Engineering Solutions 106 (0.0%) + Semihalf Embedded Systems 47 (0.0%) + Siemens 43 (0.0%) + SUSE 34 (0.0%) + Pengutronix 13 (0.0%) + Samsung 9 (0.0%) + Ronetix 4 (0.0%) + Xilinx 3 (0.0%) + Intel 1 (0.0%) + linutronix 1 (0.0%) + ==================================== ===== + + +.. table:: Employers with the most signoffs (total 215) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 48 (22.3%) + Rockchip 29 (13.5%) + Toradex 28 (13.0%) + Amarula Solutions 24 (11.2%) + AMD 23 (10.7%) + NVidia 19 (8.8%) + Linaro 9 (4.2%) + Renesas Electronics 9 (4.2%) + Texas Instruments 5 (2.3%) + Konsulko Group 5 (2.3%) + NXP 4 (1.9%) + ARM 3 (1.4%) + Canonical 3 (1.4%) + Collabora Ltd. 2 (0.9%) + Google, Inc. 1 (0.5%) + BayLibre SAS 1 (0.5%) + SUSE 1 (0.5%) + Intel 1 (0.5%) + ==================================== ===== + + +.. table:: Employers with the most hackers (total 160) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 86 (53.8%) + Linaro 9 (5.6%) + Texas Instruments 8 (5.0%) + AMD 6 (3.8%) + Collabora Ltd. 6 (3.8%) + Toradex 5 (3.1%) + DENX Software Engineering 5 (3.1%) + Amarula Solutions 4 (2.5%) + NXP 4 (2.5%) + ARM 3 (1.9%) + ST Microelectronics 3 (1.9%) + Renesas Electronics 2 (1.2%) + SUSE 2 (1.2%) + Socionext Inc. 2 (1.2%) + Konsulko Group 1 (0.6%) + Google, Inc. 1 (0.6%) + BayLibre SAS 1 (0.6%) + Intel 1 (0.6%) + Edgeble AI Technologies Pvt. Ltd. 1 (0.6%) + Bootlin 1 (0.6%) + Red Hat 1 (0.6%) + Extreme Engineering Solutions 1 (0.6%) + Semihalf Embedded Systems 1 (0.6%) + Siemens 1 (0.6%) + Pengutronix 1 (0.6%) + Samsung 1 (0.6%) + Ronetix 1 (0.6%) + Xilinx 1 (0.6%) + linutronix 1 (0.6%) + ==================================== ===== + From 063359444c251163cf0e4159355bc545b486d01d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 1 Apr 2023 09:06:55 +0200 Subject: [PATCH 015/805] usb: gadget: missing fallthrough in composite_setup() Add a missing fallthrough macro. This fixes a -Wimplicit-fallthrough warning. Signed-off-by: Heinrich Schuchardt --- drivers/usb/gadget/composite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index 2a309e624e..04b8541993 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -1068,7 +1068,7 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) if (!gadget_is_dualspeed(gadget) || gadget->speed >= USB_SPEED_SUPER) break; - + fallthrough; case USB_DT_CONFIG: value = config_desc(cdev, w_value); if (value >= 0) From 7f2347088529693ee13b4ab7e7a27f5a1f617c1f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 7 Mar 2023 08:42:33 +0100 Subject: [PATCH 016/805] usb: gadget: f_sdp: Add missing spl_board_prepare_for_boot() call The spl_board_prepare_for_boot() should be called before jump_to_image_no_args() to perform board-specific deinitialization before jumping to the next stage. This board-specific deinitialization can be very much anything, e.g. disable dcache in case it was enabled, or such. Add the missing spl_board_prepare_for_boot() call into f_sdp . Signed-off-by: Marek Vasut --- drivers/usb/gadget/f_sdp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 9ea43f29cf..4da5a160a0 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -865,6 +865,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, struct spl_image_info spl_image = {}; struct spl_boot_device bootdev = {}; spl_parse_image_header(&spl_image, &bootdev, header); + spl_board_prepare_for_boot(); jump_to_image_no_args(&spl_image); #else /* In U-Boot, allow jumps to scripts */ From 8ca42025952afba977ce6cecf644371e3f7fa11d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 3 Apr 2023 20:48:24 -0400 Subject: [PATCH 017/805] mx6sx-udoo-neo-basic-u-boot.dtsi: Correct to bootph-all Updating this was missed in the merge of the next branch back in to master. Signed-off-by: Tom Rini --- arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi b/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi index be755e125b..b5e1f2b9a1 100644 --- a/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi +++ b/arch/arm/dts/imx6sx-udoo-neo-basic-u-boot.dtsi @@ -1,17 +1,17 @@ // SPDX-License-Identifier: GPL-2.0+ &soc { - u-boot,dm-pre-reloc; + bootph-all; }; &aips1 { - u-boot,dm-pre-reloc; + bootph-all; }; &pinctrl_uart1 { - u-boot,dm-pre-reloc; + bootph-all; }; &uart1 { - u-boot,dm-pre-reloc; + bootph-all; }; From d08c00082183dc6a2301690678794d2b80e75258 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 7 Mar 2023 08:51:05 +0100 Subject: [PATCH 018/805] ARM: imx: Enable SDP download in SPL on DH i.MX6 DHSOM Enable SDP protocol support in SPL for DH i.MX6 DHSOM, now that those components fit into the SPL due to LTO. To start U-Boot via SDP upload on i.MX6 DHSOM based board, proceed as follows: - Compile imx_usb [1] . - Power off the i.MX6 DHSOM based board. - Connect both USB-serial console and USB-OTG miniB ports to host PC. - Switch board to USB boot mode. - Power on the board. - Verify using '$ dmesg' that a new device has been detected as follows: New USB device found, idVendor=15a2, idProduct=0054, bcdDevice= 0.01 New USB device strings: Mfr=1, Product=2, SerialNumber=0 Product: SE Blank ARIK Manufacturer: Freescale SemiConductor Inc - Upload U-Boot SPL: $ imx_usb u-boot-with-spl.imx - Wait for SPL to come up, the following print ought to be the last on UART console: SDP: handle requests... - Upload U-Boot proper: $ imx_usb u-boot.img [1] https://github.com/boundarydevices/imx_usb_loader.git Signed-off-by: Marek Vasut --- configs/dh_imx6_defconfig | 5 +++++ include/configs/dh_imx6.h | 2 -- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 3487cc2f5c..29b07821bf 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -39,6 +39,10 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 CONFIG_CMD_MEMTEST=y @@ -113,6 +117,7 @@ CONFIG_USB_GADGET_MANUFACTURER="dh" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x17ffffc0 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index e9b382a3b7..4b5ef4ad51 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -31,7 +31,6 @@ #define CFG_MXC_UART_BASE UART1_BASE /* USB Configs */ -#ifdef CONFIG_CMD_USB #define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CFG_MXC_USB_FLAGS 0 @@ -39,7 +38,6 @@ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) #define DFU_DEFAULT_POLL_TIMEOUT 300 #endif -#endif #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ From 95942f99a7057359c07bf383214d57154e2466fe Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Fri, 10 Mar 2023 11:07:52 +0100 Subject: [PATCH 019/805] arm: imx: add u-boot-nand.imx to boot from NAND without SPL U-Boot can be booted from NAND without SPL by prepending the DCD header to the actual U-Boot binary. However this requires prepending 1024 bytes to u-boot.imx (DCD + u-boot.bin). There is already a similar target to build spl/u-boot-nand-spl.imx, add the same option for no-SPL boot. Tested on i.MX6ULL. The resulting layout of u-boot-nand.imx is: - Offset 0x0000 (0 KiB): padding - Offset 0x0400 (1 KiB): DCD header - Offset 0x1000 (4 KiB): u-boot.bin Signed-off-by: Luca Ceresoli --- Makefile | 3 +++ arch/arm/mach-imx/Makefile | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/Makefile b/Makefile index 0f37c4b767..15f48cf135 100644 --- a/Makefile +++ b/Makefile @@ -1522,6 +1522,9 @@ endif u-boot.uim: u-boot.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ +u-boot-nand.imx: u-boot.imx FORCE + $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ + u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 9bcb23c4da..906f538259 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -136,6 +136,12 @@ u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) +quiet_cmd_u-boot-nand_imx = GEN $@ +cmd_u-boot-nand_imx = (dd bs=1024 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@ + +u-boot-nand.imx: u-boot.imx FORCE + $(call if_changed,u-boot-nand_imx) + ifeq ($(CONFIG_MULTI_DTB_FIT),y) MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ -T $(IMAGE_TYPE) -e $(CONFIG_TEXT_BASE) From 7ef55171087ebe51917612d89fae8cc75a2d5ffe Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 27 Mar 2023 10:23:29 +0200 Subject: [PATCH 020/805] configs: tqma6: switch to DM_SERIAL Usage without DM_SERIAL is deprecated. Fix this. Signed-off-by: Markus Niebel --- configs/tqma6dl_mba6_mmc_defconfig | 2 +- configs/tqma6dl_mba6_spi_defconfig | 2 +- configs/tqma6q_mba6_mmc_defconfig | 2 +- configs/tqma6q_mba6_spi_defconfig | 2 +- configs/tqma6s_mba6_mmc_defconfig | 2 +- configs/tqma6s_mba6_spi_defconfig | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig index a02ee92785..3f19430d65 100644 --- a/configs/tqma6dl_mba6_mmc_defconfig +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -61,4 +61,4 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DM_SERIAL=y diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index 8f7e0ac101..1a30d58a75 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -65,4 +65,4 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DM_SERIAL=y diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index 48822f388c..aa3ee0e3e9 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -61,4 +61,4 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DM_SERIAL=y diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index ed774262ae..5407d09508 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -65,4 +65,4 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DM_SERIAL=y diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index 9400c64812..84eb98fcae 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -61,4 +61,4 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DM_SERIAL=y diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index ddbf9a757e..76e447a606 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -65,4 +65,4 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DM_SERIAL=y From 2443d8b1db58e132d322fbdfd7ac639b59e0cde1 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 27 Mar 2023 10:23:30 +0200 Subject: [PATCH 021/805] configs: tqma6: enable DM for MDIO / PHY Since this works with current device trees, enabled these. Signed-off-by: Markus Niebel --- configs/tqma6dl_mba6_mmc_defconfig | 3 +++ configs/tqma6dl_mba6_spi_defconfig | 3 +++ configs/tqma6q_mba6_mmc_defconfig | 3 +++ configs/tqma6q_mba6_spi_defconfig | 3 +++ configs/tqma6s_mba6_mmc_defconfig | 3 +++ configs/tqma6s_mba6_spi_defconfig | 3 +++ 6 files changed, 18 insertions(+) diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig index 3f19430d65..a848dc8459 100644 --- a/configs/tqma6dl_mba6_mmc_defconfig +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -51,7 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC=y +CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index 1a30d58a75..d1db8cce47 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -55,7 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC=y +CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index aa3ee0e3e9..cc57c7b8bf 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -51,7 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC=y +CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index 5407d09508..8776aef29c 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -55,7 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC=y +CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index 84eb98fcae..a613279f72 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -51,7 +51,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC=y +CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index 76e447a606..ef7733f4f7 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -55,7 +55,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC=y +CONFIG_RGMII=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y From bc1bcd272e5d5118bb20a70ed558f0068b68af2d Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 27 Mar 2023 10:23:31 +0200 Subject: [PATCH 022/805] configs: tqma6: enable DM_THERMAL Enabling this gives some informal output at boot time. Signed-off-by: Markus Niebel --- configs/tqma6dl_mba6_mmc_defconfig | 2 ++ configs/tqma6dl_mba6_spi_defconfig | 2 ++ configs/tqma6q_mba6_mmc_defconfig | 2 ++ configs/tqma6q_mba6_spi_defconfig | 2 ++ configs/tqma6s_mba6_mmc_defconfig | 2 ++ configs/tqma6s_mba6_spi_defconfig | 2 ++ 6 files changed, 12 insertions(+) diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig index a848dc8459..34d0dddfcb 100644 --- a/configs/tqma6dl_mba6_mmc_defconfig +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -65,3 +65,5 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index d1db8cce47..1bd7f8d7b3 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -69,3 +69,5 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index cc57c7b8bf..f1f4232294 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -65,3 +65,5 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index 8776aef29c..cc8616fcfe 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -69,3 +69,5 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index a613279f72..bd9476cf74 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -65,3 +65,5 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index ef7733f4f7..a9aa3fc850 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -69,3 +69,5 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y From 54351fe54226201da835d34b603ebca736e4928e Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Mon, 3 Apr 2023 14:01:53 +0200 Subject: [PATCH 023/805] board: verdin-imx8mp: update ddrc config for different lpddr4 memories Add support to Verdin IMX8MP V1.1B SKU which uses MT53E1G32D2FW-046 WT:B memory. Compared to the 8 GB memory (MT53E2G32D4NQ-046 WT:A) used on Verdin IMX8MP V1.0A it has 16 row addresses instead of 17. In fact, the new memory, is a 2 GB/rank memory. The 8 GB memory is a 4 GB/rank memory. Manually tweaking Host Interface addresses vs LPDDR4 signals mapping it is possible to have a single configuration working with both memories: - Old configuration: HIF bit 30 -> rank, HIF bit 29 -> Row 16 - New configuration: HIF bit 29 -> rank, HIF bit 30 -> Row 16 With this change the memory space from the host processor is contiguous for both the configurations and the correct memory size is computed using get_ram_size() at runtime. Support for single rank memories still works thanks to the fact dual ranks training fails (ddr_init->ddr_cfg_phy) toward single rank memories. Signed-off-by: Emanuele Ghidoli Signed-off-by: Marcel Ziswiler --- board/toradex/verdin-imx8mp/lpddr4_timing.c | 4 ++-- board/toradex/verdin-imx8mp/spl.c | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c index 3e00d9b51e..314b74e7df 100644 --- a/board/toradex/verdin-imx8mp/lpddr4_timing.c +++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c @@ -55,13 +55,13 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4001c4, 0x1 }, { 0x3d4000f4, 0xc99 }, { 0x3d400108, 0x9121c1c }, - { 0x3d400200, 0x18 }, + { 0x3d400200, 0x17 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, + { 0x3d40021c, 0xf08 }, { 0x3d400250, 0x1705 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index ea99e37085..7b383cc0d5 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -34,11 +34,10 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) void spl_dram_init(void) { /* - * try configuring for quad die, dual rank aka 8 GB falling back to - * dual die, single rank aka 1 GB (untested), 2 GB or 4 GB if it fails + * Try configuring for dual rank memory falling back to single rank */ if (ddr_init(&dram_timing)) { - printf("Quad die, dual rank failed, attempting dual die, single rank configuration.\n"); + printf("Dual rank failed, attempting single rank configuration.\n"); ddr_init(&dram_timing2); } } From cfa3723163c2e6bc66493944a4f8ea4cb9c973bd Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Mon, 3 Apr 2023 14:01:54 +0200 Subject: [PATCH 024/805] board: verdin-imx8mp: fix lpddr4 refresh timing Change tRFCmin (tRFCab) from 280 ns to 380 ns to be compliant with current and futures memories. Fixes: 2bc2f817cea7 ("board: toradex: add verdin imx8m plus support") Signed-off-by: Emanuele Ghidoli Signed-off-by: Marcel Ziswiler --- board/toradex/verdin-imx8mp/lpddr4_timing.c | 24 ++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c index 314b74e7df..58278d2150 100644 --- a/board/toradex/verdin-imx8mp/lpddr4_timing.c +++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c @@ -21,7 +21,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400000, 0xa3080020 }, { 0x3d400020, 0x1303 }, { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, + { 0x3d400064, 0x7a017c }, { 0x3d400070, 0x61027f10 }, { 0x3d400074, 0x7b0 }, { 0x3d4000d0, 0xc00307a3 }, @@ -39,7 +39,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40011c, 0x501 }, { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, + { 0x3d400138, 0x184 }, { 0x3d400144, 0xc80064 }, { 0x3d400180, 0x3e8001e }, { 0x3d400184, 0x3207a12 }, @@ -77,7 +77,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402020, 0x1001 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, + { 0x3d402064, 0xc0026 }, { 0x3d4020dc, 0x840000 }, { 0x3d4020e0, 0x330000 }, { 0x3d4020e8, 0x660048 }, @@ -92,7 +92,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40211c, 0x301 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, + { 0x3d402138, 0x27 }, { 0x3d402144, 0x14000a }, { 0x3d402180, 0x640004 }, { 0x3d402190, 0x3818200 }, @@ -102,7 +102,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403020, 0x1001 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, + { 0x3d403064, 0x3000a }, { 0x3d4030dc, 0x840000 }, { 0x3d4030e0, 0x330000 }, { 0x3d4030e8, 0x660048 }, @@ -117,7 +117,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40311c, 0x301 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, + { 0x3d403138, 0xa }, { 0x3d403144, 0x50003 }, { 0x3d403180, 0x190004 }, { 0x3d403190, 0x3818200 }, @@ -1841,7 +1841,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d400000, 0xa1080020 }, { 0x3d400020, 0x1303 }, { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, + { 0x3d400064, 0x7a017c }, { 0x3d400070, 0x61027f10 }, { 0x3d400074, 0x7b0 }, { 0x3d4000d0, 0xc00307a3 }, @@ -1859,7 +1859,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d40011c, 0x501 }, { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, + { 0x3d400138, 0x184 }, { 0x3d400144, 0xc80064 }, { 0x3d400180, 0x3e8001e }, { 0x3d400184, 0x3207a12 }, @@ -1897,7 +1897,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d402020, 0x1001 }, { 0x3d402024, 0x30d400 }, { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, + { 0x3d402064, 0xc0026 }, { 0x3d4020dc, 0x840000 }, { 0x3d4020e0, 0x330000 }, { 0x3d4020e8, 0x660048 }, @@ -1912,7 +1912,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d40211c, 0x301 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, + { 0x3d402138, 0x27 }, { 0x3d402144, 0x14000a }, { 0x3d402180, 0x640004 }, { 0x3d402190, 0x3818200 }, @@ -1922,7 +1922,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d403020, 0x1001 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, + { 0x3d403064, 0x3000a }, { 0x3d4030dc, 0x840000 }, { 0x3d4030e0, 0x330000 }, { 0x3d4030e8, 0x660048 }, @@ -1937,7 +1937,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d40311c, 0x301 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, + { 0x3d403138, 0xa }, { 0x3d403144, 0x50003 }, { 0x3d403180, 0x190004 }, { 0x3d403190, 0x3818200 }, From 390bb9fcc031b82119b501d07d80c3b0f75fbf32 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Mon, 3 Apr 2023 14:01:55 +0200 Subject: [PATCH 025/805] board: verdin-imx8mp: update lpddr4 configuration and training Update LPDDR4 configuration and training using updated spreadsheet and tools from NXP using data from previous spreadsheet and verified toward datasheet: - MX8M_Plus_LPDDR4_RPA_v9.xlsx - mscale_ddr_tool_v3.30.exe From: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467 Some register values differ due to these fixes/modifications: - corrected calculation of T_CKPDX parameter (equal to tCKCKEH for LPDDR4) - corrected ECC related items, none of which affect normal operation when ECC is not enabled - corrected formula for calculation of tRTP in cell D122 Signed-off-by: Emanuele Ghidoli Signed-off-by: Marcel Ziswiler --- board/toradex/verdin-imx8mp/lpddr4_timing.c | 49 +++++++++++---------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c index 58278d2150..4f0bbe6ce1 100644 --- a/board/toradex/verdin-imx8mp/lpddr4_timing.c +++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c @@ -22,8 +22,8 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400020, 0x1303 }, { 0x3d400024, 0x1e84800 }, { 0x3d400064, 0x7a017c }, - { 0x3d400070, 0x61027f10 }, - { 0x3d400074, 0x7b0 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, { 0x3d4000d0, 0xc00307a3 }, { 0x3d4000d4, 0xc50000 }, { 0x3d4000dc, 0xf4003f }, @@ -31,12 +31,12 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x807bf }, + { 0x3d400104, 0x8083f }, { 0x3d40010c, 0xe0e000 }, { 0x3d400110, 0x12040a12 }, { 0x3d400114, 0x2050f0f }, { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x501 }, + { 0x3d40011c, 0x502 }, { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, { 0x3d400138, 0x184 }, @@ -53,9 +53,10 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4001b0, 0x11 }, { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x9121c1c }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9121b1c }, { 0x3d400200, 0x17 }, + { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, @@ -89,7 +90,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402110, 0x2040202 }, { 0x3d402114, 0x2030202 }, { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, + { 0x3d40211c, 0x302 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, { 0x3d402138, 0x27 }, @@ -98,7 +99,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, + { 0x3d4020f4, 0x599 }, { 0x3d403020, 0x1001 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, @@ -114,7 +115,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403110, 0x2040202 }, { 0x3d403114, 0x2030202 }, { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, + { 0x3d40311c, 0x302 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, { 0x3d403138, 0xa }, @@ -123,7 +124,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, + { 0x3d4030f4, 0x599 }, { 0x3d400028, 0x0 }, }; @@ -1700,15 +1701,15 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, { 0x200be, 0x3 }, - { 0x2000b, 0x7d }, + { 0x2000b, 0x465 }, { 0x2000c, 0xfa }, { 0x2000d, 0x9c4 }, { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, + { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, + { 0x22000b, 0x1c }, { 0x22000c, 0x6 }, { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, @@ -1842,8 +1843,8 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d400020, 0x1303 }, { 0x3d400024, 0x1e84800 }, { 0x3d400064, 0x7a017c }, - { 0x3d400070, 0x61027f10 }, - { 0x3d400074, 0x7b0 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, { 0x3d4000d0, 0xc00307a3 }, { 0x3d4000d4, 0xc50000 }, { 0x3d4000dc, 0xf4003f }, @@ -1851,12 +1852,12 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x807bf }, + { 0x3d400104, 0x8083f }, { 0x3d40010c, 0xe0e000 }, { 0x3d400110, 0x12040a12 }, { 0x3d400114, 0x2050f0f }, { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x501 }, + { 0x3d40011c, 0x502 }, { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, { 0x3d400138, 0x184 }, @@ -1873,9 +1874,10 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d4001b0, 0x11 }, { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x9121c1c }, + { 0x3d4000f4, 0x799 }, + { 0x3d400108, 0x9121b1c }, { 0x3d400200, 0x1f }, + { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, @@ -1909,7 +1911,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d402110, 0x2040202 }, { 0x3d402114, 0x2030202 }, { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, + { 0x3d40211c, 0x302 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, { 0x3d402138, 0x27 }, @@ -1918,7 +1920,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, + { 0x3d4020f4, 0x599 }, { 0x3d403020, 0x1001 }, { 0x3d403024, 0xc3500 }, { 0x3d403050, 0x20d000 }, @@ -1934,7 +1936,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d403110, 0x2040202 }, { 0x3d403114, 0x2030202 }, { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, + { 0x3d40311c, 0x302 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, { 0x3d403138, 0xa }, @@ -1943,7 +1945,7 @@ struct dram_cfg_param ddr_ddrc_cfg2[] = { { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, + { 0x3d4030f4, 0x599 }, { 0x3d400028, 0x0 }, }; @@ -2076,7 +2078,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg2[] = { { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x110 }, From 0e897621b44931053aa7fd547f2fc50bd46e4a90 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Mon, 3 Apr 2023 14:01:56 +0200 Subject: [PATCH 026/805] board: verdin-imx8mp: compact slight different lpddr4 configuration Deduplicate similar DDRC configurations and LPDDR4 training patterns by patching a single configuration. The aim is to reduce the SPL memory footprint and simplify maintenance of lpddr4_timing.c Signed-off-by: Emanuele Ghidoli Signed-off-by: Marcel Ziswiler --- board/toradex/verdin-imx8mp/lpddr4_timing.c | 380 ++++---------------- board/toradex/verdin-imx8mp/lpddr4_timing.h | 11 + board/toradex/verdin-imx8mp/spl.c | 6 +- 3 files changed, 75 insertions(+), 322 deletions(-) create mode 100644 board/toradex/verdin-imx8mp/lpddr4_timing.h diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c index 4f0bbe6ce1..29ea31e146 100644 --- a/board/toradex/verdin-imx8mp/lpddr4_timing.c +++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c @@ -13,6 +13,33 @@ #include #include +#include "lpddr4_timing.h" + +struct dram_cfg_param ddr_ddrc_cfg_single_rank_patch[] = { + { 0x3d400000, 0xa1080020}, + { 0x3d400200, 0x1f}, + { 0x3d40021c, 0xf07} +}; + +struct dram_cfg_param ddr_fsp0_cfg_single_rank_patch[] = { + { 0x54012, 0x110}, + { 0x5402c, 0x1} +}; + +struct dram_cfg_param ddr_fsp1_cfg_single_rank_patch[] = { + { 0x54012, 0x110}, + { 0x5402c, 0x1} +}; + +struct dram_cfg_param ddr_fsp2_cfg_single_rank_patch[] = { + { 0x54012, 0x110}, + { 0x5402c, 0x1} +}; + +struct dram_cfg_param ddr_fsp0_2d_cfg_single_rank_patch[] = { + { 0x54012, 0x110}, + { 0x5402c, 0x1} +}; struct dram_cfg_param ddr_ddrc_cfg[] = { /** Initialize DDRC registers **/ @@ -1835,311 +1862,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = { }, }; -struct dram_cfg_param ddr_ddrc_cfg2[] = { - /** Initialize DDRC registers **/ - { 0x3d400304, 0x1 }, - { 0x3d400030, 0x1 }, - { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x1303 }, - { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a017c }, - { 0x3d400070, 0x7027f90 }, - { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc00307a3 }, - { 0x3d4000d4, 0xc50000 }, - { 0x3d4000dc, 0xf4003f }, - { 0x3d4000e0, 0x330000 }, - { 0x3d4000e8, 0x660048 }, - { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x8083f }, - { 0x3d40010c, 0xe0e000 }, - { 0x3d400110, 0x12040a12 }, - { 0x3d400114, 0x2050f0f }, - { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x502 }, - { 0x3d400130, 0x20800 }, - { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x184 }, - { 0x3d400144, 0xc80064 }, - { 0x3d400180, 0x3e8001e }, - { 0x3d400184, 0x3207a12 }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820e }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0e }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0xdf00e4 }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, - { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0x799 }, - { 0x3d400108, 0x9121b1c }, - { 0x3d400200, 0x1f }, - { 0x3d400208, 0x0 }, - { 0x3d40020c, 0x0 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, - { 0x3d400250, 0x1705 }, - { 0x3d400254, 0x2c }, - { 0x3d40025c, 0x4000030 }, - { 0x3d400264, 0x900093e7 }, - { 0x3d40026c, 0x2005574 }, - { 0x3d400400, 0x111 }, - { 0x3d400404, 0x72ff }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x2100e07 }, - { 0x3d400498, 0x620096 }, - { 0x3d40049c, 0x1100e07 }, - { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1001 }, - { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc0026 }, - { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, - { 0x3d4020e8, 0x660048 }, - { 0x3d4020ec, 0x160048 }, - { 0x3d402100, 0xa040305 }, - { 0x3d402104, 0x30407 }, - { 0x3d402108, 0x203060b }, - { 0x3d40210c, 0x505000 }, - { 0x3d402110, 0x2040202 }, - { 0x3d402114, 0x2030202 }, - { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x302 }, - { 0x3d402130, 0x20300 }, - { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x27 }, - { 0x3d402144, 0x14000a }, - { 0x3d402180, 0x640004 }, - { 0x3d402190, 0x3818200 }, - { 0x3d402194, 0x80303 }, - { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0x599 }, - { 0x3d403020, 0x1001 }, - { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x3000a }, - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, - { 0x3d4030e8, 0x660048 }, - { 0x3d4030ec, 0x160048 }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x302 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0xa }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0x599 }, - { 0x3d400028, 0x0 }, -}; - -/* P0 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg2[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg2[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x110 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg2[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x110 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg2[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -struct dram_fsp_msg ddr_dram_fsp_msg2[] = { - { - /* P0 4000mts 1D */ - .drate = 4000, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg2, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg2), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg2, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg2), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg2, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg2), - }, - { - /* P0 4000mts 2D */ - .drate = 4000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg2, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg2), - }, -}; - -/* quad die, dual rank aka 8 GB DDR timing config params */ +/* ddr timing config params */ struct dram_timing_info dram_timing = { .ddrc_cfg = ddr_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), @@ -2154,17 +1877,36 @@ struct dram_timing_info dram_timing = { .fsp_table = { 4000, 400, 100, }, }; -/* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB DDR timing config params */ -struct dram_timing_info dram_timing2 = { - .ddrc_cfg = ddr_ddrc_cfg2, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg2), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg2, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg2), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 4000, 400, 100, }, -}; +static void apply_cfg_patch(struct dram_cfg_param *cfg, int cfg_sz, + struct dram_cfg_param *patch, int patch_sz) +{ + int i, j; + + for (i = 0; i < cfg_sz; i++) + for (j = 0; j < patch_sz; j++) + if (cfg[i].reg == patch[j].reg) + cfg[i].val = patch[j].val; +} + +void lpddr4_single_rank_training_patch(void) +{ + apply_cfg_patch(ddr_ddrc_cfg, ARRAY_SIZE(ddr_ddrc_cfg), + ddr_ddrc_cfg_single_rank_patch, + ARRAY_SIZE(ddr_ddrc_cfg_single_rank_patch)); + + apply_cfg_patch(ddr_fsp0_cfg, ARRAY_SIZE(ddr_fsp0_cfg), + ddr_fsp0_cfg_single_rank_patch, + ARRAY_SIZE(ddr_fsp0_cfg_single_rank_patch)); + + apply_cfg_patch(ddr_fsp1_cfg, ARRAY_SIZE(ddr_fsp1_cfg), + ddr_fsp1_cfg_single_rank_patch, + ARRAY_SIZE(ddr_fsp1_cfg_single_rank_patch)); + + apply_cfg_patch(ddr_fsp2_cfg, ARRAY_SIZE(ddr_fsp2_cfg), + ddr_fsp2_cfg_single_rank_patch, + ARRAY_SIZE(ddr_fsp2_cfg_single_rank_patch)); + + apply_cfg_patch(ddr_fsp0_2d_cfg, ARRAY_SIZE(ddr_fsp0_2d_cfg), + ddr_fsp0_2d_cfg_single_rank_patch, + ARRAY_SIZE(ddr_fsp0_2d_cfg_single_rank_patch)); +} diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.h b/board/toradex/verdin-imx8mp/lpddr4_timing.h new file mode 100644 index 0000000000..95e74e37ba --- /dev/null +++ b/board/toradex/verdin-imx8mp/lpddr4_timing.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2022 Toradex + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +void lpddr4_single_rank_training_patch(void); + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index 7b383cc0d5..ab5bcbc092 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -21,8 +21,7 @@ #include #include #include - -extern struct dram_timing_info dram_timing2; +#include "lpddr4_timing.h" DECLARE_GLOBAL_DATA_PTR; @@ -38,7 +37,8 @@ void spl_dram_init(void) */ if (ddr_init(&dram_timing)) { printf("Dual rank failed, attempting single rank configuration.\n"); - ddr_init(&dram_timing2); + lpddr4_single_rank_training_patch(); + ddr_init(&dram_timing); } } From c03eaf23bba56aed6c2b77fcff290650963a626d Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Mon, 3 Apr 2023 14:01:57 +0200 Subject: [PATCH 027/805] board: verdin-imx8mp: change prints in spl_dram_init function change prints to show which DDR configuration (single/dual rank) is used Signed-off-by: Emanuele Ghidoli Signed-off-by: Marcel Ziswiler --- board/toradex/verdin-imx8mp/spl.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index ab5bcbc092..73729a42b4 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -35,11 +35,17 @@ void spl_dram_init(void) /* * Try configuring for dual rank memory falling back to single rank */ - if (ddr_init(&dram_timing)) { - printf("Dual rank failed, attempting single rank configuration.\n"); - lpddr4_single_rank_training_patch(); - ddr_init(&dram_timing); + if (!ddr_init(&dram_timing)) { + puts("DDR configured as dual rank\n"); + return; } + + lpddr4_single_rank_training_patch(); + if (!ddr_init(&dram_timing)) { + puts("DDR configured as single rank\n"); + return; + } + puts("DDR configuration failed\n"); } void spl_board_init(void) From 240a274f0fc01e04902be6909d506c430935f8a7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 4 Apr 2023 00:39:37 +0200 Subject: [PATCH 028/805] ARM: dts: imx: Add WDT reboot bindings on DH i.MX6 DHSOM Add WDT reboot bindings on DH i.MX6 DHSOM to permit the platform to reboot via WDT in U-Boot. These are custom U-Boot bindings, hence they are placed in -u-boot.dtsi . Reviewed-by: Fabio Estevam Signed-off-by: Marek Vasut --- arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi index 190567ab7b..740a24d96e 100644 --- a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi @@ -8,6 +8,12 @@ aliases { eeprom0 = &eeprom0; }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &fec { @@ -25,3 +31,7 @@ gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; enable-active-high; }; + +&wdog1 { + bootph-pre-ram; +}; From 302f7e80b9d599c737bf804ee66728c67d3b739e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 4 Apr 2023 01:07:43 +0200 Subject: [PATCH 029/805] ARM: dts: imx: Add support for Data Modul i.MX8M Plus eDM SBC Add support for Data Modul i.MX8M Plus eDM SBC board. This is an evaluation board for various custom display units. Currently supported are serial console, ethernet, eMMC, SD, SPI NOR, USB. Signed-off-by: Marek Vasut --- arch/arm/dts/Makefile | 1 + .../dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi | 130 ++ arch/arm/dts/imx8mp-data-modul-edm-sbc.dts | 973 +++++++++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/data_modul/imx8mp_edm_sbc/Kconfig | 15 + board/data_modul/imx8mp_edm_sbc/MAINTAINERS | 8 + board/data_modul/imx8mp_edm_sbc/Makefile | 13 + .../imx8mp_data_modul_edm_sbc.c | 67 + board/data_modul/imx8mp_edm_sbc/imximage.cfg | 8 + .../data_modul/imx8mp_edm_sbc/lpddr4_timing.h | 11 + .../imx8mp_edm_sbc/lpddr4_timing_4G_32.c | 1849 +++++++++++++++++ board/data_modul/imx8mp_edm_sbc/spl.c | 124 ++ configs/imx8mp_data_modul_edm_sbc_defconfig | 267 +++ include/configs/imx8mp_data_modul_edm_sbc.h | 45 + 14 files changed, 3519 insertions(+) create mode 100644 arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-data-modul-edm-sbc.dts create mode 100644 board/data_modul/imx8mp_edm_sbc/Kconfig create mode 100644 board/data_modul/imx8mp_edm_sbc/MAINTAINERS create mode 100644 board/data_modul/imx8mp_edm_sbc/Makefile create mode 100644 board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c create mode 100644 board/data_modul/imx8mp_edm_sbc/imximage.cfg create mode 100644 board/data_modul/imx8mp_edm_sbc/lpddr4_timing.h create mode 100644 board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c create mode 100644 board/data_modul/imx8mp_edm_sbc/spl.c create mode 100644 configs/imx8mp_data_modul_edm_sbc_defconfig create mode 100644 include/configs/imx8mp_data_modul_edm_sbc.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 97a48327c4..8acb60d3e0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -995,6 +995,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mn-beacon-kit.dtb \ imx8mq-mnt-reform2.dtb \ imx8mq-phanbell.dtb \ + imx8mp-data-modul-edm-sbc.dtb \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ imx8mp-evk.dtb \ diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi new file mode 100644 index 0000000000..dd0f34f344 --- /dev/null +++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Marek Vasut + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + aliases { + eeprom0 = &eeprom; + mmc0 = &usdhc3; /* eMMC */ + mmc1 = &usdhc2; /* MicroSD */ + spi0 = &ecspi1; + }; + + config { + dmo,ram-coding-gpios = <&gpio3 20 0>, <&gpio4 3 0>, <&gpio4 1 0>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; +}; + +&buck4 { + bootph-pre-ram; +}; + +&buck5 { + bootph-pre-ram; +}; + +&ecspi1 { + bootph-pre-ram; + flash@0 { + bootph-pre-ram; + }; +}; + +&eqos { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&i2c3 { + bootph-pre-ram; +}; + +&pinctrl_ecspi1 { + bootph-pre-ram; +}; + +&pinctrl_hog_sbc { + bootph-pre-ram; +}; + +&pinctrl_i2c3 { + bootph-pre-ram; +}; + +&pinctrl_i2c3_gpio { + bootph-pre-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; +}; + +&pinctrl_uart3 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pmic { + bootph-pre-ram; + + regulators { + bootph-pre-ram; + }; +}; + +&uart3 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&usdhc3 { + bootph-pre-ram; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts new file mode 100644 index 0000000000..8066f7fb64 --- /dev/null +++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts @@ -0,0 +1,973 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022 Marek Vasut + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "Data Modul i.MX8M Plus eDM SBC"; + compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp"; + + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + /* There are 1/2/4 GiB options, adjusted by bootloader. */ + reg = <0x0 0x40000000 0 0x40000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_backlight>; + brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 5000000 0>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + panel: panel { + backlight = <&backlight>; + power-supply = <®_panel_vcc>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + reg_panel_vcc: regulator-panel-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_vcc_reg>; + regulator-name = "PANEL_VCC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 6 0>; + enable-active-high; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 19 0>; /* SD2_RESET */ + off-on-delay-us = <12000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3_SD"; + startup-delay-us = <100>; + vin-supply = <&buck4>; + }; + + watchdog { + /* TPS3813 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_watchdog_gpio>; + compatible = "linux,wdt-gpio"; + always-running; + gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + hw_algo = "level"; + /* Reset triggers in 2..3 seconds */ + hw_margin_ms = <1500>; + /* Disabled by default */ + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { /* W25Q128JVEI */ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; /* Up to 133 MHz */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&ecspi2 { /* Feature connector SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + /* Disabled by default, unless feature board plugged in. */ + status = "disabled"; +}; + +&ecspi3 { /* Display connector SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&eqos { /* First ethernet */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-handle = <&phy_eqos>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8031 PHY */ + phy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + /* + * Dedicated ENET_WOL# signal is unused, the PHY + * can wake the SoC up via INT signal as well. + */ + interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + qca,keep-pll-enabled; + vddio-supply = <&vddio_eqos>; + + vddio_eqos: vddio-regulator { + regulator-name = "VDDIO_EQOS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh_eqos: vddh-regulator { + regulator-name = "VDDH_EQOS"; + }; + }; + }; +}; + +&fec { /* Second ethernet */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-handle = <&phy_fec>; + phy-mode = "rgmii-id"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8031 PHY */ + phy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + /* + * Dedicated ENET_WOL# signal is unused, the PHY + * can wake the SoC up via INT signal as well. + */ + interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + qca,keep-pll-enabled; + vddio-supply = <&vddio_fec>; + + vddio_fec: vddio-regulator { + regulator-name = "VDDIO_FEC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh_fec: vddh-regulator { + regulator-name = "VDDH_FEC"; + }; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#", + "", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03", + "GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#", + "", "", "", "ENET_RST#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "ENET2_INT#", "", "", "", "", "", + "WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#", + "", "", "", "", + "", "", "", "SD2_RESET#", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "", + "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8", + "CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "", + "", "", "EEPROM_WP_1V8#", "", "", "", "", "", + "MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", + "", "M2_W_DISABLE1_1V8#", + "M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#", + "", "DIS_USB_DN1", "DIS_USB_DN2", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "WDOG_EN", "", "", + "", "SPI1_CS#", "", "", + "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3", + "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3", + "", "", "", "", + "", "SPI3_CS#", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + usb-hub@2c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_hub>; + compatible = "microchip,usb2514bi"; + reg = <0x2c>; + individual-port-switching; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + self-powered; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + compatible = "st,m41t62"; + reg = <0x68>; + interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; + }; + + pcieclk: clk@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + /* + * i.MX 8M Plus Data Sheet for Consumer Products + * 3.1.4 Operating ranges + * MIMX8ML8CVNKZAB + */ + regulators { + buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck2: BUCK2 { /* VDD_ARM */ + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck4: BUCK4 { /* VDD_3V3 */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { /* VDD_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { /* NVCC_DRAM_1V1 */ + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { /* NVCC_SNVS_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3: LDO3 { /* VDDA_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { /* PMIC_LDO4 */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5: LDO5 { /* NVCC_SD2 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c5 { /* HDMI EDID bus */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>, + <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>, + <&pinctrl_panel_expansion>; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 + >; + }; + + pinctrl_ecspi2: ecspi2-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 + >; + }; + + pinctrl_ecspi3: ecspi3-grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x44 + MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x44 + MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x44 + MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x40 + >; + }; + + pinctrl_eqos: eqos-grp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + /* ENET_RST# */ + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6 + /* ENET_INT# */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090 + >; + }; + + pinctrl_fec: fec-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + /* ENET2_RST# */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6 + /* ENET2_INT# */ + MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090 + >; + }; + + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_hog_feature: hog-feature-grp { + fsl,pins = < + /* GPIO5_IO03 */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40000006 + /* GPIO5_IO04 */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40000006 + + /* CAN_INT# */ + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x40000090 + >; + }; + + pinctrl_hog_panel: hog-panel-grp { + fsl,pins = < + /* GRAPHICS_GPIO0_1V8 */ + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x26 + >; + }; + + pinctrl_hog_misc: hog-misc-grp { + fsl,pins = < + /* ENET_WOL# -- shared by both PHYs */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090 + + /* PG_V_IN_VAR# */ + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000 + /* CSI2_PD_1V8 */ + MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0 + /* CSI2_RESET_1V8# */ + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0 + + /* DIS_USB_DN1 */ + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0 + /* DIS_USB_DN2 */ + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0 + + /* EEPROM_WP_1V8# */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x100 + /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */ + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0 + /* GRAPHICS_PRSNT_1V8# */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000 + + /* CLK_CCM_CLKO1_3V3 */ + MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10 + >; + }; + + pinctrl_hog_sbc: hog-sbc-grp { + fsl,pins = < + /* MEMCFG[0..2] straps */ + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x40000140 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40000140 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000140 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 + >; + }; + + pinctrl_i2c5: i2c5-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 + >; + }; + + pinctrl_i2c5_gpio: i2c5-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 + >; + }; + + pinctrl_panel_backlight: panel-backlight-grp { + fsl,pins = < + /* BL_ENABLE_1V8 */ + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x104 + >; + }; + + pinctrl_panel_expansion: panel-expansion-grp { + fsl,pins = < + /* DSI_RESET_1V8# */ + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x2 + /* DSI_IRQ_1V8# */ + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000090 + >; + }; + + pinctrl_panel_pwm: panel-pwm-grp { + fsl,pins = < + /* BL_PWM_3V3 */ + MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x12 + >; + }; + + pinctrl_panel_vcc_reg: panel-vcc-grp { + fsl,pins = < + /* TFT_ENABLE_1V8 */ + MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x104 + >; + }; + + pinctrl_pcie0: pcie-grp { + fsl,pins = < + /* M2_PCIE_RST# */ + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 + /* M2_W_DISABLE1_1V8# */ + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2 + /* M2_W_DISABLE2_1V8# */ + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2 + /* CLK_M2_32K768 */ + MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14 + /* M2_PCIE_WAKE# */ + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140 + /* M2_PCIE_CLKREQ# */ + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 + >; + }; + + pinctrl_pdm: pdm-grp { + fsl,pins = < + /* PDM_SEL */ + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x0 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x0 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0 + >; + }; + + pinctrl_pmic: pmic-grp { + fsl,pins = < + /* PMIC_nINT */ + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + /* RTC_IRQ# */ + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000090 + >; + }; + + pinctrl_sai1: sai1-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 + MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0xd6 + >; + }; + + pinctrl_sai2: sai2-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 + >; + }; + + pinctrl_sai3: sai3-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x49 + MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49 + MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x49 + MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x49 + MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 + MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usb_hub: usb-hub-grp { + fsl,pins = < + /* USBHUB_RESET# */ + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x4 + >; + }; + + pinctrl_usb1: usb1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x6 + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80 + >; + }; + + pinctrl_watchdog_gpio: watchdog-gpio-grp { + fsl,pins = < + /* WDOG_B# */ + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x26 + /* WDOG_EN -- ungate WDT RESET# signal propagation */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x6 + /* WDOG_KICK# / WDI */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26 + >; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_pwm>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +/* SD slot */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&uart1 { /* RS485 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "disabled"; /* Optional */ +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { /* A53 Debug */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { /* Lower plug direct */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { /* Upper plug via HUB */ + dr_mode = "host"; + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 5e4836b02f..39016dcf78 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -170,6 +170,13 @@ config TARGET_IMX8MN_VENICE select GATEWORKS_SC select MISC +config TARGET_IMX8MP_DATA_MODUL_EDM_SBC + bool "Data Modul eDM SBC i.MX8M Plus" + select BINMAN + select IMX8MP + select IMX8M_LPDDR4 + select SUPPORT_SPL + config TARGET_IMX8MP_DH_DHCOM_PDK2 bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus" select BINMAN @@ -330,6 +337,7 @@ source "board/bsh/imx8mn_smm_s2/Kconfig" source "board/cloos/imx8mm_phg/Kconfig" source "board/compulab/imx8mm-cl-iot-gate/Kconfig" source "board/data_modul/imx8mm_edm_sbc/Kconfig" +source "board/data_modul/imx8mp_edm_sbc/Kconfig" source "board/dhelectronics/dh_imx8mp/Kconfig" source "board/engicam/imx8mm/Kconfig" source "board/engicam/imx8mp/Kconfig" diff --git a/board/data_modul/imx8mp_edm_sbc/Kconfig b/board/data_modul/imx8mp_edm_sbc/Kconfig new file mode 100644 index 0000000000..d7a55b4459 --- /dev/null +++ b/board/data_modul/imx8mp_edm_sbc/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8MP_DATA_MODUL_EDM_SBC + +config SYS_BOARD + default "imx8mp_edm_sbc" + +config SYS_VENDOR + default "data_modul" + +config SYS_CONFIG_NAME + default "imx8mp_data_modul_edm_sbc" + +config IMX_CONFIG + default "board/data_modul/imx8mp_edm_sbc/imximage.cfg" + +endif diff --git a/board/data_modul/imx8mp_edm_sbc/MAINTAINERS b/board/data_modul/imx8mp_edm_sbc/MAINTAINERS new file mode 100644 index 0000000000..a67e104761 --- /dev/null +++ b/board/data_modul/imx8mp_edm_sbc/MAINTAINERS @@ -0,0 +1,8 @@ +Data Modul eDM SBC i.MX8M Plus +M: Marek Vasut +S: Maintained +F: arch/arm/dts/imx8mp-data-modul-edm-sbc.dts +F: arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi +F: board/data_modul/imx8mp_data_modul_edm_sbc/ +F: configs/imx8mp_data_modul_edm_sbc_defconfig +F: include/configs/imx8mp_data_modul_edm_sbc.h diff --git a/board/data_modul/imx8mp_edm_sbc/Makefile b/board/data_modul/imx8mp_edm_sbc/Makefile new file mode 100644 index 0000000000..28c1d62f2b --- /dev/null +++ b/board/data_modul/imx8mp_edm_sbc/Makefile @@ -0,0 +1,13 @@ +# +# Copyright (C) 2022 Marek Vasut +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o lpddr4_timing_4G_32.o +else +obj-y += imx8mp_data_modul_edm_sbc.o +endif + +obj-y += ../common/common.o diff --git a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c new file mode 100644 index 0000000000..9fbbbc1b77 --- /dev/null +++ b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Marek Vasut + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void dmo_setup_second_mac_address(void) +{ + u8 enetaddr[6]; + int ret; + + /* In case 'eth1addr' is already set in environment, do nothing. */ + ret = eth_env_get_enetaddr_by_index("eth", 1, enetaddr); + if (ret) /* valid 'eth1addr' is already set */ + return; + + /* Read 'ethaddr' from environment and validate. */ + ret = eth_env_get_enetaddr_by_index("eth", 0, enetaddr); + if (!ret) /* 'ethaddr' in environment is not valid, stop */ + return; + + /* Set 'eth1addr' as 'ethaddr' + 1 */ + enetaddr[5]++; + + eth_env_set_enetaddr_by_index("eth", 1, enetaddr); +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + /* Environment is always in eMMC boot partitions */ + return prio ? ENVL_UNKNOWN : ENVL_MMC; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + struct udevice *dev; + int ret; + + dmo_setup_boot_device(); + dmo_setup_mac_address(); + dmo_setup_second_mac_address(); + + ret = uclass_get_device_by_name(UCLASS_MISC, "usb-hub@2c", &dev); + if (ret) + printf("Error bringing up USB hub (%d)\n", ret); + + return 0; +} diff --git a/board/data_modul/imx8mp_edm_sbc/imximage.cfg b/board/data_modul/imx8mp_edm_sbc/imximage.cfg new file mode 100644 index 0000000000..8aadedb102 --- /dev/null +++ b/board/data_modul/imx8mp_edm_sbc/imximage.cfg @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing.h b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing.h new file mode 100644 index 0000000000..24569d5931 --- /dev/null +++ b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 Marek Vasut + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +extern struct dram_timing_info dmo_imx8mp_sbc_dram_timing_32_32; + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c new file mode 100644 index 0000000000..04cef3a8b9 --- /dev/null +++ b/board/data_modul/imx8mp_edm_sbc/lpddr4_timing_4G_32.c @@ -0,0 +1,1849 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x1303 }, + { 0x3d400024, 0x1c79100 }, + { 0x3d400064, 0x710106 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc0030720 }, + { 0x3d4000d4, 0xb80000 }, + { 0x3d4000dc, 0xe40036 }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x1e262028 }, + { 0x3d400104, 0x7073b }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x11040a11 }, + { 0x3d400114, 0x2050e0e }, + { 0x3d400118, 0x1010008 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20700 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x10d }, + { 0x3d400144, 0xbb005e }, + { 0x3d400180, 0x3a5001c }, + { 0x3d400184, 0x2f071e5 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49b820c }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1b0c }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x810191a }, + { 0x3d400200, 0x17 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1001 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1001 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x6 }, + { 0x100a1, 0x7 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x1 }, + { 0x100a4, 0x3 }, + { 0x100a5, 0x2 }, + { 0x100a6, 0x4 }, + { 0x100a7, 0x5 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x6 }, + { 0x130a1, 0x7 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x1 }, + { 0x130a4, 0x3 }, + { 0x130a5, 0x2 }, + { 0x130a6, 0x4 }, + { 0x130a7, 0x5 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0xe7 }, + { 0x1043, 0xe7 }, + { 0x2043, 0xe7 }, + { 0x3043, 0xe7 }, + { 0x4043, 0xe7 }, + { 0x5043, 0xe7 }, + { 0x6043, 0xe7 }, + { 0x7043, 0xe7 }, + { 0x8043, 0xe7 }, + { 0x9043, 0xe7 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3a5 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x419 }, + { 0x2000c, 0xe9 }, + { 0x2000d, 0x91c }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dmo_imx8mp_sbc_dram_timing_32_32 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 400, 100, }, +}; diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c new file mode 100644 index 0000000000..c30185e48d --- /dev/null +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Marek Vasut + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "lpddr4_timing.h" + +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +int data_modul_imx_edm_sbc_board_power_init(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("Failed to get PMIC\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output. */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */ + if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) + /* Set DVS0 to 0.85V for special case. */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c); + + /* Set DVS1 to 0.85v for suspend. */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + + /* + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H). + */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* Kernel uses OD/OD frequency for SoC. */ + + /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); + + /* Set LDO4 and CONFIG2 to enable the I2C level translator. */ + pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); + pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); + + return 0; +} + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + if (boot_dev_spl == SPI_NOR_BOOT) /* SPI NOR */ + return BOOT_DEVICE_SPI; + + if (boot_dev_spl == MMC3_BOOT) /* eMMC */ + return BOOT_DEVICE_MMC2; + + return BOOT_DEVICE_MMC1; /* SD */ +} + +void board_boot_order(u32 *spl_boot_list) +{ + int boot_device = spl_boot_device(); + + spl_boot_list[0] = boot_device; /* 1:SD 2:eMMC 8:SPI NOR */ + + if (boot_device == BOOT_DEVICE_SPI) { /* SPI, eMMC, SD */ + spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */ + spl_boot_list[2] = BOOT_DEVICE_MMC1; /* SD */ + } else if (boot_device == BOOT_DEVICE_MMC1) { /* SD, eMMC, SPI */ + spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */ + spl_boot_list[2] = BOOT_DEVICE_SPI; /* SPI */ + } else { /* eMMC, SPI, SD */ + spl_boot_list[1] = BOOT_DEVICE_SPI; /* SPI */ + spl_boot_list[2] = BOOT_DEVICE_MMC1; /* SD */ + } + + spl_boot_list[3] = BOOT_DEVICE_UART; /* YModem */ + spl_boot_list[4] = BOOT_DEVICE_NONE; +} + +static struct dram_timing_info *dram_timing_info[8] = { + &dmo_imx8mp_sbc_dram_timing_32_32, /* 32 Gbit x32 */ + NULL, /* 32 Gbit x16 */ + NULL, /* 16 Gbit x32 */ + NULL, /* 16 Gbit x16 */ + NULL, /* 8 Gbit x32 */ + NULL, /* 8 Gbit x16 */ + NULL, /* INVALID */ + NULL, /* INVALID */ +}; + +void board_init_f(ulong dummy) +{ + dmo_board_init_f(MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B, dram_timing_info); +} diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig new file mode 100644 index 0000000000..950d557089 --- /dev/null +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -0,0 +1,267 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_OFFSET=0xFFFC0000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 +CONFIG_SPL=y +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_DEBUG_UART_BASE=0x30880000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_DEBUG_UART=y +CONFIG_LTO=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb" +CONFIG_CONSOLE_MUX=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x96fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x96fc00 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4c000000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_POWER=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000 +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2081 +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x8000000 +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=16384 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_SHA1SUM=y +CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_BIND=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MBR=y +CONFIG_CMD_MMC=y +CONFIG_CMD_BKOPS_ENABLE=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_READ=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_UUID=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_SMC=y +CONFIG_HASH_VERIFY=y +CONFIG_CMD_BTRFS=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_MTDIDS_DEFAULT="nor0=flash@0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)" +CONFIG_MMC_SPEED_MODE_SET=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_TSIZE=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_DFU_TFTP=y +CONFIG_DFU_TIMEOUT=y +CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +# CONFIG_INPUT is not set +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_USB_HUB_USB251XB=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_SPL_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_DM_RTC=y +CONFIG_RTC_M41T62=y +CONFIG_CONS_INDEX=3 +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Data Modul" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_SDP_LOADADDR=0x0 +CONFIG_USB_FUNCTION_ACM=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y +CONFIG_IMX_WATCHDOG=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h new file mode 100644 index 0000000000..11ac3c00f7 --- /dev/null +++ b/include/configs/imx8mp_data_modul_edm_sbc.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 Marek Vasut + */ + +#ifndef __IMX8MP_DATA_MODUL_EDM_SBC_H +#define __IMX8MP_DATA_MODUL_EDM_SBC_H + +#include +#include +#include + +/* Link Definitions */ +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */ + +#define CFG_MXC_UART_BASE UART3_BASE_ADDR + +/* PHY needs a longer autonegotiation timeout after reset */ +#define PHY_ANEG_TIMEOUT 20000 +#define FEC_QUIRK_ENET_MAC + +#define CFG_EXTRA_ENV_SETTINGS \ + "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ + "bootlimit=3\0" \ + "devtype=mmc\0" \ + "devpart=1\0" \ + /* Give slow devices beyond USB HUB chance to come up. */ \ + "usb_pgood_delay=2000\0" \ + "dmo_update_env=" \ + "setenv dmo_update_env true ; saveenv ; saveenv\0" \ + "dmo_update_sf_write_data=" \ + "sf probe && sf update ${loadaddr} 0 ${filesize}\0" \ + "dmo_update_emmc_to_sf=" \ + "load mmc 0:1 ${loadaddr} boot/flash.bin && " \ + "run dmo_update_sf_write_data\0" \ + "dmo_update_sd_to_sf=" \ + "load mmc 1:1 ${loadaddr} boot/flash.bin && " \ + "run dmo_update_sf_write_data\0" + +#endif From 58ec2711fdc3ced5aeff9326eed496e09f694da2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 7 Mar 2023 08:51:04 +0100 Subject: [PATCH 030/805] ARM: imx: Enable LTO for DH electronics i.MX6 DHCOM Enable LTO to reduce the size of SPL, which with SPL SDP support may be close to the limit. Signed-off-by: Marek Vasut --- configs/dh_imx6_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 29b07821bf..fa2d7f3d09 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_SPI=y CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x20000000 +CONFIG_LTO=y CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y From ab53bd43dbde4dc8895a9f419e018d219eb4dc20 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 23 Mar 2023 22:06:16 -0500 Subject: [PATCH 031/805] arm64: imx: Add support for imx8mp-beacon-kit Beacon Embedded has an i.MX8M Plus development kit which consists of a SOM + baseboard. The SOM includes Bluetooth, WiFi, QSPI, eMMC, and one Ethernet PHY. The baseboard includes audio, HDMI, USB-C Dual Role port, USB Hub with five ports, a PCIe slot, and a second Ethernet PHY. The device trees are already queued for inclusion in Linux 6.3. Signed-off-by: Adam Ford Reviewed-by: Tom Rini --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi | 216 +++ arch/arm/dts/imx8mp-beacon-kit.dts | 550 ++++++ arch/arm/dts/imx8mp-beacon-som.dtsi | 416 ++++ arch/arm/mach-imx/imx8m/Kconfig | 11 + board/beacon/imx8mp/Kconfig | 16 + board/beacon/imx8mp/MAINTAINERS | 6 + board/beacon/imx8mp/Makefile | 13 + board/beacon/imx8mp/imx8mp_beacon.c | 35 + board/beacon/imx8mp/imx8mp_beacon.env | 19 + board/beacon/imx8mp/imximage-8mp-lpddr4.cfg | 9 + board/beacon/imx8mp/lpddr4_timing.c | 1881 +++++++++++++++++++ board/beacon/imx8mp/spl.c | 132 ++ configs/imx8mp_beacon_defconfig | 182 ++ doc/board/beacon/beacon-imx8mp.rst | 52 + doc/board/beacon/index.rst | 9 + doc/board/index.rst | 1 + include/configs/imx8mp_beacon.h | 29 + 18 files changed, 3578 insertions(+) create mode 100644 arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-beacon-kit.dts create mode 100644 arch/arm/dts/imx8mp-beacon-som.dtsi create mode 100644 board/beacon/imx8mp/Kconfig create mode 100644 board/beacon/imx8mp/MAINTAINERS create mode 100644 board/beacon/imx8mp/Makefile create mode 100644 board/beacon/imx8mp/imx8mp_beacon.c create mode 100644 board/beacon/imx8mp/imx8mp_beacon.env create mode 100644 board/beacon/imx8mp/imximage-8mp-lpddr4.cfg create mode 100644 board/beacon/imx8mp/lpddr4_timing.c create mode 100644 board/beacon/imx8mp/spl.c create mode 100644 configs/imx8mp_beacon_defconfig create mode 100644 doc/board/beacon/beacon-imx8mp.rst create mode 100644 doc/board/beacon/index.rst create mode 100644 include/configs/imx8mp_beacon.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8acb60d3e0..0a9b1f7749 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -995,6 +995,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mn-beacon-kit.dtb \ imx8mq-mnt-reform2.dtb \ imx8mq-phanbell.dtb \ + imx8mp-beacon-kit.dtb \ imx8mp-data-modul-edm-sbc.dtb \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi new file mode 100644 index 0000000000..5ca631e9d8 --- /dev/null +++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Logic PD, Inc DBA Beacon EmbeddedWorks + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + bootph-pre-ram; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-pre-ram; +}; + +&crypto { + bootph-pre-ram; +}; + +&eqos { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +ðphy0 { + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&fec { + phy-reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&flexspi { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&i2c1 { + bootph-pre-ram; +}; + +&i2c2 { + bootph-pre-ram; +}; + +&i2c3 { + bootph-pre-ram; +}; + +&pca6416 { + compatible = "ti,tca6416"; + label = "exp4"; +}; + +&pca6416_1 { + compatible = "ti,tca6416"; + label = "exp4"; +}; + +&pca6416_3 { + compatible = "ti,tca6416"; + label = "exp2"; +}; + +&pinctrl_i2c1 { + bootph-pre-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pinctrl_wdog { + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; + u-boot,off-on-delay-us = <20000>; +}; + +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { + bootph-pre-ram; +}; + +&tpm { + compatible = "tcg,tpm_tis-spi"; +}; + +&uart2 { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&usdhc2 { + bootph-pre-ram; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&usdhc3 { + bootph-pre-ram; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&usb3_0 { + dma-ranges = <0x40000000 0x40000000 0xc0000000>; + /delete-property/ power-domains; +}; + +&usb3_1 { + dma-ranges = <0x40000000 0x40000000 0xc0000000>; + /delete-property/ power-domains; +}; + +&usb_dwc3_0 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&usb_dwc3_1 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&usdhc1 { + status = "disabled"; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mp-beacon-kit.dts b/arch/arm/dts/imx8mp-beacon-kit.dts new file mode 100644 index 0000000000..cdae45a48c --- /dev/null +++ b/arch/arm/dts/imx8mp-beacon-kit.dts @@ -0,0 +1,550 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks + */ + +/dts-v1/; + +#include +#include +#include "imx8mp.dtsi" +#include "imx8mp-beacon-som.dtsi" + +/ { + model = "Beacon EmbeddedWorks i.MX8MPlus Development kit"; + compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + }; + + chosen { + stdout-path = &uart2; + }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + port@1 { + reg = <1>; + + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-0 { + label = "btn0"; + linux,code = ; + gpios = <&pca6416_1 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + wakeup-source; + }; + + button-1 { + label = "btn1"; + linux,code = ; + gpios = <&pca6416_1 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + wakeup-source; + }; + + button-2 { + label = "btn2"; + linux,code = ; + gpios = <&pca6416_1 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + wakeup-source; + }; + + button-3 { + label = "btn3"; + linux,code = ; + gpios = <&pca6416_1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led3>; + + led-0 { + label = "gen_led0"; + gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "gen_led1"; + gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "gen_led2"; + gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + label = "heartbeat"; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + pcie0_refclk: clock-pcie { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <20000>; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm: tpm@0 { + compatible = "infineon,slb9670"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + spi-max-frequency = <18500000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@3 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <150000>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&gpio2 { + usb-mux-hog { + gpio-hog; + gpios = <20 0>; + output-low; + line-name = "USB-C Mux En"; + }; +}; + +&i2c2 { + clock-frequency = <384000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pca6416_3: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&i2c3 { + /* Connected to USB Hub */ + usb-typec@52 { + compatible = "nxp,ptn5110"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "host"; + source-pdos = ; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <384000>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6414>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pca6416_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + usb-hub-hog { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "USB Hub Enable"; + }; + }; + + usb-typec@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hd3ss3220>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&usb3_phy0 { + vbus-supply = <®_usb1_host_vbus>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x140 + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_hd3ss3220: hd3ss3220grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_led3: led3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41 + >; + }; + + pinctrl_pcal6414: pcal6414-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 /* PCIe_nDIS */ + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x10 /* PCIe_nRST */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */ + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1d6 /* IRQ */ + >; + }; + + pinctrl_typec: typec1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0xc4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-beacon-som.dtsi b/arch/arm/dts/imx8mp-beacon-som.dtsi new file mode 100644 index 0000000000..e5da908047 --- /dev/null +++ b/arch/arm/dts/imx8mp-beacon-som.dtsi @@ -0,0 +1,416 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks + */ + +/ { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + }; + + reg_wl_bt: regulator-wifi-bt { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wl_bt>; + regulator-name = "wl-bt-pow-dwn"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; + startup-delay-us = <70000>; + regulator-always-on; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + snps,force_thresh_dma_mode; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@3 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <384000>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <384000>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; /* Manufacturing EEPROM programmed at factory */ + }; + + rtc: rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + vmmc-supply = <®_wl_bt>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + keep-power-in-suspend; + wakeup-source; + non-removable; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mwifiex: wifi@1 { + compatible = "marvell,sd8997"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 + >; + }; + + pinctrl_reg_wl_bt: reg-wl-btgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140 + >; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 39016dcf78..dc51f971d4 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -177,6 +177,16 @@ config TARGET_IMX8MP_DATA_MODUL_EDM_SBC select IMX8M_LPDDR4 select SUPPORT_SPL +config TARGET_IMX8MP_BEACON + bool "imx8mm Beacon Embedded devkit" + select BINMAN + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL + config TARGET_IMX8MP_DH_DHCOM_PDK2 bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus" select BINMAN @@ -333,6 +343,7 @@ endchoice source "board/advantech/imx8mp_rsb3720a1/Kconfig" source "board/beacon/imx8mm/Kconfig" source "board/beacon/imx8mn/Kconfig" +source "board/beacon/imx8mp/Kconfig" source "board/bsh/imx8mn_smm_s2/Kconfig" source "board/cloos/imx8mm_phg/Kconfig" source "board/compulab/imx8mm-cl-iot-gate/Kconfig" diff --git a/board/beacon/imx8mp/Kconfig b/board/beacon/imx8mp/Kconfig new file mode 100644 index 0000000000..3c0fca9be8 --- /dev/null +++ b/board/beacon/imx8mp/Kconfig @@ -0,0 +1,16 @@ +if TARGET_IMX8MP_BEACON + +config SYS_BOARD + default "imx8mp" + +config SYS_VENDOR + default "beacon" + +config SYS_CONFIG_NAME + default "imx8mp_beacon" + +config IMX_CONFIG + default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg" + + +endif diff --git a/board/beacon/imx8mp/MAINTAINERS b/board/beacon/imx8mp/MAINTAINERS new file mode 100644 index 0000000000..3750551a4a --- /dev/null +++ b/board/beacon/imx8mp/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8MP Beacon EmbeddedWorks Devkit +M: Adam Ford +S: Maintained +F: board/beacon/imx8mp/ +F: include/configs/imx8mp_beacon.h +F: configs/imx8mp_beacon_defconfig diff --git a/board/beacon/imx8mp/Makefile b/board/beacon/imx8mp/Makefile new file mode 100644 index 0000000000..264720f6d4 --- /dev/null +++ b/board/beacon/imx8mp/Makefile @@ -0,0 +1,13 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks +# + +obj-y += imx8mp_beacon.o +obj-y += ../../freescale/common/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/beacon/imx8mp/imx8mp_beacon.c b/board/beacon/imx8mp/imx8mp_beacon.c new file mode 100644 index 0000000000..8963a51fbb --- /dev/null +++ b/board/beacon/imx8mp/imx8mp_beacon.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks */ + +#include +#include +#include +#include + +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +} + +#if IS_ENABLED(CONFIG_NET) +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + int ret = 0; + + if (CONFIG_IS_ENABLED(FEC_MXC)) + setup_fec(); + + return ret; +} diff --git a/board/beacon/imx8mp/imx8mp_beacon.env b/board/beacon/imx8mp/imx8mp_beacon.env new file mode 100644 index 0000000000..ec9fbd3332 --- /dev/null +++ b/board/beacon/imx8mp/imx8mp_beacon.env @@ -0,0 +1,19 @@ +boot_fdt=try +boot_fit=no +console=ttymxc1,115200 +fdt_addr=0x43000000 +fdt_addr_r=0x43000000 +fdt_file=imx8mp-beacon-kit.dtb +finduuid=part uuid mmc ${mmcdev}:2 uuid +image=Image +kernel_addr_r=0x40480000 +loadfdt=echo ${fdt_file}; fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file} +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +mmcargs=setenv bootargs console=${console} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs} +mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if run loadfdt; then booti ${loadaddr} - ${fdt_addr_r}; else echo WARN: Cannot load the DT; fi; fi; +mmcdev=1 +mmcpart=1 +netargs=setenv bootargs ${jh_clk} console=${console} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr_r}; else echo WARN: Cannot load the DT; fi; fi; +optargs=audit=0 video=LVDS-1:d video=LVDS-2:d +scriptaddr=0x40480000 diff --git a/board/beacon/imx8mp/imximage-8mp-lpddr4.cfg b/board/beacon/imx8mp/imximage-8mp-lpddr4.cfg new file mode 100644 index 0000000000..6dedf1724a --- /dev/null +++ b/board/beacon/imx8mp/imximage-8mp-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/beacon/imx8mp/lpddr4_timing.c b/board/beacon/imx8mp/lpddr4_timing.c new file mode 100644 index 0000000000..ae0b84870e --- /dev/null +++ b/board/beacon/imx8mp/lpddr4_timing.c @@ -0,0 +1,1881 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x1322 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x3d017c }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400070, 0x1027f54 }, +#else + { 0x3d400070, 0x7027f90 }, +#endif + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x2028112a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x184 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + { 0x3d400200, 0x13 }, + { 0x3d40020c, 0x13131300 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x50505 }, + { 0x3d400214, 0x4040404 }, + { 0x3d400218, 0x68040404 }, +#else + { 0x3d400200, 0x16 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x68070707 }, +#endif + { 0x3d40021c, 0xf08 }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1020 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0x60026 }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040105 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x27 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1020 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x3000a }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0xa }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x465 }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; + +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) +void board_dram_ecc_scrub(void) +{ + ddrc_inline_ecc_scrub(0x0, 0x3ffffff); + ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff); + ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff); + ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff); + ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff); + ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff); + ddrc_inline_ecc_scrub(0x8000000, 0xbffffff); + ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff); + ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff); + ddrc_inline_ecc_scrub(0xc000000, 0xfffffff); + ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff); + ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff); + ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff); + ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff); + ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff); + ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff); + ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff); + ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff); + ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff); + ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff); + ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff); + ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff); +} +#endif diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c new file mode 100644 index 0000000000..591e8ca9ab --- /dev/null +++ b/board/beacon/imx8mp/spl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize caam_jr: %d\n", ret); + } + /* + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does + * not allow to change it. Should set the clock after PMIC + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) + * set by ROM for ND VDD_SOC + */ + if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) { + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + } +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV)) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); + + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_SPL_LOAD_FIT) +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + ret = spl_early_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig new file mode 100644 index 0000000000..ca6ee2fe05 --- /dev/null +++ b/configs/imx8mp_beacon_defconfig @@ -0,0 +1,182 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-beacon-kit" +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y +CONFIG_TARGET_IMX8MP_BEACON=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x960000 +CONFIG_SPL=y +CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y +CONFIG_ARMV8_MULTIENTRY=y +CONFIG_ARMV8_SET_SMPEN=y +# CONFIG_PSCI_RESET is not set +CONFIG_ARMV8_PSCI=y +CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4 +CONFIG_ARMV8_PSCI_RELOCATE=y +CONFIG_ARMV8_SECURE_BASE=0x970000 +CONFIG_ARMV8_EA_EL3_FIRST=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" +CONFIG_DEFAULT_FDT_FILE="imx8mp-beacon-kit.dtb" +# CONFIG_SYS_DEVICE_NULLDEV is not set +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x98fc00 +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_SYS_BOOTM_LEN=0x2000000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="imx8mp_beacon" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth1" +CONFIG_SPL_DM=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MP=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y +CONFIG_GPIO_HOG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +# CONFIG_DM_RNG is not set +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_TPM2_TIS_SPI=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_MX7 is not set +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_SDP_LOADADDR=0x0 +CONFIG_USB_FUNCTION_ACM=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_IMX_WATCHDOG=y +CONFIG_TPM=y +# CONFIG_SPL_SHA512 is not set +# CONFIG_SPL_SHA384 is not set diff --git a/doc/board/beacon/beacon-imx8mp.rst b/doc/board/beacon/beacon-imx8mp.rst new file mode 100644 index 0000000000..375931c07d --- /dev/null +++ b/doc/board/beacon/beacon-imx8mp.rst @@ -0,0 +1,52 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Beacon EmbeddedWorks i.MX8M Plus Devkit +====================================================== + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get DDR firmware +- Build U-Boot +- Burn U-Noot to microSD Card +- Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone https://github.com/nxp-imx/imx-atf.git -b v2.6 + $ make PLAT=imx8mp bl31 CROSS_COMPILE=aarch64-linux-gnu- + $ cp build/imx8mn/release/bl31.bin ../ + +Get the DDR firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.15.bin + $ chmod +x firmware-imx-8.15.bin + $ ./firmware-imx-8.15 + $ cp firmware-imx-8.15/firmware/ddr/synopsys/lpddr4*.bin . + +Build U-Boot +------------ + +.. code-block:: bash + + $ make imx8mp_beacon_defconfig + $ make CROSS_COMPILE=aarch64-linux-gnu- + +Burn U-Boot to microSD Card +--------------------------- + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 + +Boot +---- +Set baseboard DIP switch: +S17: 1100XXXX diff --git a/doc/board/beacon/index.rst b/doc/board/beacon/index.rst new file mode 100644 index 0000000000..1fe1046a4c --- /dev/null +++ b/doc/board/beacon/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Beacon +====== + +.. toctree:: + :maxdepth: 2 + + beacon-imx8mp diff --git a/doc/board/index.rst b/doc/board/index.rst index 618d22e616..69e2cd5fb8 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -14,6 +14,7 @@ Board-specific doc apple/index armltd/index atmel/index + beacon/index broadcom/index bsh/index cloos/index diff --git a/include/configs/imx8mp_beacon.h b/include/configs/imx8mp_beacon.h new file mode 100644 index 0000000000..ee0fd07e65 --- /dev/null +++ b/include/configs/imx8mp_beacon.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks + */ + +#ifndef __IMX8MP_BEACON_H +#define __IMX8MP_BEACON_H + +#include + +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#if defined(CONFIG_CMD_NET) +#define PHY_ANEG_TIMEOUT 20000 +#endif + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 + +/* Totally 6GB DDR */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ + +#endif From 2532eadcd5bfe9e98fff5585785af737e475fb4c Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 15 Mar 2023 13:01:16 +0200 Subject: [PATCH 032/805] configs: convert NXP LS1028A RDB and QDS to DM_SERIAL Since the device trees are more or less synchronized with Linux, the only necessary changes are to enable CONFIG_DM_SERIAL and the DM_SERIAL driver for ns16550 (ns16550.c rather than serial_ns16550.c). ls1028aqds_tfa_lpuart_defconfig already uses DM_SERIAL for the LPUART driver, so I didn't touch that. Signed-off-by: Vladimir Oltean Reviewed-by: Ioana Ciornei Signed-off-by: Peng Fan --- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 3 ++- configs/ls1028aqds_tfa_defconfig | 3 ++- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 3 ++- configs/ls1028ardb_tfa_defconfig | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index ae01d83de9..15ac90fa65 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -86,7 +86,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 2361c35b25..78dd20a0e5 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -92,7 +92,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index af560c61fb..2c3c9bd080 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -80,7 +80,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 93e87212db..3384b98dae 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -86,7 +86,8 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y From 204d574fe4b01a9468ac5256cf3cffdd874d204a Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 15 Mar 2023 13:04:09 +0200 Subject: [PATCH 033/805] arch: arm: dts: fsl-ls1088a.dtsi: add an 'soc' node The u-boot dts for these boards do not have an soc node, unlike its Linux counterpart. This patch just adds the soc node as seen in Linux, the next patches will move some nodes under it. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- arch/arm/dts/fsl-ls1088a.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 9b7c54b260..36ec0ff51f 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -35,6 +35,15 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + + }; + i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; From 2b7d2c236bc246b3640268675daeda68f24a98d4 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 15 Mar 2023 13:04:10 +0200 Subject: [PATCH 034/805] arch: arm: dts: fsl-ls1088a.dtsi: move the serial nodes under soc Move the serial nodes under the soc node. No changes are made to the nodes, just their location is changed. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- arch/arm/dts/fsl-ls1088a.dtsi | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 36ec0ff51f..0eb0f6c41a 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -42,6 +42,21 @@ ranges; dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + serial0: serial@21c0500 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + clock-frequency = <0>; /* Updated by bootloader */ + interrupts = <0 32 0x1>; /* edge triggered */ + }; + + serial1: serial@21c0600 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + clock-frequency = <0>; /* Updated by bootloader */ + interrupts = <0 32 0x1>; /* edge triggered */ + }; }; i2c0: i2c@2000000 { @@ -76,22 +91,6 @@ interrupts = <0 35 4>; }; - serial0: serial@21c0500 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ - }; - - serial1: serial@21c0600 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ - }; - dspi: dspi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; From 571c49789d419548c1573864b170e2c3db80d064 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 15 Mar 2023 13:04:11 +0200 Subject: [PATCH 035/805] arch: arm: dts: fsl-ls1088a.dtsi: sync serial nodes with Linux Sync the serial nodes of the LS1088A based boards with their representation in Linux. We also imported the clockgen and sysclk nodes which are dependencies. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- arch/arm/dts/fsl-ls1088a-qds.dtsi | 8 ++++++ arch/arm/dts/fsl-ls1088a-rdb.dts | 8 ++++++ arch/arm/dts/fsl-ls1088a-ten64.dts | 6 +++-- arch/arm/dts/fsl-ls1088a.dtsi | 39 +++++++++++++++++++++--------- 4 files changed, 48 insertions(+), 13 deletions(-) diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi index 85dc7457bf..4d21d4fbd5 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi @@ -132,6 +132,14 @@ }; }; +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + &dspi { bus-num = <0>; status = "okay"; diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts index 01f8fcb61a..c63d4158e4 100644 --- a/arch/arm/dts/fsl-ls1088a-rdb.dts +++ b/arch/arm/dts/fsl-ls1088a-rdb.dts @@ -142,6 +142,14 @@ }; }; +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + &qspi { status = "okay"; diff --git a/arch/arm/dts/fsl-ls1088a-ten64.dts b/arch/arm/dts/fsl-ls1088a-ten64.dts index 43b669c642..55a7d41fb0 100644 --- a/arch/arm/dts/fsl-ls1088a-ten64.dts +++ b/arch/arm/dts/fsl-ls1088a-ten64.dts @@ -20,6 +20,8 @@ compatible = "traverse,ten64", "fsl,ls1088a"; aliases { + serial0 = &duart0; + serial1 = &duart1; spi0 = &qspi; }; @@ -164,11 +166,11 @@ status = "okay"; }; -&serial0 { +&duart0 { status = "okay"; }; -&serial1 { +&duart1 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 0eb0f6c41a..b094bcf67c 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -2,9 +2,10 @@ /* * NXP ls1088a SOC common device tree source * - * Copyright 2017, 2020-2021 NXP + * Copyright 2017, 2020-2021, 2023 NXP */ +#include #include / { compatible = "fsl,ls1088a"; @@ -35,6 +36,13 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -42,20 +50,29 @@ ranges; dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; - serial0: serial@21c0500 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clockgen: clocking@1300000 { + compatible = "fsl,ls1088a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; }; - serial1: serial@21c0600 { - device_type = "serial"; + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21c0600 0x0 0x100>; - clock-frequency = <0>; /* Updated by bootloader */ - interrupts = <0 32 0x1>; /* edge triggered */ + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; }; From a593c1fec579ea2e23ace4f06b06d8c168db2d05 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 15 Mar 2023 13:04:12 +0200 Subject: [PATCH 036/805] arch: arm: dts: fsl-ls1088a.dtsi: tag serial nodes with bootph-all Tag the serial nodes with bootph-all in order to have these nodes and the drivers available before relocation. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- arch/arm/dts/fsl-ls1088a.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index b094bcf67c..4782b83515 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -64,6 +64,7 @@ QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; + bootph-all; }; duart1: serial@21c0600 { @@ -73,6 +74,7 @@ QORIQ_CLK_PLL_DIV(4)>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; + bootph-all; }; }; From c1186a99bf083b8731a8c615711b5ac943b06e82 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 15 Mar 2023 13:04:13 +0200 Subject: [PATCH 037/805] configs: ls1088a: enable DM_SERIAL Now that the DT nodes for the serial devices are in place for these boards, enable DM_SERIAL in the associated configs. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- configs/ls1088aqds_tfa_defconfig | 4 +++- configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 4 +++- configs/ls1088ardb_tfa_defconfig | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 419572470e..09e273ab42 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -118,7 +118,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 5633901e96..558958c901 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -90,7 +90,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index fd466a5061..89f814130d 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -96,7 +96,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y From 677fb953720e664f1603a36041f5aa31599d2f57 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 15 Mar 2023 13:04:14 +0200 Subject: [PATCH 038/805] arch: arm: dts: fsl-lx2160a.dtsi: add an 'soc' node The u-boot dts for these boards do not have an soc node, unlike its Linux counterpart. This patch just adds the soc node as seen in Linux, the next patches will move some nodes under it. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- arch/arm/dts/fsl-lx2160a.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 57c7d3ef71..08f160f698 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -27,6 +27,14 @@ clock-output-names = "sysclk"; }; + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + }; + crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <10>; From 853493b9f9d6b2ca9ebf239820ba0636b5a957e7 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 15 Mar 2023 13:04:15 +0200 Subject: [PATCH 039/805] arch: arm: dts: fsl-lx2160a.dtsi: move the serial nodes under soc Move the serial nodes under the soc node. No changes are made to the nodes, just their location is changed. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- arch/arm/dts/fsl-lx2160a.dtsi | 56 +++++++++++++++++------------------ 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 08f160f698..58a408d2dc 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -33,6 +33,34 @@ #size-cells = <2>; ranges; dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; + + uart0: serial@21c0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21c0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + uart1: serial@21d0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21d0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + uart2: serial@21e0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21e0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + uart3: serial@21f0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21f0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; }; crypto: crypto@8000000 { @@ -185,34 +213,6 @@ status = "disabled"; }; - uart0: serial@21c0000 { - compatible = "arm,pl011"; - reg = <0x0 0x21c0000 0x0 0x1000>; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - uart1: serial@21d0000 { - compatible = "arm,pl011"; - reg = <0x0 0x21d0000 0x0 0x1000>; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - uart2: serial@21e0000 { - compatible = "arm,pl011"; - reg = <0x0 0x21e0000 0x0 0x1000>; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - uart3: serial@21f0000 { - compatible = "arm,pl011"; - reg = <0x0 0x21f0000 0x0 0x1000>; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - dspi0: dspi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; From dea0f1a27fb51d1775586c10ae080335d467d49c Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 15 Mar 2023 13:04:16 +0200 Subject: [PATCH 040/805] arch: arm: dts: fsl-lx2160a.dtsi: sync serial nodes with Linux Sync the serial nodes of the LX2160A based boards with their representation in Linux. We also imported the clockgen and sysclk nodes which are dependencies. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- arch/arm/dts/fsl-lx2160a-qds.dtsi | 11 ++++++++++- arch/arm/dts/fsl-lx2160a-rdb.dts | 11 ++++++++++- arch/arm/dts/fsl-lx2160a.dtsi | 22 +++++++++++++--------- 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi index 6635c52585..e96605b1b4 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dtsi +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -2,7 +2,7 @@ /* * NXP LX2160AQDS common device tree source * - * Copyright 2018-2020 NXP + * Copyright 2018-2020, 2023 NXP * */ @@ -11,6 +11,7 @@ / { aliases { spi0 = &fspi; + serial0 = &uart0; }; }; @@ -286,3 +287,11 @@ &sata3 { status = "okay"; }; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index 399409776e..aaa59598bd 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -5,7 +5,7 @@ * Author: Priyanka Jain * Sriram Dash * - * Copyright 2018 NXP + * Copyright 2018, 2023 NXP * */ @@ -18,6 +18,7 @@ compatible = "fsl,lx2160ardb", "fsl,lx2160a"; aliases { spi0 = &fspi; + serial0 = &uart0; }; }; @@ -137,3 +138,11 @@ &sata3 { status = "okay"; }; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 58a408d2dc..0b0f317f30 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -2,7 +2,7 @@ /* * NXP lx2160a SOC common device tree source * - * Copyright 2018-2021 NXP + * Copyright 2018-2021, 2023 NXP * */ @@ -35,30 +35,34 @@ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; uart0: serial@21c0000 { - compatible = "arm,pl011"; + compatible = "arm,sbsa-uart","arm,pl011"; reg = <0x0 0x21c0000 0x0 0x1000>; - clocks = <&clockgen 4 0>; + interrupts = ; + current-speed = <115200>; status = "disabled"; }; uart1: serial@21d0000 { - compatible = "arm,pl011"; + compatible = "arm,sbsa-uart","arm,pl011"; reg = <0x0 0x21d0000 0x0 0x1000>; - clocks = <&clockgen 4 0>; + interrupts = ; + current-speed = <115200>; status = "disabled"; }; uart2: serial@21e0000 { - compatible = "arm,pl011"; + compatible = "arm,sbsa-uart","arm,pl011"; reg = <0x0 0x21e0000 0x0 0x1000>; - clocks = <&clockgen 4 0>; + interrupts = ; + current-speed = <115200>; status = "disabled"; }; uart3: serial@21f0000 { - compatible = "arm,pl011"; + compatible = "arm,sbsa-uart","arm,pl011"; reg = <0x0 0x21f0000 0x0 0x1000>; - clocks = <&clockgen 4 0>; + interrupts = ; + current-speed = <115200>; status = "disabled"; }; }; From f2ac9f6a17aeffbca1926f4364ccddce329659b1 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 15 Mar 2023 13:04:17 +0200 Subject: [PATCH 041/805] arch: arm: dts: fsl-lx2160a.dtsi: tag serial nodes with bootph-all Tag the serial nodes with bootph-all in order to have these nodes and the drivers available before relocation. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- arch/arm/dts/fsl-lx2160a.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 0b0f317f30..680c69c7b7 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -40,6 +40,7 @@ interrupts = ; current-speed = <115200>; status = "disabled"; + bootph-all; }; uart1: serial@21d0000 { @@ -48,6 +49,7 @@ interrupts = ; current-speed = <115200>; status = "disabled"; + bootph-all; }; uart2: serial@21e0000 { @@ -56,6 +58,7 @@ interrupts = ; current-speed = <115200>; status = "disabled"; + bootph-all; }; uart3: serial@21f0000 { @@ -64,6 +67,7 @@ interrupts = ; current-speed = <115200>; status = "disabled"; + bootph-all; }; }; From 8ac04e9062fc65bb09754cefefc096d554c6881c Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Wed, 15 Mar 2023 13:04:18 +0200 Subject: [PATCH 042/805] board: freescale: lx2160a: remove the PL01X device instantiation There is no need for the board file to instantiate a PL01X platform device anymore. This is all taken care of by the DM code which now will probe the device based on the DT node. Signed-off-by: Ioana Ciornei Signed-off-by: Peng Fan --- board/freescale/lx2160a/lx2160a.c | 34 ------------------------------- 1 file changed, 34 deletions(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 33842d0217..2a752054cd 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -55,45 +55,11 @@ DECLARE_GLOBAL_DATA_PTR; -static struct pl01x_serial_plat serial0 = { -#if CONFIG_CONS_INDEX == 0 - .base = CFG_SYS_SERIAL0, -#elif CONFIG_CONS_INDEX == 1 - .base = CFG_SYS_SERIAL1, -#else -#error "Unsupported console index value." -#endif - .type = TYPE_PL011, -}; - -U_BOOT_DRVINFO(nxp_serial0) = { - .name = "serial_pl01x", - .plat = &serial0, -}; - -static struct pl01x_serial_plat serial1 = { - .base = CFG_SYS_SERIAL1, - .type = TYPE_PL011, -}; - -U_BOOT_DRVINFO(nxp_serial1) = { - .name = "serial_pl01x", - .plat = &serial1, -}; - -static void uart_get_clock(void) -{ - serial0.clock = get_serial_clock(); - serial1.clock = get_serial_clock(); -} - int board_early_init_f(void) { #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD) i2c_early_init_f(); #endif - /* get required clock for UART IP */ - uart_get_clock(); #ifdef CONFIG_EMC2305 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0); From 046b8ef438a26713f94b38d1aa8e131d8049921b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 23 Mar 2023 14:57:57 -0400 Subject: [PATCH 043/805] pytest: Update requirements to match sphinx versions In order to better make use of pip caches, and also for better overall consistency, we should use the same versions of packages in each of our python requirements files. Update pytest to use the newer versions of packages we use in sphinx builds. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- test/py/requirements.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/test/py/requirements.txt b/test/py/requirements.txt index e241780f92..86d6266053 100644 --- a/test/py/requirements.txt +++ b/test/py/requirements.txt @@ -8,21 +8,21 @@ fixtures==3.0.0 importlib-metadata==0.23 linecache2==1.0.0 more-itertools==7.2.0 -packaging==19.2 +packaging==21.3 pbr==5.4.3 pluggy==0.13.0 py==1.10.0 pycryptodomex==3.9.8 pyelftools==0.27 pygit2==1.9.2 -pyparsing==2.4.2 +pyparsing==3.0.7 pytest==6.2.5 pytest-xdist==2.5.0 python-mimeparse==1.6.0 python-subunit==1.3.0 -requests==2.25.1 +requests==2.27.1 setuptools==58.3.0 -six==1.12.0 +six==1.16.0 testtools==2.3.0 traceback2==1.4.0 unittest2==1.1.0 From 866f30205b50e0fc9834852f46def55bf84c20a5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 23 Mar 2023 14:57:58 -0400 Subject: [PATCH 044/805] Dockerfile: Populate a pip cache Given the number of jobs in CI we have which use python and pip install packages, we should do this once in the Dockerfile, in order to populate the cache. We let each job continue to create and use the virtual environments they need to facilitate making updates to these environments easier. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- tools/docker/Dockerfile | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index bd02531be2..20c2b2a9d6 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -265,6 +265,17 @@ RUN echo uboot ALL=NOPASSWD: ALL > /etc/sudoers.d/uboot RUN useradd -m -U uboot USER uboot:uboot +# Populate the cache for pip to use. Get these via wget as the +# COPY / ADD directives don't work as we need them to. +RUN wget -O /tmp/pytest-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/test/py/requirements.txt +RUN wget -O /tmp/sphinx-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/doc/sphinx/requirements.txt +RUN virtualenv -p /usr/bin/python3 /tmp/venv && \ + . /tmp/venv/bin/activate && \ + pip install -r /tmp/pytest-requirements.txt \ + -r /tmp/sphinx-requirements.txt && \ + deactivate && \ + rm -rf /tmp/venv /tmp/pytest-requirements.txt /tmp/sphinx-requirements.txt + # Create the buildman config file RUN /bin/echo -e "[toolchain]\nroot = /usr" > ~/.buildman RUN /bin/echo -e "kernelorg = /opt/gcc-12.2.0-nolibc/*" >> ~/.buildman From 65fa29d6c39235a859f185465b1363814ffcc26c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 28 Mar 2023 14:54:50 -0400 Subject: [PATCH 045/805] smartweb: Enable LTO In order to prepare for slight size growth due to reworking linker list support, enable LTO here to save more space again. Signed-off-by: Tom Rini Reviewed-by: Heiko Schocher --- configs/smartweb_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 4cbdab0b37..836e0c002d 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x180000 CONFIG_SYS_LOAD_ADDR=0x22000000 +CONFIG_LTO=y CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 From d0e3378ad73ed80d4baab95e2c3aaa0a18ae7747 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 28 Mar 2023 14:54:51 -0400 Subject: [PATCH 046/805] linker_lists: Rework start/end macros to not rely on undefined behavior Per the GCC bug listed below, the way we do linker lists is relying on undefined behavior that seems to work in gcc, but doesn't always work in clang. Andrew suggests rewriting our start/end macros in a different way (as implemented here, from what he said in comment 1) to avoid these problems. Reported-by: AdityaK Suggested-by: Andrew Pinski Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108915 Signed-off-by: Tom Rini Reviewed-by: Simon Glass Reviewed-by: Andrew Pinski --- include/linker_lists.h | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/include/linker_lists.h b/include/linker_lists.h index d3da9d44e8..f9a2ee0c76 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -127,7 +127,9 @@ static char start[0] __aligned(CONFIG_LINKER_LIST_ALIGN) \ __attribute__((unused)) \ __section("__u_boot_list_2_"#_list"_1"); \ - (_type *)&start; \ + _type * tmp = (_type *)&start; \ + asm("":"+r"(tmp)); \ + tmp; \ }) /** @@ -153,7 +155,9 @@ ({ \ static char end[0] __aligned(4) __attribute__((unused)) \ __section("__u_boot_list_2_"#_list"_3"); \ - (_type *)&end; \ + _type * tmp = (_type *)&end; \ + asm("":"+r"(tmp)); \ + tmp; \ }) /** * ll_entry_count() - Return the number of elements in linker-generated array @@ -247,7 +251,9 @@ ({ \ static char start[0] __aligned(4) __attribute__((unused)) \ __section("__u_boot_list_1"); \ - (_type *)&start; \ + _type * tmp = (_type *)&start; \ + asm("":"+r"(tmp)); \ + tmp; \ }) /** @@ -270,7 +276,9 @@ ({ \ static char end[0] __aligned(4) __attribute__((unused)) \ __section("__u_boot_list_3"); \ - (_type *)&end; \ + _type * tmp = (_type *)&end; \ + asm("":"+r"(tmp)); \ + tmp; \ }) #endif /* __ASSEMBLY__ */ From d7e0678c7627e68ea3810ddc6ac3df209670a6cf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 21 Mar 2023 15:07:45 -0400 Subject: [PATCH 047/805] CI: Move to clang-16 As this is now the stable release, move to using that now for our tests. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- .azure-pipelines.yml | 6 +++--- .gitlab-ci.yml | 4 ++-- tools/docker/Dockerfile | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 64da11e87f..642a16f304 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: windows-2019 ubuntu_vm: ubuntu-22.04 macos_vm: macOS-12 - ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230308-21Mar2023 + ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20230308-04Apr2023 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. @@ -254,7 +254,7 @@ stages: TEST_PY_BD: "sandbox" sandbox_clang: TEST_PY_BD: "sandbox" - OVERRIDE: "-O clang-14" + OVERRIDE: "-O clang-16" sandbox_nolto: TEST_PY_BD: "sandbox" BUILD_ENV: "NO_LTO=1" @@ -509,7 +509,7 @@ stages: OVERRIDE: "-a ASAN" sandbox_clang_asan: BUILDMAN: "sandbox" - OVERRIDE: "-O clang-14 -a ASAN" + OVERRIDE: "-O clang-16 -a ASAN" samsung_socfpga: BUILDMAN: "samsung socfpga" sun4i: diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2a423744c5..7509a7a224 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -10,7 +10,7 @@ default: # Grab our configured image. The source for this is found # in the u-boot tree at tools/docker/Dockerfile -image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230308-21Mar2023 +image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20230308-04Apr2023 # We run some tests in different order, to catch some failures quicker. stages: @@ -277,7 +277,7 @@ sandbox test.py: sandbox with clang test.py: variables: TEST_PY_BD: "sandbox" - OVERRIDE: "-O clang-14" + OVERRIDE: "-O clang-16" <<: *buildman_and_testpy_dfn sandbox without LTO test.py: diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 20c2b2a9d6..801bebf1b0 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -12,7 +12,7 @@ ENV DEBIAN_FRONTEND=noninteractive # Add LLVM repository RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/* RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add - -RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-14 main | tee /etc/apt/sources.list.d/llvm.list +RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-16 main | tee /etc/apt/sources.list.d/llvm.list # Manually install the kernel.org "Crosstool" based toolchains for gcc-12.2.0 RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ @@ -39,7 +39,7 @@ RUN apt-get update && apt-get install -y \ binutils-dev \ bison \ build-essential \ - clang-14 \ + clang-16 \ coreutils \ cpio \ cppcheck \ From d71a732af45e2d3acef92649f4f7986a83175cf4 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:03 +0100 Subject: [PATCH 048/805] android: boot: rename andr_img_hdr -> andr_boot_img_hdr_v0 Android introduced boot header version 3 or 4. The header structure change with version 3 and 4 to support the new updates such as: - Introducing Vendor boot image: with a vendor ramdisk - Bootconfig feature (v4) Change andr_img_hdr struct name to maintain support for version v0, v1 and v2 while introducing version 3 and 4. Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/image-android.c | 37 ++++++++----- boot/image-fdt.c | 2 +- cmd/abootimg.c | 4 +- drivers/fastboot/fb_mmc.c | 8 +-- include/android_image.h | 4 +- include/image.h | 107 ++++++++++++++++++++++++++++++++++---- 6 files changed, 129 insertions(+), 33 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index 2628db3741..b070974791 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -18,7 +18,7 @@ static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1]; -static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr) +static ulong android_image_get_kernel_addr(const struct andr_boot_img_hdr_v0 *hdr) { /* * All the Android tools that generate a boot.img use this @@ -59,7 +59,7 @@ static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr) * Return: Zero, os start address and length on success, * otherwise on failure. */ -int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, +int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int verify, ulong *os_data, ulong *os_len) { u32 kernel_addr = android_image_get_kernel_addr(hdr); @@ -122,12 +122,21 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, return 0; } -int android_image_check_header(const struct andr_img_hdr *hdr) +/** + * android_image_check_header() - Check the magic of boot image + * + * This checks the header of Android boot image and verifies the + * magic is "ANDROID!" + * + * @hdr: Pointer to boot image + * Return: 0 if the magic is correct, non-zero if there is a magic mismatch + */ +int android_image_check_header(const struct andr_boot_img_hdr_v0 *hdr) { return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE); } -ulong android_image_get_end(const struct andr_img_hdr *hdr) +ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr) { ulong end; @@ -150,12 +159,12 @@ ulong android_image_get_end(const struct andr_img_hdr *hdr) return end; } -ulong android_image_get_kload(const struct andr_img_hdr *hdr) +ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr) { return android_image_get_kernel_addr(hdr); } -ulong android_image_get_kcomp(const struct andr_img_hdr *hdr) +ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr) { const void *p = (void *)((uintptr_t)hdr + hdr->page_size); @@ -167,7 +176,7 @@ ulong android_image_get_kcomp(const struct andr_img_hdr *hdr) return image_decomp_type(p, sizeof(u32)); } -int android_image_get_ramdisk(const struct andr_img_hdr *hdr, +int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, ulong *rd_data, ulong *rd_len) { if (!hdr->ramdisk_size) { @@ -186,8 +195,8 @@ int android_image_get_ramdisk(const struct andr_img_hdr *hdr, return 0; } -int android_image_get_second(const struct andr_img_hdr *hdr, - ulong *second_data, ulong *second_len) +int android_image_get_second(const struct andr_boot_img_hdr_v0 *hdr, + ulong *second_data, ulong *second_len) { if (!hdr->second_size) { *second_data = *second_len = 0; @@ -226,7 +235,7 @@ int android_image_get_second(const struct andr_img_hdr *hdr, */ bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size) { - const struct andr_img_hdr *hdr; + const struct andr_boot_img_hdr_v0 *hdr; ulong dtbo_img_addr; bool ret = true; @@ -275,7 +284,7 @@ exit: */ static bool android_image_get_dtb_img_addr(ulong hdr_addr, ulong *addr) { - const struct andr_img_hdr *hdr; + const struct andr_boot_img_hdr_v0 *hdr; ulong dtb_img_addr; bool ret = true; @@ -328,7 +337,7 @@ exit: bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, u32 *size) { - const struct andr_img_hdr *hdr; + const struct andr_boot_img_hdr_v0 *hdr; bool res; ulong dtb_img_addr; /* address of DTB part in boot image */ u32 dtb_img_size; /* size of DTB payload in boot image */ @@ -393,7 +402,7 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, * returns: * no returned results */ -void android_print_contents(const struct andr_img_hdr *hdr) +void android_print_contents(const struct andr_boot_img_hdr_v0 *hdr) { const char * const p = IMAGE_INDENT_STRING; /* os_version = ver << 11 | lvl */ @@ -485,7 +494,7 @@ static bool android_image_print_dtb_info(const struct fdt_header *fdt, */ bool android_image_print_dtb_contents(ulong hdr_addr) { - const struct andr_img_hdr *hdr; + const struct andr_boot_img_hdr_v0 *hdr; bool res; ulong dtb_img_addr; /* address of DTB part in boot image */ u32 dtb_img_size; /* size of DTB payload in boot image */ diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 714d05d1a5..ba44ecf8ef 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -529,7 +529,7 @@ int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, } #ifdef CONFIG_ANDROID_BOOT_IMAGE } else if (genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) { - struct andr_img_hdr *hdr = buf; + struct andr_boot_img_hdr_v0 *hdr = buf; ulong fdt_data, fdt_len; u32 fdt_size, dtb_idx; /* diff --git a/cmd/abootimg.c b/cmd/abootimg.c index f48a9dcb02..0262adb1e5 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -18,7 +18,7 @@ static ulong _abootimg_addr = -1; static int abootimg_get_ver(int argc, char *const argv[]) { - const struct andr_img_hdr *hdr; + const struct andr_boot_img_hdr_v0 *hdr; int res = CMD_RET_SUCCESS; if (argc > 1) @@ -65,7 +65,7 @@ static int abootimg_get_recovery_dtbo(int argc, char *const argv[]) static int abootimg_get_dtb_load_addr(int argc, char *const argv[]) { - const struct andr_img_hdr *hdr; + const struct andr_boot_img_hdr_v0 *hdr; int res = CMD_RET_SUCCESS; if (argc > 1) diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index a06c590234..68677c55ce 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -287,7 +287,7 @@ static void fb_mmc_boot_ops(struct blk_desc *dev_desc, void *buffer, */ static lbaint_t fb_mmc_get_boot_header(struct blk_desc *dev_desc, struct disk_partition *info, - struct andr_img_hdr *hdr, + struct andr_boot_img_hdr_v0 *hdr, char *response) { ulong sector_size; /* boot partition sector size */ @@ -296,7 +296,7 @@ static lbaint_t fb_mmc_get_boot_header(struct blk_desc *dev_desc, /* Calculate boot image sectors count */ sector_size = info->blksz; - hdr_sectors = DIV_ROUND_UP(sizeof(struct andr_img_hdr), sector_size); + hdr_sectors = DIV_ROUND_UP(sizeof(struct andr_boot_img_hdr_v0), sector_size); if (hdr_sectors == 0) { pr_err("invalid number of boot sectors: 0\n"); fastboot_fail("invalid number of boot sectors: 0", response); @@ -338,7 +338,7 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc, char *response) { uintptr_t hdr_addr; /* boot image header address */ - struct andr_img_hdr *hdr; /* boot image header */ + struct andr_boot_img_hdr_v0 *hdr; /* boot image header */ lbaint_t hdr_sectors; /* boot image header sectors */ u8 *ramdisk_buffer; u32 ramdisk_sector_start; @@ -361,7 +361,7 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc, /* Put boot image header in fastboot buffer after downloaded zImage */ hdr_addr = (uintptr_t)download_buffer + ALIGN(download_bytes, PAGE_SIZE); - hdr = (struct andr_img_hdr *)hdr_addr; + hdr = (struct andr_boot_img_hdr_v0 *)hdr_addr; /* Read boot image header */ hdr_sectors = fb_mmc_get_boot_header(dev_desc, &info, hdr, response); diff --git a/include/android_image.h b/include/android_image.h index 54d25af068..2bdcab9122 100644 --- a/include/android_image.h +++ b/include/android_image.h @@ -20,9 +20,9 @@ #define ANDR_BOOT_ARGS_SIZE 512 #define ANDR_BOOT_EXTRA_ARGS_SIZE 1024 -/* The bootloader expects the structure of andr_img_hdr with header +/* The bootloader expects the structure of andr_boot_img_hdr_v0 with header * version 0 to be as follows: */ -struct andr_img_hdr { +struct andr_boot_img_hdr_v0 { /* Must be ANDR_BOOT_MAGIC. */ char magic[ANDR_BOOT_MAGIC_SIZE]; diff --git a/include/image.h b/include/image.h index 7717a4c13d..735484117d 100644 --- a/include/image.h +++ b/include/image.h @@ -1734,21 +1734,108 @@ int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo); struct cipher_algo *image_get_cipher_algo(const char *full_name); -struct andr_img_hdr; -int android_image_check_header(const struct andr_img_hdr *hdr); -int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, +struct andr_boot_img_hdr_v0; + +/** + * android_image_check_header() - Check the magic of boot image + * + * This checks the header of Android boot image and verifies the + * magic is "ANDROID!" + * + * @hdr: Pointer to image header + * Return: 0 if the magic is correct, non-zero if there is a magic mismatch + */ +int android_image_check_header(const struct andr_boot_img_hdr_v0 *hdr); + +/** + * android_image_get_kernel() - Processes kernel part of Android boot images + * + * This function returns the os image's start address and length. Also, + * it appends the kernel command line to the bootargs env variable. + * + * @hdr: Pointer to image header, which is at the start + * of the image. + * @verify: Checksum verification flag. Currently unimplemented. + * @os_data: Pointer to a ulong variable, will hold os data start + * address. + * @os_len: Pointer to a ulong variable, will hold os data length. + * Return: Zero, os start address and length on success, + * otherwise on failure. + */ +int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int verify, ulong *os_data, ulong *os_len); -int android_image_get_ramdisk(const struct andr_img_hdr *hdr, + +/** + * android_image_get_ramdisk() - Extracts the ramdisk load address and its size + * + * This extracts the load address of the ramdisk and its size + * + * @hdr: Pointer to image header + * @rd_data: Pointer to a ulong variable, will hold ramdisk address + * @rd_len: Pointer to a ulong variable, will hold ramdisk length + * Return: 0 if succeeded, -1 if ramdisk size is 0 + */ +int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, ulong *rd_data, ulong *rd_len); -int android_image_get_second(const struct andr_img_hdr *hdr, - ulong *second_data, ulong *second_len); + +/** + * android_image_get_second() - Extracts the secondary bootloader address + * and its size + * + * This extracts the address of the secondary bootloader and its size + * + * @hdr: Pointer to image header + * @second_data: Pointer to a ulong variable, will hold secondary bootloader address + * @second_len : Pointer to a ulong variable, will hold secondary bootloader length + * Return: 0 if succeeded, -1 if secondary bootloader size is 0 + */ +int android_image_get_second(const struct andr_boot_img_hdr_v0 *hdr, + ulong *second_data, ulong *second_len); bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size); bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, u32 *size); -ulong android_image_get_end(const struct andr_img_hdr *hdr); -ulong android_image_get_kload(const struct andr_img_hdr *hdr); -ulong android_image_get_kcomp(const struct andr_img_hdr *hdr); -void android_print_contents(const struct andr_img_hdr *hdr); + +/** + * android_image_get_end() - Get the end of Android boot image + * + * This returns the end address of Android boot image address + * + * @hdr: Pointer to image header + * Return: The end address of Android boot image + */ +ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr); + +/** + * android_image_get_kload() - Get the kernel load address + * + * This returns the kernel load address. The load address is extracted + * from the boot image header or the "kernel_addr_r" environment variable + * + * @hdr: Pointer to image header + * Return: The kernel load address + */ +ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr); + +/** + * android_image_get_kcomp() - Get kernel compression type + * + * This gets the kernel compression type from the boot image header + * + * @hdr: Pointer to image header + * Return: Kernel compression type + */ +ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr); + +/** + * android_print_contents() - Prints out the contents of the Android format image + * + * This formats a multi line Android image contents description. + * The routine prints out Android image properties + * + * @hdr: Pointer to the Android format image header + * Return: no returned results + */ +void android_print_contents(const struct andr_boot_img_hdr_v0 *hdr); bool android_image_print_dtb_contents(ulong hdr_addr); /** From 86b62947eb237daddc7014a6b3b5545d1848b02c Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:04 +0100 Subject: [PATCH 049/805] android: boot: support vendor boot image in abootimg Vendor boot image is introduced in boot image header version 3 and 4. Please check [1] for more details. To prepare for boot image v3/v4 support, allow the abootimg command to store the vendor_boot image address. Full support for this new format will be done in a future patch. Link:[1] https://source.android.com/docs/core/architecture/bootloader/partitions/vendor-boot-partitions Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- cmd/abootimg.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/cmd/abootimg.c b/cmd/abootimg.c index 0262adb1e5..026c03f91c 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -15,6 +15,7 @@ /* Please use abootimg_addr() macro to obtain the boot image address */ static ulong _abootimg_addr = -1; +static ulong _avendor_bootimg_addr = -1; static int abootimg_get_ver(int argc, char *const argv[]) { @@ -158,7 +159,7 @@ static int do_abootimg_addr(struct cmd_tbl *cmdtp, int flag, int argc, char *endp; ulong img_addr; - if (argc != 2) + if (argc < 2 || argc > 3) return CMD_RET_USAGE; img_addr = hextoul(argv[1], &endp); @@ -168,6 +169,17 @@ static int do_abootimg_addr(struct cmd_tbl *cmdtp, int flag, int argc, } _abootimg_addr = img_addr; + + if (argc == 3) { + img_addr = simple_strtoul(argv[2], &endp, 16); + if (*endp != '\0') { + printf("Error: Wrong vendor image address\n"); + return CMD_RET_FAILURE; + } + + _avendor_bootimg_addr = img_addr; + } + return CMD_RET_SUCCESS; } @@ -211,7 +223,7 @@ static int do_abootimg_dump(struct cmd_tbl *cmdtp, int flag, int argc, } static struct cmd_tbl cmd_abootimg_sub[] = { - U_BOOT_CMD_MKENT(addr, 2, 1, do_abootimg_addr, "", ""), + U_BOOT_CMD_MKENT(addr, 3, 1, do_abootimg_addr, "", ""), U_BOOT_CMD_MKENT(dump, 2, 1, do_abootimg_dump, "", ""), U_BOOT_CMD_MKENT(get, 5, 1, do_abootimg_get, "", ""), }; @@ -239,7 +251,7 @@ static int do_abootimg(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD( abootimg, CONFIG_SYS_MAXARGS, 0, do_abootimg, "manipulate Android Boot Image", - "addr \n" + "addr []>\n" " - set the address in RAM where boot image is located\n" " ($loadaddr is used by default)\n" "abootimg dump dtb\n" From 734cb47d6de16d2e3b52a03bce5daab40e5bb29d Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:05 +0100 Subject: [PATCH 050/805] android: boot: replace android_image_check_header With the new vendor boot image introduced in versions 3 and 4 of boot image header, the header check must be done for both boot image and vendor boot image. Thus, replace android_image_check_header() by is_android_boot_image_header() to only refer to boot image header check. Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/image-android.c | 17 ++++------------- boot/image-board.c | 2 +- cmd/abootimg.c | 4 ++-- drivers/fastboot/fb_mmc.c | 3 +-- include/image.h | 22 +++++++++++----------- 5 files changed, 19 insertions(+), 29 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index b070974791..ac7cb479c1 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -122,18 +122,9 @@ int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int verify, return 0; } -/** - * android_image_check_header() - Check the magic of boot image - * - * This checks the header of Android boot image and verifies the - * magic is "ANDROID!" - * - * @hdr: Pointer to boot image - * Return: 0 if the magic is correct, non-zero if there is a magic mismatch - */ -int android_image_check_header(const struct andr_boot_img_hdr_v0 *hdr) +bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr) { - return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE); + return !memcmp(ANDR_BOOT_MAGIC, hdr, ANDR_BOOT_MAGIC_SIZE); } ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr) @@ -240,7 +231,7 @@ bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size) bool ret = true; hdr = map_sysmem(hdr_addr, sizeof(*hdr)); - if (android_image_check_header(hdr)) { + if (!is_android_boot_image_header(hdr)) { printf("Error: Boot Image header is incorrect\n"); ret = false; goto exit; @@ -289,7 +280,7 @@ static bool android_image_get_dtb_img_addr(ulong hdr_addr, ulong *addr) bool ret = true; hdr = map_sysmem(hdr_addr, sizeof(*hdr)); - if (android_image_check_header(hdr)) { + if (!is_android_boot_image_header(hdr)) { printf("Error: Boot Image header is incorrect\n"); ret = false; goto exit; diff --git a/boot/image-board.c b/boot/image-board.c index 9bf70824cb..e086103258 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -284,7 +284,7 @@ int genimg_get_format(const void *img_addr) return IMAGE_FORMAT_FIT; } if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE) && - !android_image_check_header(img_addr)) + is_android_boot_image_header(img_addr)) return IMAGE_FORMAT_ANDROID; return IMAGE_FORMAT_INVALID; diff --git a/cmd/abootimg.c b/cmd/abootimg.c index 026c03f91c..b5cfb141ef 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -26,7 +26,7 @@ static int abootimg_get_ver(int argc, char *const argv[]) return CMD_RET_USAGE; hdr = map_sysmem(abootimg_addr(), sizeof(*hdr)); - if (android_image_check_header(hdr)) { + if (!is_android_boot_image_header(hdr)) { printf("Error: Boot Image header is incorrect\n"); res = CMD_RET_FAILURE; goto exit; @@ -73,7 +73,7 @@ static int abootimg_get_dtb_load_addr(int argc, char *const argv[]) return CMD_RET_USAGE; hdr = map_sysmem(abootimg_addr(), sizeof(*hdr)); - if (android_image_check_header(hdr)) { + if (!is_android_boot_image_header(hdr)) { printf("Error: Boot Image header is incorrect\n"); res = CMD_RET_FAILURE; goto exit; diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 68677c55ce..29c18cb82a 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -313,8 +313,7 @@ static lbaint_t fb_mmc_get_boot_header(struct blk_desc *dev_desc, } /* Check boot header magic string */ - res = android_image_check_header(hdr); - if (res != 0) { + if (!is_android_boot_image_header(hdr)) { pr_err("bad boot image magic\n"); fastboot_fail("boot partition not initialized", response); return 0; diff --git a/include/image.h b/include/image.h index 735484117d..6e67cf4817 100644 --- a/include/image.h +++ b/include/image.h @@ -1736,17 +1736,6 @@ struct cipher_algo *image_get_cipher_algo(const char *full_name); struct andr_boot_img_hdr_v0; -/** - * android_image_check_header() - Check the magic of boot image - * - * This checks the header of Android boot image and verifies the - * magic is "ANDROID!" - * - * @hdr: Pointer to image header - * Return: 0 if the magic is correct, non-zero if there is a magic mismatch - */ -int android_image_check_header(const struct andr_boot_img_hdr_v0 *hdr); - /** * android_image_get_kernel() - Processes kernel part of Android boot images * @@ -1838,6 +1827,17 @@ ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr); void android_print_contents(const struct andr_boot_img_hdr_v0 *hdr); bool android_image_print_dtb_contents(ulong hdr_addr); +/** + * is_android_boot_image_header() - Check the magic of boot image + * + * This checks the header of Android boot image and verifies the + * magic is "ANDROID!" + * + * @hdr: Pointer to boot image + * Return: non-zero if the magic is correct, zero otherwise + */ +bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr); + /** * board_fit_config_name_match() - Check for a matching board name * From fbb645e7d9bc1a0da05fff8421d398c8aa43a331 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:06 +0100 Subject: [PATCH 051/805] android: boot: add boot image header v3 and v4 structures Add support for v3/v4 boot image format by adding the following structures: - andr_boot_img_hdr_v3 : describes boot image header - andr_vnd_boot_img_hdr : describes vendor boot image header These definitions have been copied over from the AOSP documentation at [1] and [2] Boot arg sizes are taken from [3]: commit: 35fb6262bc3f (ANDROID: Support for vendor boot) This also adds documentation for boot image header v3/v4 structure that was imported from [4], file: include/bootimg/bootimg.h commit: 8d0922bfb932 (Adding GKI signature in boot.img v4) Link:[1] https://source.android.com/docs/core/architecture/bootloader/boot-image-header Link:[2] https://source.android.com/docs/core/architecture/bootloader/partitions/vendor-boot-partitions#vendor-boot-header Link:[3] https://android.googlesource.com/platform/external/u-boot Link:[4] https://android.googlesource.com/platform/system/tools/mkbootimg Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- include/android_image.h | 183 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 182 insertions(+), 1 deletion(-) diff --git a/include/android_image.h b/include/android_image.h index 2bdcab9122..f054363001 100644 --- a/include/android_image.h +++ b/include/android_image.h @@ -3,7 +3,7 @@ * This is from the Android Project, * Repository: https://android.googlesource.com/platform/system/tools/mkbootimg * File: include/bootimg/bootimg.h - * Commit: e55998a0f2b61b685d5eb4a486ca3a0c680b1a2f + * Commit: cce5b1923e3cd2fcb765b512610bdc5c42bc501d * * Copyright (C) 2007 The Android Open Source Project */ @@ -14,11 +14,58 @@ #include #include +#define ANDR_GKI_PAGE_SIZE 4096 #define ANDR_BOOT_MAGIC "ANDROID!" #define ANDR_BOOT_MAGIC_SIZE 8 #define ANDR_BOOT_NAME_SIZE 16 #define ANDR_BOOT_ARGS_SIZE 512 #define ANDR_BOOT_EXTRA_ARGS_SIZE 1024 +#define VENDOR_BOOT_MAGIC "VNDRBOOT" +#define ANDR_VENDOR_BOOT_MAGIC_SIZE 8 +#define ANDR_VENDOR_BOOT_ARGS_SIZE 2048 +#define ANDR_VENDOR_BOOT_NAME_SIZE 16 + +struct andr_boot_img_hdr_v3 { + u8 magic[ANDR_BOOT_MAGIC_SIZE]; + + u32 kernel_size; /* size in bytes */ + u32 ramdisk_size; /* size in bytes */ + + u32 os_version; + + u32 header_size; /* size of boot image header in bytes */ + u32 reserved[4]; + u32 header_version; /* offset remains constant for version check */ + + u8 cmdline[ANDR_BOOT_ARGS_SIZE + ANDR_BOOT_EXTRA_ARGS_SIZE]; + /* for boot image header v4 only */ + u32 signature_size; /* size in bytes */ +}; + +struct andr_vnd_boot_img_hdr { + u8 magic[ANDR_VENDOR_BOOT_MAGIC_SIZE]; + u32 header_version; + u32 page_size; /* flash page size we assume */ + + u32 kernel_addr; /* physical load addr */ + u32 ramdisk_addr; /* physical load addr */ + + u32 vendor_ramdisk_size; /* size in bytes */ + + u8 cmdline[ANDR_VENDOR_BOOT_ARGS_SIZE]; + + u32 tags_addr; /* physical addr for kernel tags */ + + u8 name[ANDR_VENDOR_BOOT_NAME_SIZE]; /* asciiz product name */ + u32 header_size; /* size of vendor boot image header in bytes */ + u32 dtb_size; /* size of dtb image */ + u64 dtb_addr; /* physical load address */ + /* for boot image header v4 only */ + u32 vendor_ramdisk_table_size; /* size in bytes for the vendor ramdisk table */ + u32 vendor_ramdisk_table_entry_num; /* number of entries in the vendor ramdisk table */ + u32 vendor_ramdisk_table_entry_size; /* size in bytes for a vendor ramdisk table entry */ + u32 bootconfig_size; /* size in bytes for the bootconfig section */ +}; /* The bootloader expects the structure of andr_boot_img_hdr_v0 with header * version 0 to be as follows: */ @@ -136,4 +183,138 @@ struct andr_boot_img_hdr_v0 { * else: jump to kernel_addr */ +/* When the boot image header has a version of 3, the structure of the boot + * image is as follows: + * + * +---------------------+ + * | boot header | 4096 bytes + * +---------------------+ + * | kernel | m pages + * +---------------------+ + * | ramdisk | n pages + * +---------------------+ + * + * m = (kernel_size + 4096 - 1) / 4096 + * n = (ramdisk_size + 4096 - 1) / 4096 + * + * Note that in version 3 of the boot image header, page size is fixed at 4096 bytes. + * + * The structure of the vendor boot image (introduced with version 3 and + * required to be present when a v3 boot image is used) is as follows: + * + * +---------------------+ + * | vendor boot header | o pages + * +---------------------+ + * | vendor ramdisk | p pages + * +---------------------+ + * | dtb | q pages + * +---------------------+ + * o = (2112 + page_size - 1) / page_size + * p = (vendor_ramdisk_size + page_size - 1) / page_size + * q = (dtb_size + page_size - 1) / page_size + * + * 0. all entities in the boot image are 4096-byte aligned in flash, all + * entities in the vendor boot image are page_size (determined by the vendor + * and specified in the vendor boot image header) aligned in flash + * 1. kernel, ramdisk, vendor ramdisk, and DTB are required (size != 0) + * 2. load the kernel and DTB at the specified physical address (kernel_addr, + * dtb_addr) + * 3. load the vendor ramdisk at ramdisk_addr + * 4. load the generic ramdisk immediately following the vendor ramdisk in + * memory + * 5. set up registers for kernel entry as required by your architecture + * 6. if the platform has a second stage bootloader jump to it (must be + * contained outside boot and vendor boot partitions), otherwise + * jump to kernel_addr + */ + +/* When the boot image header has a version of 4, the structure of the boot + * image is as follows: + * + * +---------------------+ + * | boot header | 4096 bytes + * +---------------------+ + * | kernel | m pages + * +---------------------+ + * | ramdisk | n pages + * +---------------------+ + * | boot signature | g pages + * +---------------------+ + * + * m = (kernel_size + 4096 - 1) / 4096 + * n = (ramdisk_size + 4096 - 1) / 4096 + * g = (signature_size + 4096 - 1) / 4096 + * + * Note that in version 4 of the boot image header, page size is fixed at 4096 + * bytes. + * + * The structure of the vendor boot image version 4, which is required to be + * present when a version 4 boot image is used, is as follows: + * + * +------------------------+ + * | vendor boot header | o pages + * +------------------------+ + * | vendor ramdisk section | p pages + * +------------------------+ + * | dtb | q pages + * +------------------------+ + * | vendor ramdisk table | r pages + * +------------------------+ + * | bootconfig | s pages + * +------------------------+ + * + * o = (2128 + page_size - 1) / page_size + * p = (vendor_ramdisk_size + page_size - 1) / page_size + * q = (dtb_size + page_size - 1) / page_size + * r = (vendor_ramdisk_table_size + page_size - 1) / page_size + * s = (vendor_bootconfig_size + page_size - 1) / page_size + * + * Note that in version 4 of the vendor boot image, multiple vendor ramdisks can + * be included in the vendor boot image. The bootloader can select a subset of + * ramdisks to load at runtime. To help the bootloader select the ramdisks, each + * ramdisk is tagged with a type tag and a set of hardware identifiers + * describing the board, soc or platform that this ramdisk is intended for. + * + * The vendor ramdisk section is consist of multiple ramdisk images concatenated + * one after another, and vendor_ramdisk_size is the size of the section, which + * is the total size of all the ramdisks included in the vendor boot image. + * + * The vendor ramdisk table holds the size, offset, type, name and hardware + * identifiers of each ramdisk. The type field denotes the type of its content. + * The vendor ramdisk names are unique. The hardware identifiers are specified + * in the board_id field in each table entry. The board_id field is consist of a + * vector of unsigned integer words, and the encoding scheme is defined by the + * hardware vendor. + * + * For the different type of ramdisks, there are: + * - VENDOR_RAMDISK_TYPE_NONE indicates the value is unspecified. + * - VENDOR_RAMDISK_TYPE_PLATFORM ramdisks contain platform specific bits, so + * the bootloader should always load these into memory. + * - VENDOR_RAMDISK_TYPE_RECOVERY ramdisks contain recovery resources, so + * the bootloader should load these when booting into recovery. + * - VENDOR_RAMDISK_TYPE_DLKM ramdisks contain dynamic loadable kernel + * modules. + * + * Version 4 of the vendor boot image also adds a bootconfig section to the end + * of the image. This section contains Boot Configuration parameters known at + * build time. The bootloader is responsible for placing this section directly + * after the generic ramdisk, followed by the bootconfig trailer, before + * entering the kernel. + * + * 0. all entities in the boot image are 4096-byte aligned in flash, all + * entities in the vendor boot image are page_size (determined by the vendor + * and specified in the vendor boot image header) aligned in flash + * 1. kernel, ramdisk, and DTB are required (size != 0) + * 2. load the kernel and DTB at the specified physical address (kernel_addr, + * dtb_addr) + * 3. load the vendor ramdisks at ramdisk_addr + * 4. load the generic ramdisk immediately following the vendor ramdisk in + * memory + * 5. load the bootconfig immediately following the generic ramdisk. Add + * additional bootconfig parameters followed by the bootconfig trailer. + * 6. set up registers for kernel entry as required by your architecture + * 7. if the platform has a second stage bootloader jump to it (must be + * contained outside boot and vendor boot partitions), otherwise + * jump to kernel_addr + */ #endif From f48efa0edb6f65b2c382209871df7c9b61a905e2 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:07 +0100 Subject: [PATCH 052/805] android: boot: kcomp: support andr_image_data andr_image_data structure is used as a global representation of boot image header structure. Introduce this new structure to support all boot header versions : v0,v1.v2.v3.v4 and to support v3 and v4 while maitaining support for v0,v1,v2. The need of using andr_image_data comes from the change of header structure in both version 3 and 4. Rework android_image_get_kcomp() to support this new struct. Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/image-android.c | 75 ++++++++++++++++++++++++++++++++++++++++- include/android_image.h | 27 +++++++++++++++ include/image.h | 12 +++++++ 3 files changed, 113 insertions(+), 1 deletion(-) diff --git a/boot/image-android.c b/boot/image-android.c index ac7cb479c1..ea05c1814f 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -18,6 +18,74 @@ static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1]; +static void android_boot_image_v0_v1_v2_parse_hdr(const struct andr_boot_img_hdr_v0 *hdr, + struct andr_image_data *data) +{ + ulong end; + + data->image_name = hdr->name; + data->kcmdline = hdr->cmdline; + data->kernel_addr = hdr->kernel_addr; + data->ramdisk_addr = hdr->ramdisk_addr; + data->header_version = hdr->header_version; + data->dtb_load_addr = hdr->dtb_addr; + + end = (ulong)hdr; + + /* + * The header takes a full page, the remaining components are aligned + * on page boundary + */ + + end += hdr->page_size; + + data->kernel_ptr = end; + data->kernel_size = hdr->kernel_size; + end += ALIGN(hdr->kernel_size, hdr->page_size); + + data->ramdisk_ptr = end; + data->ramdisk_size = hdr->ramdisk_size; + end += ALIGN(hdr->ramdisk_size, hdr->page_size); + + data->second_ptr = end; + data->second_size = hdr->second_size; + end += ALIGN(hdr->second_size, hdr->page_size); + + if (hdr->header_version >= 1) { + data->recovery_dtbo_ptr = end; + data->recovery_dtbo_size = hdr->recovery_dtbo_size; + end += ALIGN(hdr->recovery_dtbo_size, hdr->page_size); + } + + if (hdr->header_version >= 2) { + data->dtb_ptr = end; + data->dtb_size = hdr->dtb_size; + end += ALIGN(hdr->dtb_size, hdr->page_size); + } + + data->boot_img_total_size = end - (ulong)hdr; +} + +bool android_image_get_data(const void *boot_hdr, struct andr_image_data *data) +{ + if (!boot_hdr || !data) { + printf("boot_hdr or data params can't be NULL\n"); + return false; + } + + if (!is_android_boot_image_header(boot_hdr)) { + printf("Incorrect boot image header\n"); + return false; + } + + if (((struct andr_boot_img_hdr_v0 *)boot_hdr)->header_version > 2) + printf("Only boot image header version 2 and below are supported\n"); + else + android_boot_image_v0_v1_v2_parse_hdr(boot_hdr, data); + + return true; +} + static ulong android_image_get_kernel_addr(const struct andr_boot_img_hdr_v0 *hdr) { /* @@ -157,8 +225,13 @@ ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr) ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr) { - const void *p = (void *)((uintptr_t)hdr + hdr->page_size); + struct andr_image_data img_data; + const void *p; + if (!android_image_get_data(hdr, &img_data)) + return -EINVAL; + + p = (const void *)img_data.kernel_ptr; if (image_get_magic((struct legacy_img_hdr *)p) == IH_MAGIC) return image_get_comp((struct legacy_img_hdr *)p); else if (get_unaligned_le32(p) == LZ4F_MAGIC) diff --git a/include/android_image.h b/include/android_image.h index f054363001..fb3a9d9858 100644 --- a/include/android_image.h +++ b/include/android_image.h @@ -317,4 +317,31 @@ struct andr_boot_img_hdr_v0 { * contained outside boot and vendor boot partitions), otherwise * jump to kernel_addr */ + +/* Private struct */ +struct andr_image_data { + ulong kernel_ptr; /* kernel address */ + u32 kernel_size; /* size in bytes */ + u32 ramdisk_size; /* size in bytes */ + u32 boot_ramdisk_size; /* size in bytes */ + ulong second_ptr; /* secondary bootloader address */ + u32 second_size; /* secondary bootloader size */ + ulong dtb_ptr; /* address of dtb image */ + u32 dtb_size; /* size of dtb image */ + ulong recovery_dtbo_ptr; /* size in bytes for recovery DTBO/ACPIO image */ + u32 recovery_dtbo_size; /* offset to recovery dtbo/acpio in boot image */ + + const char *kcmdline; /* boot kernel cmdline */ + const char *kcmdline_extra; /* vendor-boot extra kernel cmdline */ + const char *image_name; /* asciiz product name */ + + u32 kernel_addr; /* physical load addr */ + ulong ramdisk_addr; /* physical load addr */ + ulong ramdisk_ptr; /* ramdisk address */ + ulong dtb_load_addr; /* physical load address for DTB image */ + ulong tags_addr; /* physical addr for kernel tags */ + u32 header_version; /* version of the boot image header */ + u32 boot_img_total_size; /* boot image size */ +}; + #endif diff --git a/include/image.h b/include/image.h index 6e67cf4817..4bf6c98ced 100644 --- a/include/image.h +++ b/include/image.h @@ -1733,7 +1733,19 @@ struct cipher_algo { int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo); struct cipher_algo *image_get_cipher_algo(const char *full_name); +struct andr_image_data; +/** + * android_image_get_data() - Parse Android boot image + * + * This is used to parse boot image header into andr_image_data + * generic structure. + * + * @boot_hdr: Pointer to boot image header + * @data: Pointer to generic boot format structure + * Return: true if succeeded, false otherwise + */ +bool android_image_get_data(const void *boot_hdr, struct andr_image_data *data); struct andr_boot_img_hdr_v0; /** From 607b07554e23ff58d245f16765d831253a4210de Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:08 +0100 Subject: [PATCH 053/805] android: boot: move to andr_image_data structure Move from andr_boot_img_hdr_v0 to andr_image_data structure to prepare for boot image header version 3 and 4. Signed-off-by: Safae Ouajih Tested-by: Mattijs Korpershoek --- boot/image-android.c | 121 +++++++++++++++++++++++-------------------- cmd/abootimg.c | 33 ++++++------ 2 files changed, 82 insertions(+), 72 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index ea05c1814f..15a735e230 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -86,7 +86,7 @@ bool android_image_get_data(const void *boot_hdr, struct andr_image_data *data) return true; } -static ulong android_image_get_kernel_addr(const struct andr_boot_img_hdr_v0 *hdr) +static ulong android_image_get_kernel_addr(struct andr_image_data *img_data) { /* * All the Android tools that generate a boot.img use this @@ -99,17 +99,17 @@ static ulong android_image_get_kernel_addr(const struct andr_boot_img_hdr_v0 *hd * * Otherwise, we will return the actual value set by the user. */ - if (hdr->kernel_addr == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR) - return (ulong)hdr + hdr->page_size; + if (img_data->kernel_addr == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR) + return img_data->kernel_ptr; /* * abootimg creates images where all load addresses are 0 * and we need to fix them. */ - if (hdr->kernel_addr == 0 && hdr->ramdisk_addr == 0) + if (img_data->kernel_addr == 0 && img_data->ramdisk_addr == 0) return env_get_ulong("kernel_addr_r", 16, 0); - return hdr->kernel_addr; + return img_data->kernel_addr; } /** @@ -130,27 +130,33 @@ static ulong android_image_get_kernel_addr(const struct andr_boot_img_hdr_v0 *hd int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int verify, ulong *os_data, ulong *os_len) { - u32 kernel_addr = android_image_get_kernel_addr(hdr); - const struct legacy_img_hdr *ihdr = (const struct legacy_img_hdr *) - ((uintptr_t)hdr + hdr->page_size); + struct andr_image_data img_data = {0}; + u32 kernel_addr; + const struct legacy_img_hdr *ihdr; + + if (!android_image_get_data(hdr, &img_data)) + return -EINVAL; + + kernel_addr = android_image_get_kernel_addr(&img_data); + ihdr = (const struct legacy_img_hdr *)img_data.kernel_ptr; /* * Not all Android tools use the id field for signing the image with * sha1 (or anything) so we don't check it. It is not obvious that the * string is null terminated so we take care of this. */ - strncpy(andr_tmp_str, hdr->name, ANDR_BOOT_NAME_SIZE); + strlcpy(andr_tmp_str, img_data.image_name, ANDR_BOOT_NAME_SIZE); andr_tmp_str[ANDR_BOOT_NAME_SIZE] = '\0'; if (strlen(andr_tmp_str)) printf("Android's image name: %s\n", andr_tmp_str); printf("Kernel load addr 0x%08x size %u KiB\n", - kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024)); + kernel_addr, DIV_ROUND_UP(img_data.kernel_size, 1024)); int len = 0; - if (*hdr->cmdline) { - printf("Kernel command line: %s\n", hdr->cmdline); - len += strlen(hdr->cmdline); + if (*img_data.kcmdline) { + printf("Kernel command line: %s\n", img_data.kcmdline); + len += strlen(img_data.kcmdline); } char *bootargs = env_get("bootargs"); @@ -168,8 +174,9 @@ int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int verify, strcpy(newbootargs, bootargs); strcat(newbootargs, " "); } - if (*hdr->cmdline) - strcat(newbootargs, hdr->cmdline); + + if (*img_data.kcmdline) + strcat(newbootargs, img_data.kcmdline); env_set("bootargs", newbootargs); @@ -177,15 +184,14 @@ int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int verify, if (image_get_magic(ihdr) == IH_MAGIC) { *os_data = image_get_data(ihdr); } else { - *os_data = (ulong)hdr; - *os_data += hdr->page_size; + *os_data = img_data.kernel_ptr; } } if (os_len) { if (image_get_magic(ihdr) == IH_MAGIC) *os_len = image_get_data_size(ihdr); else - *os_len = hdr->kernel_size; + *os_len = img_data.kernel_size; } return 0; } @@ -197,30 +203,25 @@ bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr) ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr) { - ulong end; + struct andr_image_data img_data; - /* - * The header takes a full page, the remaining components are aligned - * on page boundary - */ - end = (ulong)hdr; - end += hdr->page_size; - end += ALIGN(hdr->kernel_size, hdr->page_size); - end += ALIGN(hdr->ramdisk_size, hdr->page_size); - end += ALIGN(hdr->second_size, hdr->page_size); + if (!android_image_get_data(hdr, &img_data)) + return -EINVAL; - if (hdr->header_version >= 1) - end += ALIGN(hdr->recovery_dtbo_size, hdr->page_size); + if (img_data.header_version > 2) + return 0; - if (hdr->header_version >= 2) - end += ALIGN(hdr->dtb_size, hdr->page_size); - - return end; + return img_data.boot_img_total_size; } ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr) { - return android_image_get_kernel_addr(hdr); + struct andr_image_data img_data; + + if (!android_image_get_data(hdr, &img_data)) + return -EINVAL; + + return android_image_get_kernel_addr(&img_data); } ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr) @@ -243,38 +244,43 @@ ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr) int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, ulong *rd_data, ulong *rd_len) { - if (!hdr->ramdisk_size) { + struct andr_image_data img_data = {0}; + + if (!android_image_get_data(hdr, &img_data)) + return -EINVAL; + + if (!img_data.ramdisk_size) { *rd_data = *rd_len = 0; return -1; } - printf("RAM disk load addr 0x%08x size %u KiB\n", - hdr->ramdisk_addr, DIV_ROUND_UP(hdr->ramdisk_size, 1024)); + printf("RAM disk load addr 0x%08lx size %u KiB\n", + img_data.ramdisk_ptr, DIV_ROUND_UP(img_data.ramdisk_size, 1024)); - *rd_data = (unsigned long)hdr; - *rd_data += hdr->page_size; - *rd_data += ALIGN(hdr->kernel_size, hdr->page_size); + *rd_data = img_data.ramdisk_ptr; - *rd_len = hdr->ramdisk_size; + *rd_len = img_data.ramdisk_size; return 0; } int android_image_get_second(const struct andr_boot_img_hdr_v0 *hdr, ulong *second_data, ulong *second_len) { - if (!hdr->second_size) { + struct andr_image_data img_data; + + if (!android_image_get_data(hdr, &img_data)) + return -EINVAL; + + if (!img_data.second_size) { *second_data = *second_len = 0; return -1; } - *second_data = (unsigned long)hdr; - *second_data += hdr->page_size; - *second_data += ALIGN(hdr->kernel_size, hdr->page_size); - *second_data += ALIGN(hdr->ramdisk_size, hdr->page_size); + *second_data = img_data.second_ptr; printf("second address is 0x%lx\n",*second_data); - *second_len = hdr->second_size; + *second_len = img_data.second_size; return 0; } @@ -401,17 +407,22 @@ exit: bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, u32 *size) { + struct andr_image_data img_data; const struct andr_boot_img_hdr_v0 *hdr; - bool res; + + hdr = map_sysmem(hdr_addr, sizeof(*hdr)); + if (!android_image_get_data(hdr, &img_data)) { + unmap_sysmem(hdr); + return false; + } + unmap_sysmem(hdr); + ulong dtb_img_addr; /* address of DTB part in boot image */ u32 dtb_img_size; /* size of DTB payload in boot image */ ulong dtb_addr; /* address of DTB blob with specified index */ u32 i; /* index iterator */ - res = android_image_get_dtb_img_addr(hdr_addr, &dtb_img_addr); - if (!res) - return false; - + android_image_get_dtb_img_addr(hdr_addr, &dtb_img_addr); /* Check if DTB area of boot image is in DTBO format */ if (android_dt_check_header(dtb_img_addr)) { return android_dt_get_fdt_by_index(dtb_img_addr, index, addr, @@ -419,9 +430,7 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, } /* Find out the address of DTB with specified index in concat blobs */ - hdr = map_sysmem(hdr_addr, sizeof(*hdr)); - dtb_img_size = hdr->dtb_size; - unmap_sysmem(hdr); + dtb_img_size = img_data.dtb_size; i = 0; dtb_addr = dtb_img_addr; while (dtb_addr < dtb_img_addr + dtb_img_size) { diff --git a/cmd/abootimg.c b/cmd/abootimg.c index b5cfb141ef..f04a7c7c8e 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -66,33 +66,34 @@ static int abootimg_get_recovery_dtbo(int argc, char *const argv[]) static int abootimg_get_dtb_load_addr(int argc, char *const argv[]) { - const struct andr_boot_img_hdr_v0 *hdr; - int res = CMD_RET_SUCCESS; - if (argc > 1) return CMD_RET_USAGE; + struct andr_image_data img_data = {0}; + const struct andr_boot_img_hdr_v0 *hdr; hdr = map_sysmem(abootimg_addr(), sizeof(*hdr)); - if (!is_android_boot_image_header(hdr)) { - printf("Error: Boot Image header is incorrect\n"); - res = CMD_RET_FAILURE; - goto exit; + if (!android_image_get_data(hdr, &img_data)) { + unmap_sysmem(hdr); + return CMD_RET_FAILURE; + } + unmap_sysmem(hdr); + + if (img_data.header_version < 2) { + printf("Error: header_version must be >= 2 for this\n"); + return CMD_RET_FAILURE; } - if (hdr->header_version < 2) { - printf("Error: header_version must be >= 2 for this\n"); - res = CMD_RET_FAILURE; - goto exit; + if (!img_data.dtb_load_addr) { + printf("Error: failed to read dtb_load_addr\n"); + return CMD_RET_FAILURE; } if (argc == 0) - printf("%lx\n", (ulong)hdr->dtb_addr); + printf("%lx\n", (ulong)img_data.dtb_load_addr); else - env_set_hex(argv[0], (ulong)hdr->dtb_addr); + env_set_hex(argv[0], (ulong)img_data.dtb_load_addr); -exit: - unmap_sysmem(hdr); - return res; + return CMD_RET_SUCCESS; } static int abootimg_get_dtb_by_index(int argc, char *const argv[]) From bb5d692732ca02511f2f491af1e680c87373fd35 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:09 +0100 Subject: [PATCH 054/805] android: boot: content print is not supported for v3, v4 header version Content print is not supported for version 3 and 4 of boot image header. Thus, only print that content when v2 is used. Update android_print_contents() to print an error message when trying to print boot image header version 3 or 4 content. Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/image-android.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/boot/image-android.c b/boot/image-android.c index 15a735e230..31a5d30162 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -477,6 +477,10 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, */ void android_print_contents(const struct andr_boot_img_hdr_v0 *hdr) { + if (hdr->header_version >= 3) { + printf("Content print is not supported for boot image header version > 2"); + return; + } const char * const p = IMAGE_INDENT_STRING; /* os_version = ver << 11 | lvl */ u32 os_ver = hdr->os_version >> 11; @@ -509,7 +513,7 @@ void android_print_contents(const struct andr_boot_img_hdr_v0 *hdr) hdr->header_size); } - if (hdr->header_version >= 2) { + if (hdr->header_version == 2) { printf("%sdtb size: %x\n", p, hdr->dtb_size); printf("%sdtb addr: %llx\n", p, hdr->dtb_addr); } From 447240e27b892ab2ccc1ada03a260abbb562484e Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:10 +0100 Subject: [PATCH 055/805] android: boot: boot image header v3, v4 do not support recovery DTBO android_image_get_dtbo() is used to get recovery DTBO via abootimg cmd. This is not supported in boot image header v3 and v4. Thus, print an error message when v1,v2 header version are not used. Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/image-android.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index 31a5d30162..748fd212ae 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -316,8 +316,8 @@ bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size) goto exit; } - if (hdr->header_version < 1) { - printf("Error: header_version must be >= 1 to get dtbo\n"); + if (hdr->header_version != 1 && hdr->header_version != 2) { + printf("Error: header version must be >= 1 and <= 2 to get dtbo\n"); ret = false; goto exit; } From e058176be32b09ca4f787442fd99d29e44079519 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:11 +0100 Subject: [PATCH 056/805] android: boot: add vendor boot image to prepare for v3, v4 support Introduce vendor boot image for version 3 and 4 of boot image header. The vendor boot image will hold extra information about kernel, dtb and ramdisk. This is done to prepare for boot image version 3 and 4 support. Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/bootm.c | 8 +++---- boot/image-android.c | 54 ++++++++++++++++++++++++++++---------------- boot/image-board.c | 3 +-- boot/image-fdt.c | 3 ++- cmd/abootimg.c | 4 ++-- include/image.h | 48 ++++++++++++++++++++++++++++++--------- 6 files changed, 81 insertions(+), 39 deletions(-) diff --git a/boot/bootm.c b/boot/bootm.c index 2eec60ec7b..28a8fc3261 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -182,11 +182,11 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc, #ifdef CONFIG_ANDROID_BOOT_IMAGE case IMAGE_FORMAT_ANDROID: images.os.type = IH_TYPE_KERNEL; - images.os.comp = android_image_get_kcomp(os_hdr); + images.os.comp = android_image_get_kcomp(os_hdr, NULL); images.os.os = IH_OS_LINUX; - images.os.end = android_image_get_end(os_hdr); - images.os.load = android_image_get_kload(os_hdr); + images.os.end = android_image_get_end(os_hdr, NULL); + images.os.load = android_image_get_kload(os_hdr, NULL); images.ep = images.os.load; ep_found = true; break; @@ -965,7 +965,7 @@ static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc, #ifdef CONFIG_ANDROID_BOOT_IMAGE case IMAGE_FORMAT_ANDROID: printf("## Booting Android Image at 0x%08lx ...\n", img_addr); - if (android_image_get_kernel(buf, images->verify, + if (android_image_get_kernel(buf, NULL, images->verify, os_data, os_len)) return NULL; break; diff --git a/boot/image-android.c b/boot/image-android.c index 748fd212ae..f16eebff49 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -66,7 +66,8 @@ static void android_boot_image_v0_v1_v2_parse_hdr(const struct andr_boot_img_hdr data->boot_img_total_size = end - (ulong)hdr; } -bool android_image_get_data(const void *boot_hdr, struct andr_image_data *data) +bool android_image_get_data(const void *boot_hdr, const void *vendor_boot_hdr, + struct andr_image_data *data) { if (!boot_hdr || !data) { printf("boot_hdr or data params can't be NULL\n"); @@ -114,8 +115,10 @@ static ulong android_image_get_kernel_addr(struct andr_image_data *img_data) /** * android_image_get_kernel() - processes kernel part of Android boot images - * @hdr: Pointer to image header, which is at the start + * @hdr: Pointer to boot image header, which is at the start * of the image. + * @vendor_boot_img: Pointer to vendor boot image header, which is at the + * start of the image. * @verify: Checksum verification flag. Currently unimplemented. * @os_data: Pointer to a ulong variable, will hold os data start * address. @@ -127,14 +130,15 @@ static ulong android_image_get_kernel_addr(struct andr_image_data *img_data) * Return: Zero, os start address and length on success, * otherwise on failure. */ -int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int verify, +int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, + const void *vendor_boot_img, int verify, ulong *os_data, ulong *os_len) { struct andr_image_data img_data = {0}; u32 kernel_addr; const struct legacy_img_hdr *ihdr; - if (!android_image_get_data(hdr, &img_data)) + if (!android_image_get_data(hdr, vendor_boot_img, &img_data)) return -EINVAL; kernel_addr = android_image_get_kernel_addr(&img_data); @@ -201,11 +205,12 @@ bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr) return !memcmp(ANDR_BOOT_MAGIC, hdr, ANDR_BOOT_MAGIC_SIZE); } -ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr) +ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr, + const void *vendor_boot_img) { struct andr_image_data img_data; - if (!android_image_get_data(hdr, &img_data)) + if (!android_image_get_data(hdr, vendor_boot_img, &img_data)) return -EINVAL; if (img_data.header_version > 2) @@ -214,22 +219,24 @@ ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr) return img_data.boot_img_total_size; } -ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr) +ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr, + const void *vendor_boot_img) { struct andr_image_data img_data; - if (!android_image_get_data(hdr, &img_data)) + if (!android_image_get_data(hdr, vendor_boot_img, &img_data)) return -EINVAL; return android_image_get_kernel_addr(&img_data); } -ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr) +ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr, + const void *vendor_boot_img) { struct andr_image_data img_data; const void *p; - if (!android_image_get_data(hdr, &img_data)) + if (!android_image_get_data(hdr, vendor_boot_img, &img_data)) return -EINVAL; p = (const void *)img_data.kernel_ptr; @@ -242,11 +249,11 @@ ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr) } int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, - ulong *rd_data, ulong *rd_len) + const void *vendor_boot_img, ulong *rd_data, ulong *rd_len) { struct andr_image_data img_data = {0}; - if (!android_image_get_data(hdr, &img_data)) + if (!android_image_get_data(hdr, vendor_boot_img, &img_data)) return -EINVAL; if (!img_data.ramdisk_size) { @@ -268,7 +275,7 @@ int android_image_get_second(const struct andr_boot_img_hdr_v0 *hdr, { struct andr_image_data img_data; - if (!android_image_get_data(hdr, &img_data)) + if (!android_image_get_data(hdr, NULL, &img_data)) return -EINVAL; if (!img_data.second_size) { @@ -348,11 +355,12 @@ exit: /** * android_image_get_dtb_img_addr() - Get the address of DTB area in boot image. * @hdr_addr: Boot image header address + * @vhdr_addr: Vendor Boot image header address * @addr: Will contain the address of DTB area in boot image * * Return: true on success or false on fail. */ -static bool android_image_get_dtb_img_addr(ulong hdr_addr, ulong *addr) +static bool android_image_get_dtb_img_addr(ulong hdr_addr, ulong vhdr_addr, ulong *addr) { const struct andr_boot_img_hdr_v0 *hdr; ulong dtb_img_addr; @@ -395,6 +403,7 @@ exit: /** * android_image_get_dtb_by_index() - Get address and size of blob in DTB area. * @hdr_addr: Boot image header address + * @vendor_boot_img: Pointer to vendor boot image header, which is at the start of the image. * @index: Index of desired DTB in DTB area (starting from 0) * @addr: If not NULL, will contain address to specified DTB * @size: If not NULL, will contain size of specified DTB @@ -404,17 +413,24 @@ exit: * * Return: true on success or false on error. */ -bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, - u32 *size) +bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img, + u32 index, ulong *addr, u32 *size) { struct andr_image_data img_data; const struct andr_boot_img_hdr_v0 *hdr; + const struct andr_vnd_boot_img_hdr *vhdr; hdr = map_sysmem(hdr_addr, sizeof(*hdr)); - if (!android_image_get_data(hdr, &img_data)) { + if (vendor_boot_img != -1) + vhdr = map_sysmem(vendor_boot_img, sizeof(*vhdr)); + if (!android_image_get_data(hdr, vhdr, &img_data)) { + if (vendor_boot_img != -1) + unmap_sysmem(vhdr); unmap_sysmem(hdr); return false; } + if (vendor_boot_img != -1) + unmap_sysmem(vhdr); unmap_sysmem(hdr); ulong dtb_img_addr; /* address of DTB part in boot image */ @@ -422,7 +438,7 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, ulong dtb_addr; /* address of DTB blob with specified index */ u32 i; /* index iterator */ - android_image_get_dtb_img_addr(hdr_addr, &dtb_img_addr); + android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img, &dtb_img_addr); /* Check if DTB area of boot image is in DTBO format */ if (android_dt_check_header(dtb_img_addr)) { return android_dt_get_fdt_by_index(dtb_img_addr, index, addr, @@ -578,7 +594,7 @@ bool android_image_print_dtb_contents(ulong hdr_addr) ulong dtb_addr; /* address of DTB blob with specified index */ u32 i; /* index iterator */ - res = android_image_get_dtb_img_addr(hdr_addr, &dtb_img_addr); + res = android_image_get_dtb_img_addr(hdr_addr, 0, &dtb_img_addr); if (!res) return false; diff --git a/boot/image-board.c b/boot/image-board.c index e086103258..2d73c76a4a 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -428,8 +428,7 @@ static int select_ramdisk(struct bootm_headers *images, const char *select, u8 a if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) { void *ptr = map_sysmem(images->os.start, 0); int ret; - - ret = android_image_get_ramdisk(ptr, rd_datap, rd_lenp); + ret = android_image_get_ramdisk(ptr, NULL, rd_datap, rd_lenp); unmap_sysmem(ptr); if (ret) return ret; diff --git a/boot/image-fdt.c b/boot/image-fdt.c index ba44ecf8ef..d639f37896 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -536,7 +536,8 @@ int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, * Firstly check if this android boot image has dtb field. */ dtb_idx = (u32)env_get_ulong("adtb_idx", 10, 0); - if (android_image_get_dtb_by_index((ulong)hdr, dtb_idx, &fdt_addr, &fdt_size)) { + if (android_image_get_dtb_by_index((ulong)hdr, 0, + dtb_idx, &fdt_addr, &fdt_size)) { fdt_blob = (char *)map_sysmem(fdt_addr, 0); if (fdt_check_header(fdt_blob)) goto no_fdt; diff --git a/cmd/abootimg.c b/cmd/abootimg.c index f04a7c7c8e..4d6cf0fa3e 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -72,7 +72,7 @@ static int abootimg_get_dtb_load_addr(int argc, char *const argv[]) const struct andr_boot_img_hdr_v0 *hdr; hdr = map_sysmem(abootimg_addr(), sizeof(*hdr)); - if (!android_image_get_data(hdr, &img_data)) { + if (!android_image_get_data(hdr, NULL, &img_data)) { unmap_sysmem(hdr); return CMD_RET_FAILURE; } @@ -119,7 +119,7 @@ static int abootimg_get_dtb_by_index(int argc, char *const argv[]) return CMD_RET_FAILURE; } - if (!android_image_get_dtb_by_index(abootimg_addr(), num, + if (!android_image_get_dtb_by_index(abootimg_addr(), 0, num, &addr, &size)) { return CMD_RET_FAILURE; } diff --git a/include/image.h b/include/image.h index 4bf6c98ced..f84c03f08f 100644 --- a/include/image.h +++ b/include/image.h @@ -1736,16 +1736,19 @@ struct cipher_algo *image_get_cipher_algo(const char *full_name); struct andr_image_data; /** - * android_image_get_data() - Parse Android boot image + * android_image_get_data() - Parse Android boot images * - * This is used to parse boot image header into andr_image_data - * generic structure. + * This is used to parse boot and vendor-boot header into + * andr_image_data generic structure. * * @boot_hdr: Pointer to boot image header + * @vendor_boot_hdr: Pointer to vendor boot image header * @data: Pointer to generic boot format structure * Return: true if succeeded, false otherwise */ -bool android_image_get_data(const void *boot_hdr, struct andr_image_data *data); +bool android_image_get_data(const void *boot_hdr, const void *vendor_boot_hdr, + struct andr_image_data *data); + struct andr_boot_img_hdr_v0; /** @@ -1756,6 +1759,7 @@ struct andr_boot_img_hdr_v0; * * @hdr: Pointer to image header, which is at the start * of the image. + * @vendor_boot_img : Pointer to vendor boot image header * @verify: Checksum verification flag. Currently unimplemented. * @os_data: Pointer to a ulong variable, will hold os data start * address. @@ -1763,7 +1767,8 @@ struct andr_boot_img_hdr_v0; * Return: Zero, os start address and length on success, * otherwise on failure. */ -int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int verify, +int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, + const void *vendor_boot_img, int verify, ulong *os_data, ulong *os_len); /** @@ -1772,12 +1777,13 @@ int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, int verify, * This extracts the load address of the ramdisk and its size * * @hdr: Pointer to image header + * @vendor_boot_img : Pointer to vendor boot image header * @rd_data: Pointer to a ulong variable, will hold ramdisk address * @rd_len: Pointer to a ulong variable, will hold ramdisk length * Return: 0 if succeeded, -1 if ramdisk size is 0 */ int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, - ulong *rd_data, ulong *rd_len); + const void *vendor_boot_img, ulong *rd_data, ulong *rd_len); /** * android_image_get_second() - Extracts the secondary bootloader address @@ -1793,8 +1799,22 @@ int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, int android_image_get_second(const struct andr_boot_img_hdr_v0 *hdr, ulong *second_data, ulong *second_len); bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size); -bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, - u32 *size); + +/** + * android_image_get_dtb_by_index() - Get address and size of blob in DTB area. + * @hdr_addr: Boot image header address + * @vendor_boot_img: Pointer to vendor boot image header, which is at the start of the image. + * @index: Index of desired DTB in DTB area (starting from 0) + * @addr: If not NULL, will contain address to specified DTB + * @size: If not NULL, will contain size of specified DTB + * + * Get the address and size of DTB blob by its index in DTB area of Android + * Boot Image in RAM. + * + * Return: true on success or false on error. + */ +bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img, + u32 index, ulong *addr, u32 *size); /** * android_image_get_end() - Get the end of Android boot image @@ -1802,9 +1822,11 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr, * This returns the end address of Android boot image address * * @hdr: Pointer to image header + * @vendor_boot_img : Pointer to vendor boot image header * Return: The end address of Android boot image */ -ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr); +ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr, + const void *vendor_boot_img); /** * android_image_get_kload() - Get the kernel load address @@ -1813,9 +1835,11 @@ ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr); * from the boot image header or the "kernel_addr_r" environment variable * * @hdr: Pointer to image header + * @vendor_boot_img : Pointer to vendor boot image header * Return: The kernel load address */ -ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr); +ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr, + const void *vendor_boot_img); /** * android_image_get_kcomp() - Get kernel compression type @@ -1823,9 +1847,11 @@ ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr); * This gets the kernel compression type from the boot image header * * @hdr: Pointer to image header + * @vendor_boot_img : Pointer to vendor boot image header * Return: Kernel compression type */ -ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr); +ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr, + const void *vendor_boot_img); /** * android_print_contents() - Prints out the contents of the Android format image From 1115027d2f75ade805f0d4d44a6a2c21e74ea6b2 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:12 +0100 Subject: [PATCH 057/805] android: boot: update android_image_get_data to support v3, v4 Since boot image header version 3 and 4 introduced vendor boot image, use the following functions to fill the generic android structure : andr_image_data: - android_boot_image_v3_v4_parse_hdr() - android_vendor_boot_image_v3_v4_parse_hdr() Update android_image_get_data() to support v3 and v4 Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/image-android.c | 80 +++++++++++++++++++++++++++++++++++++++-- include/android_image.h | 3 ++ include/image.h | 11 ++++++ 3 files changed, 91 insertions(+), 3 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index f16eebff49..712d437766 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -18,6 +18,65 @@ static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1]; +static void android_boot_image_v3_v4_parse_hdr(const struct andr_boot_img_hdr_v3 *hdr, + struct andr_image_data *data) +{ + ulong end; + + data->kcmdline = hdr->cmdline; + data->header_version = hdr->header_version; + + /* + * The header takes a full page, the remaining components are aligned + * on page boundary. + */ + end = (ulong)hdr; + end += ANDR_GKI_PAGE_SIZE; + data->kernel_ptr = end; + data->kernel_size = hdr->kernel_size; + end += ALIGN(hdr->kernel_size, ANDR_GKI_PAGE_SIZE); + data->ramdisk_size = hdr->ramdisk_size; + data->boot_ramdisk_size = hdr->ramdisk_size; + end += ALIGN(hdr->ramdisk_size, ANDR_GKI_PAGE_SIZE); + + if (hdr->header_version > 3) + end += ALIGN(hdr->signature_size, ANDR_GKI_PAGE_SIZE); + + data->boot_img_total_size = end - (ulong)hdr; +} + +static void android_vendor_boot_image_v3_v4_parse_hdr(const struct andr_vnd_boot_img_hdr + *hdr, struct andr_image_data *data) +{ + ulong end; + + /* + * The header takes a full page, the remaining components are aligned + * on page boundary. + */ + data->tags_addr = hdr->tags_addr; + data->image_name = hdr->name; + data->kernel_addr = hdr->kernel_addr; + data->ramdisk_addr = hdr->ramdisk_addr; + data->dtb_load_addr = hdr->dtb_addr; + end = (ulong)hdr; + end += hdr->page_size; + if (hdr->vendor_ramdisk_size) { + data->vendor_ramdisk_ptr = end; + data->vendor_ramdisk_size = hdr->vendor_ramdisk_size; + data->ramdisk_size += hdr->vendor_ramdisk_size; + end += ALIGN(hdr->vendor_ramdisk_size, hdr->page_size); + } + + data->dtb_ptr = end; + data->dtb_size = hdr->dtb_size; + + end += ALIGN(hdr->dtb_size, hdr->page_size); + end += ALIGN(hdr->vendor_ramdisk_table_size, hdr->page_size); + end += ALIGN(hdr->bootconfig_size, hdr->page_size); + data->vendor_boot_img_total_size = end - (ulong)hdr; +} + static void android_boot_image_v0_v1_v2_parse_hdr(const struct andr_boot_img_hdr_v0 *hdr, struct andr_image_data *data) { @@ -79,10 +138,20 @@ bool android_image_get_data(const void *boot_hdr, const void *vendor_boot_hdr, return false; } - if (((struct andr_boot_img_hdr_v0 *)boot_hdr)->header_version > 2) - printf("Only boot image header version 2 and below are supported\n"); - else + if (((struct andr_boot_img_hdr_v0 *)boot_hdr)->header_version > 2) { + if (!vendor_boot_hdr) { + printf("For boot header v3+ vendor boot image has to be provided\n"); + return false; + } + if (!is_android_vendor_boot_image_header(vendor_boot_hdr)) { + printf("Incorrect vendor boot image header\n"); + return false; + } + android_boot_image_v3_v4_parse_hdr(boot_hdr, data); + android_vendor_boot_image_v3_v4_parse_hdr(vendor_boot_hdr, data); + } else { android_boot_image_v0_v1_v2_parse_hdr(boot_hdr, data); + } return true; } @@ -200,6 +269,11 @@ int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, return 0; } +bool is_android_vendor_boot_image_header(const void *vendor_boot_img) +{ + return !memcmp(VENDOR_BOOT_MAGIC, vendor_boot_img, ANDR_VENDOR_BOOT_MAGIC_SIZE); +} + bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr) { return !memcmp(ANDR_BOOT_MAGIC, hdr, ANDR_BOOT_MAGIC_SIZE); diff --git a/include/android_image.h b/include/android_image.h index fb3a9d9858..99e7803508 100644 --- a/include/android_image.h +++ b/include/android_image.h @@ -323,6 +323,8 @@ struct andr_image_data { ulong kernel_ptr; /* kernel address */ u32 kernel_size; /* size in bytes */ u32 ramdisk_size; /* size in bytes */ + ulong vendor_ramdisk_ptr; /* vendor ramdisk address */ + u32 vendor_ramdisk_size; /* vendor ramdisk size*/ u32 boot_ramdisk_size; /* size in bytes */ ulong second_ptr; /* secondary bootloader address */ u32 second_size; /* secondary bootloader size */ @@ -342,6 +344,7 @@ struct andr_image_data { ulong tags_addr; /* physical addr for kernel tags */ u32 header_version; /* version of the boot image header */ u32 boot_img_total_size; /* boot image size */ + u32 vendor_boot_img_total_size; /* vendor boot image size */ }; #endif diff --git a/include/image.h b/include/image.h index f84c03f08f..c2e751c136 100644 --- a/include/image.h +++ b/include/image.h @@ -1876,6 +1876,17 @@ bool android_image_print_dtb_contents(ulong hdr_addr); */ bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr); +/** + * is_android_vendor_boot_image_header() - Check the magic of vendor boot image + * + * This checks the header of Android vendor boot image and verifies the magic + * is "VNDRBOOT" + * + * @vendor_boot_img: Pointer to boot image + * Return: non-zero if the magic is correct, zero otherwise + */ +bool is_android_vendor_boot_image_header(const void *vendor_boot_img); + /** * board_fit_config_name_match() - Check for a matching board name * From c79a2e6823d5a3a2813f66d03023c0a192c27e7e Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:13 +0100 Subject: [PATCH 058/805] android: boot: ramdisk: support vendor ramdisk Version 3 and 4 of boot image header introduced vendor boot ramdisk: Please check include/android_image.h for details. The ramdisk is now split into a generic ramdisk in boot image and a vendor ramdisk in vendor boot image. Support the new vendor ramdisk. Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/image-android.c | 13 +++++++++++-- include/image.h | 4 ++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index 712d437766..35243fd5b1 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -25,6 +25,7 @@ static void android_boot_image_v3_v4_parse_hdr(const struct andr_boot_img_hdr_v3 data->kcmdline = hdr->cmdline; data->header_version = hdr->header_version; + data->ramdisk_ptr = env_get_ulong("ramdisk_addr_r", 16, 0); /* * The header takes a full page, the remaining components are aligned @@ -322,10 +323,11 @@ ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr, return image_decomp_type(p, sizeof(u32)); } -int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, - const void *vendor_boot_img, ulong *rd_data, ulong *rd_len) +int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, + ulong *rd_data, ulong *rd_len) { struct andr_image_data img_data = {0}; + ulong ramdisk_ptr; if (!android_image_get_data(hdr, vendor_boot_img, &img_data)) return -EINVAL; @@ -334,6 +336,13 @@ int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, *rd_data = *rd_len = 0; return -1; } + if (img_data.header_version > 2) { + ramdisk_ptr = img_data.ramdisk_ptr; + memcpy((void *)(ramdisk_ptr), (void *)img_data.vendor_ramdisk_ptr, + img_data.vendor_ramdisk_size); + memcpy((void *)(ramdisk_ptr + img_data.vendor_ramdisk_size), + (void *)img_data.ramdisk_ptr, img_data.boot_ramdisk_size); + } printf("RAM disk load addr 0x%08lx size %u KiB\n", img_data.ramdisk_ptr, DIV_ROUND_UP(img_data.ramdisk_size, 1024)); diff --git a/include/image.h b/include/image.h index c2e751c136..c4d9b1c575 100644 --- a/include/image.h +++ b/include/image.h @@ -1782,8 +1782,8 @@ int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, * @rd_len: Pointer to a ulong variable, will hold ramdisk length * Return: 0 if succeeded, -1 if ramdisk size is 0 */ -int android_image_get_ramdisk(const struct andr_boot_img_hdr_v0 *hdr, - const void *vendor_boot_img, ulong *rd_data, ulong *rd_len); +int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, + ulong *rd_data, ulong *rd_len); /** * android_image_get_second() - Extracts the secondary bootloader address From b36b227b6a37695ab39306341c3a977cf9b081b6 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:14 +0100 Subject: [PATCH 059/805] android: boot: support extra command line In version 3 and 4 of boot image header, the vendor specific command line are located in vendor boot image. Thus, use extra command line to add those cmd to bootargs. Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/image-android.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/boot/image-android.c b/boot/image-android.c index 35243fd5b1..a944f0a31a 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -55,6 +55,7 @@ static void android_vendor_boot_image_v3_v4_parse_hdr(const struct andr_vnd_boot * The header takes a full page, the remaining components are aligned * on page boundary. */ + data->kcmdline_extra = hdr->cmdline; data->tags_addr = hdr->tags_addr; data->image_name = hdr->name; data->kernel_addr = hdr->kernel_addr; @@ -233,6 +234,11 @@ int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, len += strlen(img_data.kcmdline); } + if (img_data.kcmdline_extra) { + printf("Kernel extra command line: %s\n", img_data.kcmdline_extra); + len += strlen(img_data.kcmdline_extra); + } + char *bootargs = env_get("bootargs"); if (bootargs) len += strlen(bootargs); @@ -252,6 +258,11 @@ int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, if (*img_data.kcmdline) strcat(newbootargs, img_data.kcmdline); + if (img_data.kcmdline_extra) { + strcat(newbootargs, " "); + strcat(newbootargs, img_data.kcmdline_extra); + } + env_set("bootargs", newbootargs); if (os_data) { From 2d0da1972ded075ba783f3ea705662349e77fa61 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:15 +0100 Subject: [PATCH 060/805] android: boot: update android_image_get_dtb_img_addr to support v3, v4 Add support for boot image version 3 and 4 in android_image_get_dtb_img_addr(). Since the dtb is now included in vendor_boot image instead of boot image, extract the dtb address from vendor_boot image when a v3 or v4 is used. Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/image-android.c | 47 +++++++++++++++++++++++++++++++------------- 1 file changed, 33 insertions(+), 14 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index a944f0a31a..6be439ed12 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -457,6 +457,7 @@ exit: static bool android_image_get_dtb_img_addr(ulong hdr_addr, ulong vhdr_addr, ulong *addr) { const struct andr_boot_img_hdr_v0 *hdr; + const struct andr_vnd_boot_img_hdr *v_hdr; ulong dtb_img_addr; bool ret = true; @@ -473,22 +474,40 @@ static bool android_image_get_dtb_img_addr(ulong hdr_addr, ulong vhdr_addr, ulon goto exit; } - if (hdr->dtb_size == 0) { - printf("Error: dtb_size is 0\n"); - ret = false; - goto exit; + if (hdr->header_version == 2) { + if (!hdr->dtb_size) { + printf("Error: dtb_size is 0\n"); + ret = false; + goto exit; + } + /* Calculate the address of DTB area in boot image */ + dtb_img_addr = hdr_addr; + dtb_img_addr += hdr->page_size; + dtb_img_addr += ALIGN(hdr->kernel_size, hdr->page_size); + dtb_img_addr += ALIGN(hdr->ramdisk_size, hdr->page_size); + dtb_img_addr += ALIGN(hdr->second_size, hdr->page_size); + dtb_img_addr += ALIGN(hdr->recovery_dtbo_size, hdr->page_size); + + *addr = dtb_img_addr; } - /* Calculate the address of DTB area in boot image */ - dtb_img_addr = hdr_addr; - dtb_img_addr += hdr->page_size; - dtb_img_addr += ALIGN(hdr->kernel_size, hdr->page_size); - dtb_img_addr += ALIGN(hdr->ramdisk_size, hdr->page_size); - dtb_img_addr += ALIGN(hdr->second_size, hdr->page_size); - dtb_img_addr += ALIGN(hdr->recovery_dtbo_size, hdr->page_size); - - *addr = dtb_img_addr; - + if (hdr->header_version > 2) { + v_hdr = map_sysmem(vhdr_addr, sizeof(*v_hdr)); + if (!v_hdr->dtb_size) { + printf("Error: dtb_size is 0\n"); + ret = false; + unmap_sysmem(v_hdr); + goto exit; + } + /* Calculate the address of DTB area in boot image */ + dtb_img_addr = vhdr_addr; + dtb_img_addr += v_hdr->page_size; + if (v_hdr->vendor_ramdisk_size) + dtb_img_addr += ALIGN(v_hdr->vendor_ramdisk_size, v_hdr->page_size); + *addr = dtb_img_addr; + unmap_sysmem(v_hdr); + goto exit; + } exit: unmap_sysmem(hdr); return ret; From bc6413bdd9a4a7ab8a62232aa4791cc26a0ef215 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:16 +0100 Subject: [PATCH 061/805] drivers: fastboot: zImage flashing is not supported for v3, v4 With vendor boot image introduced in version 3 and 4 of boot image header, boot information is located in both boot image and vendor boot image. Flashing zImage is not supported for version 3 and 4 since this requires updating vendor boot image and/or generating a new image. Print an error message when the boot image header version is greater than 2. Signed-off-by: Safae Ouajih Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- drivers/fastboot/fb_mmc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 29c18cb82a..9d25c40202 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -370,6 +370,14 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc, return -1; } + /* Check if boot image header version is 2 or less */ + if (hdr->header_version > 2) { + pr_err("zImage flashing supported only for boot images v2 and less\n"); + fastboot_fail("zImage flashing supported only for boot images v2 and less", + response); + return -EOPNOTSUPP; + } + /* Check if boot image has second stage in it (we don't support it) */ if (hdr->second_size > 0) { pr_err("moving second stage is not supported yet\n"); From 636da2039aea4ea3a638b14da0a9ec258897a10c Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:17 +0100 Subject: [PATCH 062/805] android: boot: support boot image header version 3 and 4 Enable the support for boot image header version 3 and 4 using abootimg command. In order to use version 3 or 4: 1- Vendor boot image address should be given to abootimg cmd. abootimg addr $1 $vendor_boot_load_addr 2- "ramdisk_addr_r" env variable (ramdisk address) should be set to host the ramdisk : generic ramdisk + vendor ramdisk Replace "struct andr_boot_img_hdr_v0*" by "void *" in some functions since v3 and v4 are now supported as well. Signed-off-by: Safae Ouajih Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/bootm.c | 37 ++++++++++++++++++++++++++++++++----- boot/image-android.c | 16 ++++++++++------ boot/image-board.c | 18 +++++++++++++++--- boot/image-fdt.c | 2 +- cmd/abootimg.c | 24 ++++++++++++++++++++++-- include/image.h | 25 +++++++++++++++++++------ 6 files changed, 99 insertions(+), 23 deletions(-) diff --git a/boot/bootm.c b/boot/bootm.c index 28a8fc3261..4144ff3b03 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -113,6 +113,10 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { const void *os_hdr; +#ifdef CONFIG_ANDROID_BOOT_IMAGE + const void *vendor_boot_img; + const void *boot_img; +#endif bool ep_found = false; int ret; @@ -181,14 +185,23 @@ static int bootm_find_os(struct cmd_tbl *cmdtp, int flag, int argc, #endif #ifdef CONFIG_ANDROID_BOOT_IMAGE case IMAGE_FORMAT_ANDROID: + boot_img = os_hdr; + vendor_boot_img = NULL; + if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { + boot_img = map_sysmem(get_abootimg_addr(), 0); + vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0); + } images.os.type = IH_TYPE_KERNEL; - images.os.comp = android_image_get_kcomp(os_hdr, NULL); + images.os.comp = android_image_get_kcomp(boot_img, vendor_boot_img); images.os.os = IH_OS_LINUX; - - images.os.end = android_image_get_end(os_hdr, NULL); - images.os.load = android_image_get_kload(os_hdr, NULL); + images.os.end = android_image_get_end(boot_img, vendor_boot_img); + images.os.load = android_image_get_kload(boot_img, vendor_boot_img); images.ep = images.os.load; ep_found = true; + if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { + unmap_sysmem(vendor_boot_img); + unmap_sysmem(boot_img); + } break; #endif default: @@ -889,6 +902,10 @@ static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc, int os_noffset; #endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + const void *boot_img; + const void *vendor_boot_img; +#endif img_addr = genimg_get_kernel_addr_fit(argc < 1 ? NULL : argv[0], &fit_uname_config, &fit_uname_kernel); @@ -964,10 +981,20 @@ static const void *boot_get_kernel(struct cmd_tbl *cmdtp, int flag, int argc, #endif #ifdef CONFIG_ANDROID_BOOT_IMAGE case IMAGE_FORMAT_ANDROID: + boot_img = buf; + vendor_boot_img = NULL; + if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { + boot_img = map_sysmem(get_abootimg_addr(), 0); + vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0); + } printf("## Booting Android Image at 0x%08lx ...\n", img_addr); - if (android_image_get_kernel(buf, NULL, images->verify, + if (android_image_get_kernel(boot_img, vendor_boot_img, images->verify, os_data, os_len)) return NULL; + if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { + unmap_sysmem(vendor_boot_img); + unmap_sysmem(boot_img); + } break; #endif default: diff --git a/boot/image-android.c b/boot/image-android.c index 6be439ed12..fb29ff403f 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -201,7 +201,7 @@ static ulong android_image_get_kernel_addr(struct andr_image_data *img_data) * Return: Zero, os start address and length on success, * otherwise on failure. */ -int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, +int android_image_get_kernel(const void *hdr, const void *vendor_boot_img, int verify, ulong *os_data, ulong *os_len) { @@ -286,7 +286,7 @@ bool is_android_vendor_boot_image_header(const void *vendor_boot_img) return !memcmp(VENDOR_BOOT_MAGIC, vendor_boot_img, ANDR_VENDOR_BOOT_MAGIC_SIZE); } -bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr) +bool is_android_boot_image_header(const void *hdr) { return !memcmp(ANDR_BOOT_MAGIC, hdr, ANDR_BOOT_MAGIC_SIZE); } @@ -305,7 +305,7 @@ ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr, return img_data.boot_img_total_size; } -ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr, +ulong android_image_get_kload(const void *hdr, const void *vendor_boot_img) { struct andr_image_data img_data; @@ -316,7 +316,7 @@ ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr, return android_image_get_kernel_addr(&img_data); } -ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr, +ulong android_image_get_kcomp(const void *hdr, const void *vendor_boot_img) { struct andr_image_data img_data; @@ -364,14 +364,18 @@ int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, return 0; } -int android_image_get_second(const struct andr_boot_img_hdr_v0 *hdr, - ulong *second_data, ulong *second_len) +int android_image_get_second(const void *hdr, ulong *second_data, ulong *second_len) { struct andr_image_data img_data; if (!android_image_get_data(hdr, NULL, &img_data)) return -EINVAL; + if (img_data.header_version > 2) { + printf("Second stage bootloader is only supported for boot image version <= 2\n"); + return -EOPNOTSUPP; + } + if (!img_data.second_size) { *second_data = *second_len = 0; return -1; diff --git a/boot/image-board.c b/boot/image-board.c index 2d73c76a4a..7dd0c32e6e 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -426,10 +426,22 @@ static int select_ramdisk(struct bootm_headers *images, const char *select, u8 a break; case IMAGE_FORMAT_ANDROID: if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) { - void *ptr = map_sysmem(images->os.start, 0); int ret; - ret = android_image_get_ramdisk(ptr, NULL, rd_datap, rd_lenp); - unmap_sysmem(ptr); + if (IS_ENABLED(CONFIG_CMD_ABOOTIMG)) { + void *boot_img = map_sysmem(get_abootimg_addr(), 0); + void *vendor_boot_img = map_sysmem(get_avendor_bootimg_addr(), 0); + + ret = android_image_get_ramdisk(boot_img, vendor_boot_img, + rd_datap, rd_lenp); + unmap_sysmem(vendor_boot_img); + unmap_sysmem(boot_img); + } else { + void *ptr = map_sysmem(images->os.start, 0); + + ret = android_image_get_ramdisk(ptr, NULL, rd_datap, rd_lenp); + unmap_sysmem(ptr); + } + if (ret) return ret; done = true; diff --git a/boot/image-fdt.c b/boot/image-fdt.c index d639f37896..f10200f647 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -529,7 +529,7 @@ int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, } #ifdef CONFIG_ANDROID_BOOT_IMAGE } else if (genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) { - struct andr_boot_img_hdr_v0 *hdr = buf; + void *hdr = buf; ulong fdt_data, fdt_len; u32 fdt_size, dtb_idx; /* diff --git a/cmd/abootimg.c b/cmd/abootimg.c index 4d6cf0fa3e..2653b555b1 100644 --- a/cmd/abootimg.c +++ b/cmd/abootimg.c @@ -17,6 +17,16 @@ static ulong _abootimg_addr = -1; static ulong _avendor_bootimg_addr = -1; +ulong get_abootimg_addr(void) +{ + return (_abootimg_addr == -1 ? image_load_addr : _abootimg_addr); +} + +ulong get_avendor_bootimg_addr(void) +{ + return _avendor_bootimg_addr; +} + static int abootimg_get_ver(int argc, char *const argv[]) { const struct andr_boot_img_hdr_v0 *hdr; @@ -70,12 +80,21 @@ static int abootimg_get_dtb_load_addr(int argc, char *const argv[]) return CMD_RET_USAGE; struct andr_image_data img_data = {0}; const struct andr_boot_img_hdr_v0 *hdr; + const struct andr_vnd_boot_img_hdr *vhdr; hdr = map_sysmem(abootimg_addr(), sizeof(*hdr)); - if (!android_image_get_data(hdr, NULL, &img_data)) { + if (get_avendor_bootimg_addr() != -1) + vhdr = map_sysmem(get_avendor_bootimg_addr(), sizeof(*vhdr)); + + if (!android_image_get_data(hdr, vhdr, &img_data)) { + if (get_avendor_bootimg_addr() != -1) + unmap_sysmem(vhdr); unmap_sysmem(hdr); return CMD_RET_FAILURE; } + + if (get_avendor_bootimg_addr() != -1) + unmap_sysmem(vhdr); unmap_sysmem(hdr); if (img_data.header_version < 2) { @@ -119,7 +138,8 @@ static int abootimg_get_dtb_by_index(int argc, char *const argv[]) return CMD_RET_FAILURE; } - if (!android_image_get_dtb_by_index(abootimg_addr(), 0, num, + if (!android_image_get_dtb_by_index(abootimg_addr(), + get_avendor_bootimg_addr(), num, &addr, &size)) { return CMD_RET_FAILURE; } diff --git a/include/image.h b/include/image.h index c4d9b1c575..456197d6fd 100644 --- a/include/image.h +++ b/include/image.h @@ -1767,7 +1767,7 @@ struct andr_boot_img_hdr_v0; * Return: Zero, os start address and length on success, * otherwise on failure. */ -int android_image_get_kernel(const struct andr_boot_img_hdr_v0 *hdr, +int android_image_get_kernel(const void *hdr, const void *vendor_boot_img, int verify, ulong *os_data, ulong *os_len); @@ -1796,8 +1796,7 @@ int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, * @second_len : Pointer to a ulong variable, will hold secondary bootloader length * Return: 0 if succeeded, -1 if secondary bootloader size is 0 */ -int android_image_get_second(const struct andr_boot_img_hdr_v0 *hdr, - ulong *second_data, ulong *second_len); +int android_image_get_second(const void *hdr, ulong *second_data, ulong *second_len); bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size); /** @@ -1838,7 +1837,7 @@ ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr, * @vendor_boot_img : Pointer to vendor boot image header * Return: The kernel load address */ -ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr, +ulong android_image_get_kload(const void *hdr, const void *vendor_boot_img); /** @@ -1850,7 +1849,7 @@ ulong android_image_get_kload(const struct andr_boot_img_hdr_v0 *hdr, * @vendor_boot_img : Pointer to vendor boot image header * Return: Kernel compression type */ -ulong android_image_get_kcomp(const struct andr_boot_img_hdr_v0 *hdr, +ulong android_image_get_kcomp(const void *hdr, const void *vendor_boot_img); /** @@ -1874,7 +1873,7 @@ bool android_image_print_dtb_contents(ulong hdr_addr); * @hdr: Pointer to boot image * Return: non-zero if the magic is correct, zero otherwise */ -bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr); +bool is_android_boot_image_header(const void *hdr); /** * is_android_vendor_boot_image_header() - Check the magic of vendor boot image @@ -1887,6 +1886,20 @@ bool is_android_boot_image_header(const struct andr_boot_img_hdr_v0 *hdr); */ bool is_android_vendor_boot_image_header(const void *vendor_boot_img); +/** + * get_abootimg_addr() - Get Android boot image address + * + * Return: Android boot image address + */ +ulong get_abootimg_addr(void); + +/** + * get_avendor_bootimg_addr() - Get Android vendor boot image address + * + * Return: Android vendor boot image address + */ +ulong get_avendor_bootimg_addr(void); + /** * board_fit_config_name_match() - Check for a matching board name * From 57e405e1f4745cdca49a4a6b260afe68592b1d5c Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:18 +0100 Subject: [PATCH 063/805] android: boot: support bootconfig Support Bootconfig feature. - The bootconfig feature replaces the androidboot.* kernel cmdline options. This was adapted from downstream [1] commit : 7af0a0506d4d ("cuttlefish: support bootconfig parameters"). Link:[1] https://android.googlesource.com/platform/external/u-boot/ Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek --- boot/image-android.c | 58 +++++++++++++++++++++++++++++++++++++++-- include/android_image.h | 11 ++++++++ 2 files changed, 67 insertions(+), 2 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index fb29ff403f..88e40bc7ec 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -18,6 +18,45 @@ static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1]; +static ulong checksum(const unsigned char *buffer, ulong size) +{ + ulong sum = 0; + + for (ulong i = 0; i < size; i++) + sum += buffer[i]; + return sum; +} + +static bool is_trailer_present(ulong bootconfig_end_addr) +{ + return !strncmp((char *)(bootconfig_end_addr - BOOTCONFIG_MAGIC_SIZE), + BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE); +} + +static ulong add_trailer(ulong bootconfig_start_addr, ulong bootconfig_size) +{ + ulong end; + ulong sum; + + if (!bootconfig_start_addr) + return -1; + if (!bootconfig_size) + return 0; + + end = bootconfig_start_addr + bootconfig_size; + if (is_trailer_present(end)) + return 0; + + memcpy((void *)(end), &bootconfig_size, BOOTCONFIG_SIZE_SIZE); + sum = checksum((unsigned char *)bootconfig_start_addr, bootconfig_size); + memcpy((void *)(end + BOOTCONFIG_SIZE_SIZE), &sum, + BOOTCONFIG_CHECKSUM_SIZE); + memcpy((void *)(end + BOOTCONFIG_SIZE_SIZE + BOOTCONFIG_CHECKSUM_SIZE), + BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE); + + return BOOTCONFIG_TRAILER_SIZE; +} + static void android_boot_image_v3_v4_parse_hdr(const struct andr_boot_img_hdr_v3 *hdr, struct andr_image_data *data) { @@ -61,6 +100,7 @@ static void android_vendor_boot_image_v3_v4_parse_hdr(const struct andr_vnd_boot data->kernel_addr = hdr->kernel_addr; data->ramdisk_addr = hdr->ramdisk_addr; data->dtb_load_addr = hdr->dtb_addr; + data->bootconfig_size = hdr->bootconfig_size; end = (ulong)hdr; end += hdr->page_size; if (hdr->vendor_ramdisk_size) { @@ -75,7 +115,13 @@ static void android_vendor_boot_image_v3_v4_parse_hdr(const struct andr_vnd_boot end += ALIGN(hdr->dtb_size, hdr->page_size); end += ALIGN(hdr->vendor_ramdisk_table_size, hdr->page_size); - end += ALIGN(hdr->bootconfig_size, hdr->page_size); + data->bootconfig_addr = end; + if (hdr->bootconfig_size) { + data->bootconfig_size += add_trailer(data->bootconfig_addr, + data->bootconfig_size); + data->ramdisk_size += data->bootconfig_size; + } + end += ALIGN(data->bootconfig_size, hdr->page_size); data->vendor_boot_img_total_size = end - (ulong)hdr; } @@ -352,7 +398,15 @@ int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img, memcpy((void *)(ramdisk_ptr), (void *)img_data.vendor_ramdisk_ptr, img_data.vendor_ramdisk_size); memcpy((void *)(ramdisk_ptr + img_data.vendor_ramdisk_size), - (void *)img_data.ramdisk_ptr, img_data.boot_ramdisk_size); + (void *)img_data.ramdisk_ptr, + img_data.boot_ramdisk_size); + if (img_data.bootconfig_size) { + memcpy((void *) + (ramdisk_ptr + img_data.vendor_ramdisk_size + + img_data.boot_ramdisk_size), + (void *)img_data.bootconfig_addr, + img_data.bootconfig_size); + } } printf("RAM disk load addr 0x%08lx size %u KiB\n", diff --git a/include/android_image.h b/include/android_image.h index 99e7803508..d503c980b2 100644 --- a/include/android_image.h +++ b/include/android_image.h @@ -25,6 +25,14 @@ #define ANDR_VENDOR_BOOT_ARGS_SIZE 2048 #define ANDR_VENDOR_BOOT_NAME_SIZE 16 +#define BOOTCONFIG_MAGIC "#BOOTCONFIG\n" +#define BOOTCONFIG_MAGIC_SIZE 12 +#define BOOTCONFIG_SIZE_SIZE 4 +#define BOOTCONFIG_CHECKSUM_SIZE 4 +#define BOOTCONFIG_TRAILER_SIZE BOOTCONFIG_MAGIC_SIZE + \ + BOOTCONFIG_SIZE_SIZE + \ + BOOTCONFIG_CHECKSUM_SIZE + struct andr_boot_img_hdr_v3 { u8 magic[ANDR_BOOT_MAGIC_SIZE]; @@ -337,6 +345,9 @@ struct andr_image_data { const char *kcmdline_extra; /* vendor-boot extra kernel cmdline */ const char *image_name; /* asciiz product name */ + ulong bootconfig_addr; /* bootconfig image address */ + ulong bootconfig_size; /* bootconfig image size */ + u32 kernel_addr; /* physical load addr */ ulong ramdisk_addr; /* physical load addr */ ulong ramdisk_ptr; /* ramdisk address */ From 3e7b71c7286b8e12891c4fd954c21ed8be018de7 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:19 +0100 Subject: [PATCH 064/805] doc: android: add documentation for v3, v4 boot image header Update the Android documentation to describe version 3 and 4 of boot image header. Signed-off-by: Safae Ouajih Reviewed-by: Mattijs Korpershoek Reviewed-by: Simon Glass Tested-by: Mattijs Korpershoek --- doc/android/boot-image.rst | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/doc/android/boot-image.rst b/doc/android/boot-image.rst index 71db02521b..c719b4d711 100644 --- a/doc/android/boot-image.rst +++ b/doc/android/boot-image.rst @@ -27,11 +27,21 @@ next image headers: * v2: used in devices launched with Android 10; adds ``dtb`` field, which references payload containing DTB blobs (either concatenated one after the other, or in Android DTBO image format) +* v3: used in devices launched with Android 11; adds ``vendor_boot`` partition + and removes the second-stage bootloader and recovery image support. The new + ``vendor_boot`` partition holds the device tree blob (DTB) and a vendor ramdisk. + The generic ramdisk in ``boot`` partition is loaded immediately following + the vendor ramdisk. +* v4: used in devices launched with Android 12; provides a boot signature in boot + image header, supports multiple vendor ramdisk fragments in ``vendor_boot`` + partition. This version also adds a bootconfig section at the end of the vendor + boot image, this section contains boot configuration parameters known at build time + (see [9]_ for details). v2, v1 and v0 formats are backward compatible. The Android Boot Image format is represented by -:c:type:`struct andr_img_hdr ` in U-Boot, and can be seen in +:c:type:`struct andr_image_data ` in U-Boot, and can be seen in ``include/android_image.h``. U-Boot supports booting Android Boot Image and also has associated command @@ -153,3 +163,4 @@ References .. [6] :doc:`avb2` .. [7] https://source.android.com/devices/bootloader .. [8] https://connect.linaro.org/resources/san19/san19-217/ +.. [9] https://source.android.com/docs/core/architecture/bootloader/implementing-bootconfig From 83d48a3c8bfbbbc2a8ad951b211081f72fc268b6 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:20 +0100 Subject: [PATCH 065/805] test/py: android: extend abootimg test test_abootimg is extended to include the testing of boot images version 4. For this, boot.img and vendor_boot.img have been generated using mkbootimg tool with setting the header version to 4. This tests: - Getting the header version using abootimg - Extracting the load address of the dtb - Extracting the dtb start address in RAM Running test: $ ./test/py/test.py --bd sandbox --build -k test_abootimg Signed-off-by: Safae Ouajih Reviewed-by: Simon Glass Tested-by: Mattijs Korpershoek --- test/py/tests/test_android/test_abootimg.py | 136 ++++++++++++++++++-- 1 file changed, 123 insertions(+), 13 deletions(-) diff --git a/test/py/tests/test_android/test_abootimg.py b/test/py/tests/test_android/test_abootimg.py index 43a7099c46..6a8ff34538 100644 --- a/test/py/tests/test_android/test_abootimg.py +++ b/test/py/tests/test_android/test_abootimg.py @@ -32,6 +32,23 @@ Now one can obtain original boot.img from this hex dump like this: $ xxd -r -p boot.img.gz.hex boot.img.gz $ gunzip -9 boot.img.gz + +For boot image header version 4, these tests rely on two images that are generated +using the same steps above : + +1- boot.img : + $ mkbootimg --kernel ./kernel --ramdisk ./ramdisk.img \ + --cmdline "cmdline test" --dtb ./dtb.img \ + --os_version R --os_patch_level 2019-06-05 \ + --header_version 4 --output ./boot.img + +2- vendor_boot.img + $ mkbootimg --kernel ./kernel --ramdisk ./ramdisk.img \ + --cmdline "cmdline test" --dtb ./dtb.img \ + --os_version R --os_patch_level 2019-06-05 \ + --pagesize 4096 --vendor_ramdisk ./ramdisk.img \ + --header_version 4 --vendor_boot ./vboot.img \ + """ # boot.img.gz hex dump @@ -44,6 +61,24 @@ b7762ffff07d345446c1281805e8a0868d81e117a45e111c0d8dc101b253 9c03c41a0c90f17fe85400986d82452b6c3680198a192a0ce17c3610ae34 d4a9820881a70f3873f35352731892f3730b124b32937252a96bb9119ae5 463a5546f82c1f05a360148c8251300a462e000085bf67f200200000""" + +# boot img v4 hex dump +boot_img_hex = """1f8b080827b0cd630203626f6f742e696d6700edd8bd0d82601885d1d7c4 +58d8c808b88195bd098d8d246e40e42b083f1aa0717be99d003d277916b8 +e5bddc8a7b792d8e8788c896ce9b88d32ebe6c971e7ddd3543cae734cd01 +c0ffc84c0000b0766d1a87d4e5afeadd3dab7a6f10000000f84163d5d7cd +d43a000000000000000060c53e7544995700400000""" + +# vendor boot image v4 hex dump +vboot_img_hex = """1f8b0808baaecd63020376626f6f742e696d6700edd8310b824018c6f1b3 +222a08f41b3436b4280dcdd19c11d16ee9109d18d59042d047ec8b04cd0d +d19d5a4345534bf6ffc173ef29272f38e93b1d0ec67dd79d548462aa1cd2 +d5d20b0000f8438678f90c18d584b8a4bbb3a557991ecb2a0000f80d6b2f +f4179b656be5c532f2fc066f040000000080e23936af2755f62a3d918df1 +db2a7ab67f9ffdeb7df7cda3465ecb79c4ce7e5c577562bb9364b74449a5 +1e467e20c53c0a57de763193c1779b3b4fcd9d4ee27c6a0e00000000c0ff +309ffea7010000000040f1dc004129855400400000""" + # Expected response for "abootimg dtb_dump" command dtb_dump_resp="""## DTB area contents (concat format): - DTB #0: @@ -56,15 +91,21 @@ dtb_dump_resp="""## DTB area contents (concat format): (DTB)compatible = y2,z2""" # Address in RAM where to load the boot image ('abootimg' looks in $loadaddr) loadaddr = 0x1000 +# Address in RAM where to load the vendor boot image ('abootimg' looks in $vloadaddr) +vloadaddr= 0x10000 # Expected DTB #1 offset from the boot image start address dtb1_offset = 0x187d +# Expected DTB offset from the vendor boot image start address +dtb2_offset = 0x207d # DTB #1 start address in RAM dtb1_addr = loadaddr + dtb1_offset +# DTB #2 start address in RAM +dtb2_addr = vloadaddr + dtb2_offset class AbootimgTestDiskImage(object): """Disk image used by abootimg tests.""" - def __init__(self, u_boot_console): + def __init__(self, u_boot_console, image_name, hex_img): """Initialize a new AbootimgDiskImage object. Args: @@ -74,13 +115,13 @@ class AbootimgTestDiskImage(object): Nothing. """ - gz_hex = u_boot_console.config.persistent_data_dir + '/boot.img.gz.hex' - gz = u_boot_console.config.persistent_data_dir + '/boot.img.gz' + gz_hex = u_boot_console.config.persistent_data_dir + '/' + image_name + '.gz.hex' + gz = u_boot_console.config.persistent_data_dir + '/' + image_name + '.gz' - filename = 'boot.img' + filename = image_name persistent = u_boot_console.config.persistent_data_dir + '/' + filename self.path = u_boot_console.config.result_dir + '/' + filename - + u_boot_console.log.action('persistent is ' + persistent) with u_boot_utils.persistent_file_helper(u_boot_console.log, persistent): if os.path.exists(persistent): u_boot_console.log.action('Disk image file ' + persistent + @@ -89,19 +130,17 @@ class AbootimgTestDiskImage(object): u_boot_console.log.action('Generating ' + persistent) f = open(gz_hex, "w") - f.write(img_hex) + f.write(hex_img) f.close() - cmd = ('xxd', '-r', '-p', gz_hex, gz) u_boot_utils.run_and_log(u_boot_console, cmd) - cmd = ('gunzip', '-9', gz) u_boot_utils.run_and_log(u_boot_console, cmd) cmd = ('cp', persistent, self.path) u_boot_utils.run_and_log(u_boot_console, cmd) -gtdi = None +gtdi1 = None @pytest.fixture(scope='function') def abootimg_disk_image(u_boot_console): """pytest fixture to provide a AbootimgTestDiskImage object to tests. @@ -109,10 +148,36 @@ def abootimg_disk_image(u_boot_console): function-scoped. However, we don't need to actually do any function-scope work, so this simply returns the same object over and over each time.""" - global gtdi - if not gtdi: - gtdi = AbootimgTestDiskImage(u_boot_console) - return gtdi + global gtdi1 + if not gtdi1: + gtdi1 = AbootimgTestDiskImage(u_boot_console, 'boot.img', img_hex) + return gtdi1 + +gtdi2 = None +@pytest.fixture(scope='function') +def abootimgv4_disk_image_vboot(u_boot_console): + """pytest fixture to provide a AbootimgTestDiskImage object to tests. + This is function-scoped because it uses u_boot_console, which is also + function-scoped. However, we don't need to actually do any function-scope + work, so this simply returns the same object over and over each time.""" + + global gtdi2 + if not gtdi2: + gtdi2 = AbootimgTestDiskImage(u_boot_console, 'vendor_boot.img', vboot_img_hex) + return gtdi2 + +gtdi3 = None +@pytest.fixture(scope='function') +def abootimgv4_disk_image_boot(u_boot_console): + """pytest fixture to provide a AbootimgTestDiskImage object to tests. + This is function-scoped because it uses u_boot_console, which is also + function-scoped. However, we don't need to actually do any function-scope + work, so this simply returns the same object over and over each time.""" + + global gtdi3 + if not gtdi3: + gtdi3 = AbootimgTestDiskImage(u_boot_console, 'bootv4.img', boot_img_hex) + return gtdi3 @pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('android_boot_image') @@ -157,3 +222,48 @@ def test_abootimg(abootimg_disk_image, u_boot_console): u_boot_console.run_command('fdt get value v / model') response = u_boot_console.run_command('env print v') assert response == 'v=x2' + +@pytest.mark.boardspec('sandbox') +@pytest.mark.buildconfigspec('android_boot_image') +@pytest.mark.buildconfigspec('cmd_abootimg') +@pytest.mark.buildconfigspec('cmd_fdt') +@pytest.mark.requiredtool('xxd') +@pytest.mark.requiredtool('gunzip') +def test_abootimgv4(abootimgv4_disk_image_vboot, abootimgv4_disk_image_boot, u_boot_console): + """Test the 'abootimg' command with boot image header v4.""" + + cons = u_boot_console + cons.log.action('Loading disk image to RAM...') + cons.run_command('setenv loadaddr 0x%x' % (loadaddr)) + cons.run_command('setenv vloadaddr 0x%x' % (vloadaddr)) + cons.run_command('host load hostfs - 0x%x %s' % (vloadaddr, + abootimgv4_disk_image_vboot.path)) + cons.run_command('host load hostfs - 0x%x %s' % (loadaddr, + abootimgv4_disk_image_boot.path)) + cons.run_command('abootimg addr 0x%x 0x%x' % (loadaddr, vloadaddr)) + cons.log.action('Testing \'abootimg get ver\'...') + response = cons.run_command('abootimg get ver') + assert response == "4" + cons.run_command('abootimg get ver v') + response = cons.run_command('env print v') + assert response == 'v=4' + + cons.log.action('Testing \'abootimg get recovery_dtbo\'...') + response = cons.run_command('abootimg get recovery_dtbo a') + assert response == 'Error: header version must be >= 1 and <= 2 to get dtbo' + + cons.log.action('Testing \'abootimg get dtb_load_addr\'...') + cons.run_command('abootimg get dtb_load_addr a') + response = cons.run_command('env print a') + assert response == 'a=11f00000' + + cons.log.action('Testing \'abootimg get dtb --index\'...') + cons.run_command('abootimg get dtb --index=1 dtb2_start') + response = cons.run_command('env print dtb2_start') + correct_str = "dtb2_start=%x" % (dtb2_addr) + assert response == correct_str + + cons.run_command('fdt addr $dtb2_start') + cons.run_command('fdt get value v / model') + response = cons.run_command('env print v') + assert response == 'v=x2' From f4449397551a82f0c1d9714d648f1efb90d56962 Mon Sep 17 00:00:00 2001 From: Safae Ouajih Date: Mon, 6 Feb 2023 00:50:21 +0100 Subject: [PATCH 066/805] Dockerfile: add mkbootimg tool mkbootimg tool is part of the Android project and it is used to pack Android boot images such as boot image and vendor_boot image. Use the following command to run mkbootimg: $ python3 -m mkbootimg Add mkbootimg to the docker file Signed-off-by: Safae Ouajih Tested-by: Mattijs Korpershoek --- tools/docker/Dockerfile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 801bebf1b0..9804b55ddd 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -284,3 +284,7 @@ RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/ RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman RUN /bin/echo -e "\nsandbox = x86_64" >> ~/.buildman RUN /bin/echo -e "\nx86 = i386" >> ~/.buildman; + +# Add mkbootimg tool +RUN git clone https://android.googlesource.com/platform/system/tools/mkbootimg /home/uboot/mkbootimg +ENV PYTHONPATH "${PYTHONPATH}:/home/uboot/mkbootimg" From e45bba562ff1b273bdff5cc43f7c43fe829b44b4 Mon Sep 17 00:00:00 2001 From: Tobias Waldekranz Date: Thu, 16 Feb 2023 16:33:47 +0100 Subject: [PATCH 067/805] image: Fix script execution from FIT images with external data Update the script loading code to recognize when script data is stored externally from the FIT metadata (i.e., built with `mkimage -E`). Signed-off-by: Tobias Waldekranz Reviewed-by: Simon Glass --- boot/image-board.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/boot/image-board.c b/boot/image-board.c index 7dd0c32e6e..c602832249 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -1126,7 +1126,8 @@ fallback: } /* get script subimage data address and length */ - if (fit_image_get_data(fit_hdr, noffset, &fit_data, &fit_len)) { + if (fit_image_get_data_and_size(fit_hdr, noffset, + &fit_data, &fit_len)) { puts("Could not find script subimage data\n"); return 1; } From 3d2fc79714542702f55fc407f7e7885464c39cd2 Mon Sep 17 00:00:00 2001 From: Tobias Waldekranz Date: Thu, 16 Feb 2023 16:33:48 +0100 Subject: [PATCH 068/805] cmd: blk: Allow generic read/write operations to work in sandbox Ensure that the memory destination/source addresses of block read/write operations are mapped in before access. Currently, this is only needed on sandbox builds. Signed-off-by: Tobias Waldekranz Reviewed-by: Simon Glass --- cmd/blk_common.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/cmd/blk_common.c b/cmd/blk_common.c index 75a072caf5..9f9d4327a9 100644 --- a/cmd/blk_common.c +++ b/cmd/blk_common.c @@ -11,6 +11,7 @@ #include #include #include +#include int blk_common_cmd(int argc, char *const argv[], enum uclass_id uclass_id, int *cur_devnump) @@ -63,31 +64,37 @@ int blk_common_cmd(int argc, char *const argv[], enum uclass_id uclass_id, default: /* at least 4 args */ if (strcmp(argv[1], "read") == 0) { - ulong addr = hextoul(argv[2], NULL); + phys_addr_t paddr = hextoul(argv[2], NULL); lbaint_t blk = hextoul(argv[3], NULL); ulong cnt = hextoul(argv[4], NULL); + void *vaddr; ulong n; printf("\n%s read: device %d block # "LBAFU", count %lu ... ", if_name, *cur_devnump, blk, cnt); + vaddr = map_sysmem(paddr, 512 * cnt); n = blk_read_devnum(uclass_id, *cur_devnump, blk, cnt, - (ulong *)addr); + vaddr); + unmap_sysmem(vaddr); printf("%ld blocks read: %s\n", n, n == cnt ? "OK" : "ERROR"); return n == cnt ? 0 : 1; } else if (strcmp(argv[1], "write") == 0) { - ulong addr = hextoul(argv[2], NULL); + phys_addr_t paddr = hextoul(argv[2], NULL); lbaint_t blk = hextoul(argv[3], NULL); ulong cnt = hextoul(argv[4], NULL); + void *vaddr; ulong n; printf("\n%s write: device %d block # "LBAFU", count %lu ... ", if_name, *cur_devnump, blk, cnt); + vaddr = map_sysmem(paddr, 512 * cnt); n = blk_write_devnum(uclass_id, *cur_devnump, blk, cnt, - (ulong *)addr); + vaddr); + unmap_sysmem(vaddr); printf("%ld blocks written: %s\n", n, n == cnt ? "OK" : "ERROR"); From c41e209ea67ee9be04519a3c7afda80a32253317 Mon Sep 17 00:00:00 2001 From: Tobias Waldekranz Date: Thu, 16 Feb 2023 16:33:49 +0100 Subject: [PATCH 069/805] blk: blkmap: Add basic infrastructure blkmaps are loosely modeled on Linux's device mapper subsystem. The basic idea is that you can create virtual block devices whose blocks can be backed by a plethora of sources that are user configurable. This change just adds the basic infrastructure for creating and removing blkmap devices. Subsequent changes will extend this to add support for actual mappings. Signed-off-by: Tobias Waldekranz Reviewed-by: Simon Glass --- MAINTAINERS | 6 + drivers/block/Kconfig | 18 ++ drivers/block/Makefile | 1 + drivers/block/blk-uclass.c | 1 + drivers/block/blkmap.c | 343 +++++++++++++++++++++++++++++++++++++ include/blkmap.h | 35 ++++ include/dm/uclass-id.h | 1 + 7 files changed, 405 insertions(+) create mode 100644 drivers/block/blkmap.c create mode 100644 include/blkmap.h diff --git a/MAINTAINERS b/MAINTAINERS index d2e245e5e9..8c1305e8a1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -793,6 +793,12 @@ M: Alper Nebi Yasak S: Maintained F: tools/binman/ +BLKMAP +M: Tobias Waldekranz +S: Maintained +F: drivers/block/blkmap.c +F: include/blkmap.h + BOOTDEVICE M: Simon Glass S: Maintained diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index e95da48bdc..5a1aeb3d2b 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -67,6 +67,24 @@ config BLOCK_CACHE it will prevent repeated reads from directory structures and other filesystem data structures. +config BLKMAP + bool "Composable virtual block devices (blkmap)" + depends on BLK + help + Create virtual block devices that are backed by various sources, + e.g. RAM, or parts of an existing block device. Though much more + rudimentary, it borrows a lot of ideas from Linux's device mapper + subsystem. + + Example use-cases: + - Treat a region of RAM as a block device, i.e. a RAM disk. This let's + you extract files from filesystem images stored in RAM (perhaps as a + result of a TFTP transfer). + - Create a virtual partition on an existing device. This let's you + access filesystems that aren't stored at an exact partition + boundary. A common example is a filesystem image embedded in an FIT + image. + config SPL_BLOCK_CACHE bool "Use block device cache in SPL" depends on SPL_BLK diff --git a/drivers/block/Makefile b/drivers/block/Makefile index f12447d78d..a161d145fd 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_IDE) += ide.o endif obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o +obj-$(CONFIG_BLKMAP) += blkmap.o obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index c69fc4d518..cb73faaeda 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -32,6 +32,7 @@ static struct { { UCLASS_EFI_LOADER, "efiloader" }, { UCLASS_VIRTIO, "virtio" }, { UCLASS_PVBLOCK, "pvblock" }, + { UCLASS_BLKMAP, "blkmap" }, }; static enum uclass_id uclass_name_to_iftype(const char *uclass_idname) diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c new file mode 100644 index 0000000000..acfc002ceb --- /dev/null +++ b/drivers/block/blkmap.c @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Addiva Elektronik + * Author: Tobias Waldekranz + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct blkmap; + +/** + * struct blkmap_slice - Region mapped to a blkmap + * + * Common data for a region mapped to a blkmap, specialized by each + * map type. + * + * @node: List node used to associate this slice with a blkmap + * @blknr: Start block number of the mapping + * @blkcnt: Number of blocks covered by this mapping + */ +struct blkmap_slice { + struct list_head node; + + lbaint_t blknr; + lbaint_t blkcnt; + + /** + * @read: - Read from slice + * + * @read.bm: Blkmap to which this slice belongs + * @read.bms: This slice + * @read.blknr: Start block number to read from + * @read.blkcnt: Number of blocks to read + * @read.buffer: Buffer to store read data to + */ + ulong (*read)(struct blkmap *bm, struct blkmap_slice *bms, + lbaint_t blknr, lbaint_t blkcnt, void *buffer); + + /** + * @write: - Write to slice + * + * @write.bm: Blkmap to which this slice belongs + * @write.bms: This slice + * @write.blknr: Start block number to write to + * @write.blkcnt: Number of blocks to write + * @write.buffer: Data to be written + */ + ulong (*write)(struct blkmap *bm, struct blkmap_slice *bms, + lbaint_t blknr, lbaint_t blkcnt, const void *buffer); + + /** + * @destroy: - Tear down slice + * + * @read.bm: Blkmap to which this slice belongs + * @read.bms: This slice + */ + void (*destroy)(struct blkmap *bm, struct blkmap_slice *bms); +}; + +/** + * struct blkmap - Block map + * + * Data associated with a blkmap. + * + * @label: Human readable name of this blkmap + * @blk: Underlying block device + * @slices: List of slices associated with this blkmap + */ +struct blkmap { + char *label; + struct udevice *blk; + struct list_head slices; +}; + +static bool blkmap_slice_contains(struct blkmap_slice *bms, lbaint_t blknr) +{ + return (blknr >= bms->blknr) && (blknr < (bms->blknr + bms->blkcnt)); +} + +static bool blkmap_slice_available(struct blkmap *bm, struct blkmap_slice *new) +{ + struct blkmap_slice *bms; + lbaint_t first, last; + + first = new->blknr; + last = new->blknr + new->blkcnt - 1; + + list_for_each_entry(bms, &bm->slices, node) { + if (blkmap_slice_contains(bms, first) || + blkmap_slice_contains(bms, last) || + blkmap_slice_contains(new, bms->blknr) || + blkmap_slice_contains(new, bms->blknr + bms->blkcnt - 1)) + return false; + } + + return true; +} + +static int blkmap_slice_add(struct blkmap *bm, struct blkmap_slice *new) +{ + struct blk_desc *bd = dev_get_uclass_plat(bm->blk); + struct list_head *insert = &bm->slices; + struct blkmap_slice *bms; + + if (!blkmap_slice_available(bm, new)) + return -EBUSY; + + list_for_each_entry(bms, &bm->slices, node) { + if (bms->blknr < new->blknr) + continue; + + insert = &bms->node; + break; + } + + list_add_tail(&new->node, insert); + + /* Disk might have grown, update the size */ + bms = list_last_entry(&bm->slices, struct blkmap_slice, node); + bd->lba = bms->blknr + bms->blkcnt; + return 0; +} + +static ulong blkmap_blk_read_slice(struct blkmap *bm, struct blkmap_slice *bms, + lbaint_t blknr, lbaint_t blkcnt, + void *buffer) +{ + lbaint_t nr, cnt; + + nr = blknr - bms->blknr; + cnt = (blkcnt < bms->blkcnt) ? blkcnt : bms->blkcnt; + return bms->read(bm, bms, nr, cnt, buffer); +} + +static ulong blkmap_blk_read(struct udevice *dev, lbaint_t blknr, + lbaint_t blkcnt, void *buffer) +{ + struct blk_desc *bd = dev_get_uclass_plat(dev); + struct blkmap *bm = dev_get_plat(dev->parent); + struct blkmap_slice *bms; + lbaint_t cnt, total = 0; + + list_for_each_entry(bms, &bm->slices, node) { + if (!blkmap_slice_contains(bms, blknr)) + continue; + + cnt = blkmap_blk_read_slice(bm, bms, blknr, blkcnt, buffer); + blknr += cnt; + blkcnt -= cnt; + buffer += cnt << bd->log2blksz; + total += cnt; + } + + return total; +} + +static ulong blkmap_blk_write_slice(struct blkmap *bm, struct blkmap_slice *bms, + lbaint_t blknr, lbaint_t blkcnt, + const void *buffer) +{ + lbaint_t nr, cnt; + + nr = blknr - bms->blknr; + cnt = (blkcnt < bms->blkcnt) ? blkcnt : bms->blkcnt; + return bms->write(bm, bms, nr, cnt, buffer); +} + +static ulong blkmap_blk_write(struct udevice *dev, lbaint_t blknr, + lbaint_t blkcnt, const void *buffer) +{ + struct blk_desc *bd = dev_get_uclass_plat(dev); + struct blkmap *bm = dev_get_plat(dev->parent); + struct blkmap_slice *bms; + lbaint_t cnt, total = 0; + + list_for_each_entry(bms, &bm->slices, node) { + if (!blkmap_slice_contains(bms, blknr)) + continue; + + cnt = blkmap_blk_write_slice(bm, bms, blknr, blkcnt, buffer); + blknr += cnt; + blkcnt -= cnt; + buffer += cnt << bd->log2blksz; + total += cnt; + } + + return total; +} + +static const struct blk_ops blkmap_blk_ops = { + .read = blkmap_blk_read, + .write = blkmap_blk_write, +}; + +U_BOOT_DRIVER(blkmap_blk) = { + .name = "blkmap_blk", + .id = UCLASS_BLK, + .ops = &blkmap_blk_ops, +}; + +int blkmap_dev_bind(struct udevice *dev) +{ + struct blkmap *bm = dev_get_plat(dev); + struct blk_desc *bd; + int err; + + err = blk_create_devicef(dev, "blkmap_blk", "blk", UCLASS_BLKMAP, + dev_seq(dev), 512, 0, &bm->blk); + if (err) + return log_msg_ret("blk", err); + + INIT_LIST_HEAD(&bm->slices); + + bd = dev_get_uclass_plat(bm->blk); + snprintf(bd->vendor, BLK_VEN_SIZE, "U-Boot"); + snprintf(bd->product, BLK_PRD_SIZE, "blkmap"); + snprintf(bd->revision, BLK_REV_SIZE, "1.0"); + + /* EFI core isn't keen on zero-sized disks, so we lie. This is + * updated with the correct size once the user adds a + * mapping. + */ + bd->lba = 1; + + return 0; +} + +int blkmap_dev_unbind(struct udevice *dev) +{ + struct blkmap *bm = dev_get_plat(dev); + struct blkmap_slice *bms, *tmp; + int err; + + list_for_each_entry_safe(bms, tmp, &bm->slices, node) { + list_del(&bms->node); + free(bms); + } + + err = device_remove(bm->blk, DM_REMOVE_NORMAL); + if (err) + return err; + + return device_unbind(bm->blk); +} + +U_BOOT_DRIVER(blkmap_root) = { + .name = "blkmap_dev", + .id = UCLASS_BLKMAP, + .bind = blkmap_dev_bind, + .unbind = blkmap_dev_unbind, + .plat_auto = sizeof(struct blkmap), +}; + +struct udevice *blkmap_from_label(const char *label) +{ + struct udevice *dev; + struct uclass *uc; + struct blkmap *bm; + + uclass_id_foreach_dev(UCLASS_BLKMAP, dev, uc) { + bm = dev_get_plat(dev); + if (bm->label && !strcmp(label, bm->label)) + return dev; + } + + return NULL; +} + +int blkmap_create(const char *label, struct udevice **devp) +{ + char *hname, *hlabel; + struct udevice *dev; + struct blkmap *bm; + size_t namelen; + int err; + + dev = blkmap_from_label(label); + if (dev) { + err = -EBUSY; + goto err; + } + + hlabel = strdup(label); + if (!hlabel) { + err = -ENOMEM; + goto err; + } + + namelen = strlen("blkmap-") + strlen(label) + 1; + hname = malloc(namelen); + if (!hname) { + err = -ENOMEM; + goto err_free_hlabel; + } + + strlcpy(hname, "blkmap-", namelen); + strlcat(hname, label, namelen); + + err = device_bind_driver(dm_root(), "blkmap_dev", hname, &dev); + if (err) + goto err_free_hname; + + device_set_name_alloced(dev); + bm = dev_get_plat(dev); + bm->label = hlabel; + + if (devp) + *devp = dev; + + return 0; + +err_free_hname: + free(hname); +err_free_hlabel: + free(hlabel); +err: + return err; +} + +int blkmap_destroy(struct udevice *dev) +{ + int err; + + err = device_remove(dev, DM_REMOVE_NORMAL); + if (err) + return err; + + return device_unbind(dev); +} + +UCLASS_DRIVER(blkmap) = { + .id = UCLASS_BLKMAP, + .name = "blkmap", +}; diff --git a/include/blkmap.h b/include/blkmap.h new file mode 100644 index 0000000000..3c7e36efab --- /dev/null +++ b/include/blkmap.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Addiva Elektronik + * Author: Tobias Waldekranz + */ + +#ifndef _BLKMAP_H +#define _BLKMAP_H + +/** + * blkmap_from_label() - Find blkmap from label + * + * @label: Label of the requested blkmap + * Returns: A pointer to the blkmap on success, NULL on failure + */ +struct udevice *blkmap_from_label(const char *label); + +/** + * blkmap_create() - Create new blkmap + * + * @label: Label of the new blkmap + * @devp: If not NULL, updated with the address of the resulting device + * Returns: 0 on success, negative error code on failure + */ +int blkmap_create(const char *label, struct udevice **devp); + +/** + * blkmap_destroy() - Destroy blkmap + * + * @dev: The blkmap to be destroyed + * Returns: 0 on success, negative error code on failure + */ +int blkmap_destroy(struct udevice *dev); + +#endif /* _BLKMAP_H */ diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 33e43c20db..576237b954 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -37,6 +37,7 @@ enum uclass_id { UCLASS_AUDIO_CODEC, /* Audio codec with control and data path */ UCLASS_AXI, /* AXI bus */ UCLASS_BLK, /* Block device */ + UCLASS_BLKMAP, /* Composable virtual block device */ UCLASS_BOOTCOUNT, /* Bootcount backing store */ UCLASS_BOOTDEV, /* Boot device for locating an OS to boot */ UCLASS_BOOTMETH, /* Bootmethod for booting an OS */ From 15d9e99a274df5d9b260f75f42f7c394e5fe0e42 Mon Sep 17 00:00:00 2001 From: Tobias Waldekranz Date: Thu, 16 Feb 2023 16:33:50 +0100 Subject: [PATCH 070/805] blk: blkmap: Add memory mapping support Allow a slice of RAM to be mapped to a blkmap. This means that RAM can now be accessed as if it was a block device, meaning that existing filesystem drivers can now be used to access ramdisks. Signed-off-by: Tobias Waldekranz Reviewed-by: Simon Glass --- drivers/block/blkmap.c | 105 +++++++++++++++++++++++++++++++++++++++++ include/blkmap.h | 29 ++++++++++++ 2 files changed, 134 insertions(+) diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c index acfc002ceb..6d6eed889e 100644 --- a/drivers/block/blkmap.c +++ b/drivers/block/blkmap.c @@ -130,6 +130,111 @@ static int blkmap_slice_add(struct blkmap *bm, struct blkmap_slice *new) return 0; } +/** + * struct blkmap_mem - Memory mapping + * + * @slice: Common map data + * @addr: Target memory region of this mapping + * @remapped: True if @addr is backed by a physical to virtual memory + * mapping that must be torn down at the end of this mapping's + * lifetime. + */ +struct blkmap_mem { + struct blkmap_slice slice; + void *addr; + bool remapped; +}; + +static ulong blkmap_mem_read(struct blkmap *bm, struct blkmap_slice *bms, + lbaint_t blknr, lbaint_t blkcnt, void *buffer) +{ + struct blkmap_mem *bmm = container_of(bms, struct blkmap_mem, slice); + struct blk_desc *bd = dev_get_uclass_plat(bm->blk); + char *src; + + src = bmm->addr + (blknr << bd->log2blksz); + memcpy(buffer, src, blkcnt << bd->log2blksz); + return blkcnt; +} + +static ulong blkmap_mem_write(struct blkmap *bm, struct blkmap_slice *bms, + lbaint_t blknr, lbaint_t blkcnt, + const void *buffer) +{ + struct blkmap_mem *bmm = container_of(bms, struct blkmap_mem, slice); + struct blk_desc *bd = dev_get_uclass_plat(bm->blk); + char *dst; + + dst = bmm->addr + (blknr << bd->log2blksz); + memcpy(dst, buffer, blkcnt << bd->log2blksz); + return blkcnt; +} + +static void blkmap_mem_destroy(struct blkmap *bm, struct blkmap_slice *bms) +{ + struct blkmap_mem *bmm = container_of(bms, struct blkmap_mem, slice); + + if (bmm->remapped) + unmap_sysmem(bmm->addr); +} + +int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + void *addr, bool remapped) +{ + struct blkmap *bm = dev_get_plat(dev); + struct blkmap_mem *bmm; + int err; + + bmm = malloc(sizeof(*bmm)); + if (!bmm) + return -ENOMEM; + + *bmm = (struct blkmap_mem) { + .slice = { + .blknr = blknr, + .blkcnt = blkcnt, + + .read = blkmap_mem_read, + .write = blkmap_mem_write, + .destroy = blkmap_mem_destroy, + }, + + .addr = addr, + .remapped = remapped, + }; + + err = blkmap_slice_add(bm, &bmm->slice); + if (err) + free(bmm); + + return err; +} + +int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + void *addr) +{ + return __blkmap_map_mem(dev, blknr, blkcnt, addr, false); +} + +int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + phys_addr_t paddr) +{ + struct blkmap *bm = dev_get_plat(dev); + struct blk_desc *bd = dev_get_uclass_plat(bm->blk); + void *addr; + int err; + + addr = map_sysmem(paddr, blkcnt << bd->log2blksz); + if (!addr) + return -ENOMEM; + + err = __blkmap_map_mem(dev, blknr, blkcnt, addr, true); + if (err) + unmap_sysmem(addr); + + return err; +} + static ulong blkmap_blk_read_slice(struct blkmap *bm, struct blkmap_slice *bms, lbaint_t blknr, lbaint_t blkcnt, void *buffer) diff --git a/include/blkmap.h b/include/blkmap.h index 3c7e36efab..74baeb19f8 100644 --- a/include/blkmap.h +++ b/include/blkmap.h @@ -7,6 +7,35 @@ #ifndef _BLKMAP_H #define _BLKMAP_H +/** + * blkmap_map_mem() - Map region of memory + * + * @dev: Blkmap to create the mapping on + * @blknr: Start block number of the mapping + * @blkcnt: Number of blocks to map + * @addr: The target memory address of the mapping + * Returns: 0 on success, negative error code on failure + */ +int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + void *addr); + +/** + * blkmap_map_pmem() - Map region of physical memory + * + * Ensures that a valid physical to virtual memory mapping for the + * requested region is valid for the lifetime of the mapping, on + * architectures that require it (sandbox). + * + * @dev: Blkmap to create the mapping on + * @blknr: Start block number of the mapping + * @blkcnt: Number of blocks to map + * @paddr: The target physical memory address of the mapping + * Returns: 0 on success, negative error code on failure + */ +int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + phys_addr_t paddr); + + /** * blkmap_from_label() - Find blkmap from label * From 762dc78bdea3468e8cd35c01f91def13974948f1 Mon Sep 17 00:00:00 2001 From: Tobias Waldekranz Date: Thu, 16 Feb 2023 16:33:51 +0100 Subject: [PATCH 071/805] blk: blkmap: Add linear device mapping support Allow a slice of an existing block device to be mapped to a blkmap. This means that filesystems that are not stored at exact partition boundaries can be accessed by remapping a slice of the existing device to a blkmap device. Signed-off-by: Tobias Waldekranz Reviewed-by: Simon Glass --- drivers/block/blkmap.c | 71 ++++++++++++++++++++++++++++++++++++++++++ include/blkmap.h | 13 ++++++++ 2 files changed, 84 insertions(+) diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c index 6d6eed889e..2bb0acc20f 100644 --- a/drivers/block/blkmap.c +++ b/drivers/block/blkmap.c @@ -130,6 +130,77 @@ static int blkmap_slice_add(struct blkmap *bm, struct blkmap_slice *new) return 0; } +/** + * struct blkmap_linear - Linear mapping to other block device + * + * @slice: Common map data + * @blk: Target block device of this mapping + * @blknr: Start block number of the target device + */ +struct blkmap_linear { + struct blkmap_slice slice; + + struct udevice *blk; + lbaint_t blknr; +}; + +static ulong blkmap_linear_read(struct blkmap *bm, struct blkmap_slice *bms, + lbaint_t blknr, lbaint_t blkcnt, void *buffer) +{ + struct blkmap_linear *bml = container_of(bms, struct blkmap_linear, slice); + + return blk_read(bml->blk, bml->blknr + blknr, blkcnt, buffer); +} + +static ulong blkmap_linear_write(struct blkmap *bm, struct blkmap_slice *bms, + lbaint_t blknr, lbaint_t blkcnt, + const void *buffer) +{ + struct blkmap_linear *bml = container_of(bms, struct blkmap_linear, slice); + + return blk_write(bml->blk, bml->blknr + blknr, blkcnt, buffer); +} + +int blkmap_map_linear(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + struct udevice *lblk, lbaint_t lblknr) +{ + struct blkmap *bm = dev_get_plat(dev); + struct blkmap_linear *linear; + struct blk_desc *bd, *lbd; + int err; + + bd = dev_get_uclass_plat(bm->blk); + lbd = dev_get_uclass_plat(lblk); + if (lbd->blksz != bd->blksz) + /* We could support block size translation, but we + * don't yet. + */ + return -EINVAL; + + linear = malloc(sizeof(*linear)); + if (!linear) + return -ENOMEM; + + *linear = (struct blkmap_linear) { + .slice = { + .blknr = blknr, + .blkcnt = blkcnt, + + .read = blkmap_linear_read, + .write = blkmap_linear_write, + }, + + .blk = lblk, + .blknr = lblknr, + }; + + err = blkmap_slice_add(bm, &linear->slice); + if (err) + free(linear); + + return err; +} + /** * struct blkmap_mem - Memory mapping * diff --git a/include/blkmap.h b/include/blkmap.h index 74baeb19f8..af54583c7d 100644 --- a/include/blkmap.h +++ b/include/blkmap.h @@ -7,6 +7,19 @@ #ifndef _BLKMAP_H #define _BLKMAP_H +/** + * blkmap_map_linear() - Map region of other block device + * + * @dev: Blkmap to create the mapping on + * @blknr: Start block number of the mapping + * @blkcnt: Number of blocks to map + * @lblk: The target block device of the mapping + * @lblknr: The start block number of the target device + * Returns: 0 on success, negative error code on failure + */ +int blkmap_map_linear(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + struct udevice *lblk, lbaint_t lblknr); + /** * blkmap_map_mem() - Map region of memory * From bb56da117fe608f4da2a62eb93c4457b2f485c72 Mon Sep 17 00:00:00 2001 From: Tobias Waldekranz Date: Thu, 16 Feb 2023 16:33:52 +0100 Subject: [PATCH 072/805] cmd: blkmap: Add blkmap command Add a frontend for the blkmap subsystem. In addition to the common block device operations, this allows users to create and destroy devices, and map in memory and slices of other block devices. With that we support two primary use-cases: - Being able to "distro boot" from a RAM disk. I.e., from an image where the kernel is stored in /boot of some filesystem supported by U-Boot. - Accessing filesystems not located on exact partition boundaries, e.g. when a filesystem image is wrapped in an FIT image and stored in a disk partition. Signed-off-by: Tobias Waldekranz Reviewed-by: Simon Glass --- MAINTAINERS | 1 + cmd/Kconfig | 19 +++++ cmd/Makefile | 1 + cmd/blkmap.c | 233 +++++++++++++++++++++++++++++++++++++++++++++++++++ disk/part.c | 1 + 5 files changed, 255 insertions(+) create mode 100644 cmd/blkmap.c diff --git a/MAINTAINERS b/MAINTAINERS index 8c1305e8a1..e0a1f8cbc9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -796,6 +796,7 @@ F: tools/binman/ BLKMAP M: Tobias Waldekranz S: Maintained +F: cmd/blkmap.c F: drivers/block/blkmap.c F: include/blkmap.h diff --git a/cmd/Kconfig b/cmd/Kconfig index 8c9b430f99..bab35fc667 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1980,6 +1980,25 @@ config CMD_BLOCK_CACHE during development, but also allows the cache to be disabled when it might hurt performance (e.g. when using the ums command). +config CMD_BLKMAP + bool "blkmap - Composable virtual block devices" + depends on BLKMAP + default y if BLKMAP + help + Create virtual block devices that are backed by various sources, + e.g. RAM, or parts of an existing block device. Though much more + rudimentary, it borrows a lot of ideas from Linux's device mapper + subsystem. + + Example use-cases: + - Treat a region of RAM as a block device, i.e. a RAM disk. This let's + you extract files from filesystem images stored in RAM (perhaps as a + result of a TFTP transfer). + - Create a virtual partition on an existing device. This let's you + access filesystems that aren't stored at an exact partition + boundary. A common example is a filesystem image embedded in an FIT + image. + config CMD_BUTTON bool "button" depends on BUTTON diff --git a/cmd/Makefile b/cmd/Makefile index e032091621..054ef42017 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_CMD_BCB) += bcb.o obj-$(CONFIG_CMD_BDI) += bdinfo.o obj-$(CONFIG_CMD_BIND) += bind.o obj-$(CONFIG_CMD_BINOP) += binop.o +obj-$(CONFIG_CMD_BLKMAP) += blkmap.o obj-$(CONFIG_CMD_BLOBLIST) += bloblist.o obj-$(CONFIG_CMD_BLOCK_CACHE) += blkcache.o obj-$(CONFIG_CMD_BMP) += bmp.o diff --git a/cmd/blkmap.c b/cmd/blkmap.c new file mode 100644 index 0000000000..b34c013072 --- /dev/null +++ b/cmd/blkmap.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Addiva Elektronik + * Author: Tobias Waldekranz + */ + +#include +#include +#include +#include +#include +#include + +static int blkmap_curr_dev; + +struct map_ctx { + struct udevice *dev; + lbaint_t blknr, blkcnt; +}; + +typedef int (*map_parser_fn)(struct map_ctx *ctx, int argc, char *const argv[]); + +struct map_handler { + const char *name; + map_parser_fn fn; +}; + +int do_blkmap_map_linear(struct map_ctx *ctx, int argc, char *const argv[]) +{ + struct blk_desc *lbd; + int err, ldevnum; + lbaint_t lblknr; + + if (argc < 4) + return CMD_RET_USAGE; + + ldevnum = dectoul(argv[2], NULL); + lblknr = dectoul(argv[3], NULL); + + lbd = blk_get_devnum_by_uclass_idname(argv[1], ldevnum); + if (!lbd) { + printf("Found no device matching \"%s %d\"\n", + argv[1], ldevnum); + return CMD_RET_FAILURE; + } + + err = blkmap_map_linear(ctx->dev, ctx->blknr, ctx->blkcnt, + lbd->bdev, lblknr); + if (err) { + printf("Unable to map \"%s %d\" at block 0x" LBAF ": %d\n", + argv[1], ldevnum, ctx->blknr, err); + + return CMD_RET_FAILURE; + } + + printf("Block 0x" LBAF "+0x" LBAF " mapped to block 0x" LBAF " of \"%s %d\"\n", + ctx->blknr, ctx->blkcnt, lblknr, argv[1], ldevnum); + return CMD_RET_SUCCESS; +} + +int do_blkmap_map_mem(struct map_ctx *ctx, int argc, char *const argv[]) +{ + phys_addr_t addr; + int err; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = hextoul(argv[1], NULL); + + err = blkmap_map_pmem(ctx->dev, ctx->blknr, ctx->blkcnt, addr); + if (err) { + printf("Unable to map %#llx at block 0x" LBAF ": %d\n", + (unsigned long long)addr, ctx->blknr, err); + return CMD_RET_FAILURE; + } + + printf("Block 0x" LBAF "+0x" LBAF " mapped to %#llx\n", + ctx->blknr, ctx->blkcnt, (unsigned long long)addr); + return CMD_RET_SUCCESS; +} + +struct map_handler map_handlers[] = { + { .name = "linear", .fn = do_blkmap_map_linear }, + { .name = "mem", .fn = do_blkmap_map_mem }, + + { .name = NULL } +}; + +static int do_blkmap_map(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + struct map_handler *handler; + struct map_ctx ctx; + + if (argc < 5) + return CMD_RET_USAGE; + + ctx.dev = blkmap_from_label(argv[1]); + if (!ctx.dev) { + printf("\"%s\" is not the name of any known blkmap\n", argv[1]); + return CMD_RET_FAILURE; + } + + ctx.blknr = hextoul(argv[2], NULL); + ctx.blkcnt = hextoul(argv[3], NULL); + argc -= 4; + argv += 4; + + for (handler = map_handlers; handler->name; handler++) { + if (!strcmp(handler->name, argv[0])) + return handler->fn(&ctx, argc, argv); + } + + printf("Unknown map type \"%s\"\n", argv[0]); + return CMD_RET_USAGE; +} + +static int do_blkmap_create(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + const char *label; + int err; + + if (argc != 2) + return CMD_RET_USAGE; + + label = argv[1]; + + err = blkmap_create(label, NULL); + if (err) { + printf("Unable to create \"%s\": %d\n", label, err); + return CMD_RET_FAILURE; + } + + printf("Created \"%s\"\n", label); + return CMD_RET_SUCCESS; +} + +static int do_blkmap_destroy(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + struct udevice *dev; + const char *label; + int err; + + if (argc != 2) + return CMD_RET_USAGE; + + label = argv[1]; + + dev = blkmap_from_label(label); + if (!dev) { + printf("\"%s\" is not the name of any known blkmap\n", label); + return CMD_RET_FAILURE; + } + + err = blkmap_destroy(dev); + if (err) { + printf("Unable to destroy \"%s\": %d\n", label, err); + return CMD_RET_FAILURE; + } + + printf("Destroyed \"%s\"\n", label); + return CMD_RET_SUCCESS; +} + +static int do_blkmap_get(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + struct udevice *dev; + const char *label; + int err; + + if (argc < 3) + return CMD_RET_USAGE; + + label = argv[1]; + + dev = blkmap_from_label(label); + if (!dev) { + printf("\"%s\" is not the name of any known blkmap\n", label); + return CMD_RET_FAILURE; + } + + if (!strcmp(argv[2], "dev")) { + if (argc == 3) { + printf("%d\n", dev_seq(dev)); + } else { + err = env_set_hex(argv[3], dev_seq(dev)); + if (err) + return CMD_RET_FAILURE; + } + } else { + return CMD_RET_USAGE; + } + + return CMD_RET_SUCCESS; +} + +static int do_blkmap_common(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + /* The subcommand parsing pops the original argv[0] ("blkmap") + * which blk_common_cmd expects. Push it back again. + */ + argc++; + argv--; + + return blk_common_cmd(argc, argv, UCLASS_BLKMAP, &blkmap_curr_dev); +} + +U_BOOT_CMD_WITH_SUBCMDS( + blkmap, "Composeable virtual block devices", + "info - list configured devices\n" + "blkmap part - list available partitions on current blkmap device\n" + "blkmap dev [] - show or set current blkmap device\n" + "blkmap read \n" + "blkmap write \n" + "blkmap get