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armv8: ls1028a: Updated serdes configuration for 0x13BB

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In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2

Fixes: 36f50b7523 ("armv8: ls1028a: Add other serdes
		     protocal support")

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Hou Zhiqiang 2019-09-04 06:25:44 +00:00 committed by Priyanka Jain
parent c9ba88bafc
commit 116f75c7b3
1 changed files with 1 additions and 1 deletions
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arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
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@ -24,7 +24,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} }, {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
{0xE031, {SXGMII1, QXGMII2, NONE, SATA1} }, {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} },
{0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} }, {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} },
{0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} }, {0xBB31, {SXGMII1, QXGMII2, PCIE2, PCIE1} },
{0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} }, {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} },
{0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} }, {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} },
{0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} }, {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} },