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https://github.com/AsahiLinux/u-boot
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imx: imx8ulp: reserve tee memory
The TEE memory should be reserved when TEE is present, so need to runtime update dram bank and memory information according to tee present or not. Signed-off-by: Ji Luo <ji.luo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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112b777849
1 changed files with 100 additions and 2 deletions
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@ -413,6 +413,17 @@ static struct mm_region imx8ulp_arm64_mem_map[] = {
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struct mm_region *mem_map = imx8ulp_arm64_mem_map;
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static unsigned int imx8ulp_find_dram_entry_in_mem_map(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
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if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
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return i;
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hang(); /* Entry not found, this must never happen. */
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}
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/* simplify the page table size to enhance boot speed */
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#define MAX_PTE_ENTRIES 512
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#define MAX_MEM_MAP_REGIONS 16
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@ -444,19 +455,106 @@ u64 get_page_table_size(void)
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void enable_caches(void)
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{
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/* TODO: add TEE memmap region */
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/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
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if (rom_pointer[1]) {
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/*
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* TEE are loaded, So the ddr bank structures
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* have been modified update mmu table accordingly
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*/
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int i = 0;
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int entry = imx8ulp_find_dram_entry_in_mem_map();
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u64 attrs = imx8ulp_arm64_mem_map[entry].attrs;
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while (i < CONFIG_NR_DRAM_BANKS &&
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entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) {
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if (gd->bd->bi_dram[i].start == 0)
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break;
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imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start;
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imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start;
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imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size;
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imx8ulp_arm64_mem_map[entry].attrs = attrs;
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debug("Added memory mapping (%d): %llx %llx\n", entry,
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imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size);
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i++; entry++;
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}
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}
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icache_enable();
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dcache_enable();
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}
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__weak int board_phys_sdram_size(phys_size_t *size)
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{
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if (!size)
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return -EINVAL;
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*size = PHYS_SDRAM_SIZE;
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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unsigned int entry = imx8ulp_find_dram_entry_in_mem_map();
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phys_size_t sdram_size;
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int ret;
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ret = board_phys_sdram_size(&sdram_size);
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if (ret)
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return ret;
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/* rom_pointer[1] contains the size of TEE occupies */
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if (rom_pointer[1])
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gd->ram_size = sdram_size - rom_pointer[1];
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else
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gd->ram_size = sdram_size;
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/* also update the SDRAM size in the mem_map used externally */
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imx8ulp_arm64_mem_map[entry].size = sdram_size;
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return 0;
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}
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int dram_init_banksize(void)
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{
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int bank = 0;
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int ret;
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phys_size_t sdram_size;
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ret = board_phys_sdram_size(&sdram_size);
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if (ret)
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return ret;
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gd->bd->bi_dram[bank].start = PHYS_SDRAM;
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if (rom_pointer[1]) {
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phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
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phys_size_t optee_size = (size_t)rom_pointer[1];
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gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
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if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
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if (++bank >= CONFIG_NR_DRAM_BANKS) {
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puts("CONFIG_NR_DRAM_BANKS is not enough\n");
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return -1;
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}
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gd->bd->bi_dram[bank].start = optee_start + optee_size;
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gd->bd->bi_dram[bank].size = PHYS_SDRAM +
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sdram_size - gd->bd->bi_dram[bank].start;
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}
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} else {
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gd->bd->bi_dram[bank].size = sdram_size;
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}
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return 0;
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}
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phys_size_t get_effective_memsize(void)
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{
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/* return the first bank as effective memory */
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if (rom_pointer[1])
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return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
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return gd->ram_size;
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}
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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