mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
powerpc: remove RPXsuper board support
Enough time has passed since this board was moved to Orphan. Remove. - Remove board/rpxsuper/* - Remove include/configs/RPXsuper.h - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
4fb3925ff8
commit
0ebf5f5c12
9 changed files with 1 additions and 1377 deletions
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := rpxsuper.o flash.o mii_phy.o
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@ -1,416 +0,0 @@
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/*
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* (C) Copyright 2000
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* Marius Groeger <mgroeger@sysgo.de>
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Flash Routines for AMD 29F080B devices
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* Added support for 64bit and AMD 29DL323B
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*
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*--------------------------------------------------------------------
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <asm/io.h>
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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#define RD_SWP32(x) in_le32((volatile u32*)x)
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info);
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static int write_word (flash_info_t *info, ulong dest, ulong data);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init(void)
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{
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int i;
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/* Init: no FLASHes known */
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
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flash_info[i].flash_id = FLASH_UNKNOWN;
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/* for now, only support the 4 MB Flash SIMM */
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(void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE,
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&flash_info[0]);
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/*
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* protect monitor and environment sectors
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*/
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[0]);
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#endif
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#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
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#ifndef CONFIG_ENV_SIZE
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#endif
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
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#endif
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return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024;
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case (AMD_MANUFACT & FLASH_VENDMASK):
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printf ("AMD ");
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break;
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case (FUJ_MANUFACT & FLASH_VENDMASK):
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printf ("FUJITSU ");
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break;
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case (SST_MANUFACT & FLASH_VENDMASK):
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printf ("SST ");
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break;
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default:
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printf ("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case (AMD_ID_DL323B & FLASH_TYPEMASK):
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printf("AM29DL323B (32 MBit)\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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if ((i % 5) == 0) printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " "
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);
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}
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printf ("\n");
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return;
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}
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/*
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* The following code cannot be run from FLASH!
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*/
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static ulong flash_get_size (vu_long *addr, flash_info_t *info)
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{
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short i;
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vu_long vendor[2], devid[2];
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ulong base = (ulong)addr;
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/* Reset and Write auto select command: read Manufacturer ID */
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addr[0] = 0xf0f0f0f0;
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addr[2 * 0x0555] = 0xAAAAAAAA;
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addr[2 * 0x02AA] = 0x55555555;
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addr[2 * 0x0555] = 0x90909090;
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addr[1] = 0xf0f0f0f0;
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addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
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addr[2 * 0x02AA + 1] = 0x55555555;
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addr[2 * 0x0555 + 1] = 0x90909090;
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udelay (1000);
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vendor[0] = RD_SWP32(&addr[0]);
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vendor[1] = RD_SWP32(&addr[1]);
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if (vendor[0] != vendor[1] || vendor[0] != AMD_MANUFACT) {
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info->size = 0;
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goto out;
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}
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devid[0] = RD_SWP32(&addr[2]);
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devid[1] = RD_SWP32(&addr[3]);
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if (devid[0] == AMD_ID_DL323B) {
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/*
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* we have 2 Banks
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* Bank 1 (23 Sectors): 0-7=8kbyte, 8-22=64kbyte
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* Bank 2 (48 Sectors): 23-70=64kbyte
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*/
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info->flash_id = (AMD_MANUFACT & FLASH_VENDMASK) |
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(AMD_ID_DL323B & FLASH_TYPEMASK);
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info->sector_count = 71;
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info->size = 4 * (8 * 8 + 63 * 64) * 1024;
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}
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else {
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info->size = 0;
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goto out;
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}
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/* set up sector start address table */
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for (i = 0; i < 8; i++) {
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info->start[i] = base + (i * 0x8000);
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}
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for (i = 8; i < info->sector_count; i++) {
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info->start[i] = base + (i * 0x40000) + 8 * 0x8000 - 8 * 0x40000;
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}
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/* check for protected sectors */
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for (i = 0; i < info->sector_count; i++) {
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/* read sector protection at sector address */
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addr = (volatile unsigned long *)(info->start[i]);
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addr[2 * 0x0555] = 0xAAAAAAAA;
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addr[2 * 0x02AA] = 0x55555555;
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addr[2 * 0x0555] = 0x90909090;
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addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
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addr[2 * 0x02AA + 1] = 0x55555555;
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addr[2 * 0x0555 + 1] = 0x90909090;
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udelay (1000);
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base = RD_SWP32(&addr[4]);
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base |= RD_SWP32(&addr[5]);
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info->protect[i] = base & 0x00010001 ? 1 : 0;
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}
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addr = (vu_long*)info->start[0];
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out:
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/* reset command */
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addr[0] = 0xf0f0f0f0;
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addr[1] = 0xf0f0f0f0;
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return info->size;
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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vu_long *addr = (vu_long*)(info->start[0]);
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int flag, prot, sect, l_sect;
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ulong start, now, last;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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prot = 0;
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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l_sect = -1;
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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addr[2 * 0x0555] = 0xAAAAAAAA;
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addr[2 * 0x02AA] = 0x55555555;
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addr[2 * 0x0555] = 0x80808080;
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addr[2 * 0x0555] = 0xAAAAAAAA;
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addr[2 * 0x02AA] = 0x55555555;
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addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
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addr[2 * 0x02AA + 1] = 0x55555555;
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addr[2 * 0x0555 + 1] = 0x80808080;
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addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
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addr[2 * 0x02AA + 1] = 0x55555555;
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udelay (100);
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect<=s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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addr = (vu_long*)(info->start[sect]);
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addr[0] = 0x30303030;
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addr[1] = 0x30303030;
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l_sect = sect;
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}
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}
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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/* wait at least 80us - let's wait 1 ms */
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udelay (1000);
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/*
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* We wait for the last triggered sector
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*/
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if (l_sect < 0)
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goto DONE;
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start = get_timer (0);
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last = start;
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addr = (vu_long*)(info->start[l_sect]);
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while ( (addr[0] & 0x80808080) != 0x80808080 ||
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(addr[1] & 0x80808080) != 0x80808080) {
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if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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return 1;
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}
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/* show that we're waiting */
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if ((now - last) > 1000) { /* every second */
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serial_putc ('.');
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last = now;
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}
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}
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DONE:
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/* reset to read mode */
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addr = (volatile unsigned long *)info->start[0];
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addr[0] = 0xF0F0F0F0; /* reset bank */
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addr[1] = 0xF0F0F0F0; /* reset bank */
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printf (" done\n");
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return 0;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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{
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ulong cp, wp, data;
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int i, l, rc;
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wp = (addr & ~3); /* get lower word aligned address */
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/*
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* handle unaligned start bytes
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*/
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if ((l = addr - wp) != 0) {
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data = 0;
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for (i=0, cp=wp; i<l; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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for (; i<4 && cnt>0; ++i) {
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data = (data << 8) | *src++;
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--cnt;
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++cp;
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}
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for (; cnt==0 && i<4; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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if ((rc = write_word(info, wp, data)) != 0) {
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return (rc);
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}
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wp += 4;
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}
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/*
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* handle word aligned part
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*/
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while (cnt >= 4) {
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data = 0;
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for (i=0; i<4; ++i) {
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data = (data << 8) | *src++;
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}
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if ((rc = write_word(info, wp, data)) != 0) {
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return (rc);
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}
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wp += 4;
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cnt -= 4;
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}
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if (cnt == 0) {
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return (0);
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}
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/*
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* handle unaligned tail bytes
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*/
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data = 0;
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for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
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data = (data << 8) | *src++;
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--cnt;
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}
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for (; i<4; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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return (write_word(info, wp, data));
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}
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/*-----------------------------------------------------------------------
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* Write a word to Flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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static int write_word (flash_info_t *info, ulong dest, ulong data)
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{
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vu_long *addr = (vu_long*)(info->start[0]);
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ulong start;
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int flag;
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/* Check if Flash is (sufficiently) erased */
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if ((*((vu_long *)dest) & data) != data) {
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return (2);
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}
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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if ((dest & 0x00000004) == 0) {
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addr[2 * 0x0555] = 0xAAAAAAAA;
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addr[2 * 0x02AA] = 0x55555555;
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addr[2 * 0x0555] = 0xA0A0A0A0;
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}
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else {
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addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
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addr[2 * 0x02AA + 1] = 0x55555555;
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addr[2 * 0x0555 + 1] = 0xA0A0A0A0;
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}
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|
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*((vu_long *)dest) = data;
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|
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/* re-enable interrupts if necessary */
|
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if (flag)
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enable_interrupts();
|
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|
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/* data polling for D7 */
|
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start = get_timer (0);
|
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while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
|
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if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
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return (1);
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}
|
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}
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return (0);
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}
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|
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/*-----------------------------------------------------------------------
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*/
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|
|
@ -1,107 +0,0 @@
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#include <common.h>
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#include <mii_phy.h>
|
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#include "rpxsuper.h"
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|
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#define MII_MDIO 0x01
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#define MII_MDCK 0x02
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#define MII_MDIR 0x04
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|
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void
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mii_discover_phy(void)
|
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{
|
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int known;
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unsigned short phy_reg;
|
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unsigned long phy_id;
|
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|
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known = 0;
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printf("Discovering phy @ 0: ");
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phy_id = mii_phy_read(2) << 16;
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phy_id |= mii_phy_read(3);
|
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if ((phy_id & 0xFFFFFC00) == 0x00137800) {
|
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printf("Level One ");
|
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if ((phy_id & 0x000003F0) == 0xE0) {
|
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printf("LXT971A Revision %d\n", (int)(phy_id & 0xF));
|
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known = 1;
|
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}
|
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else printf("unknown type\n");
|
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}
|
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else printf("unknown OUI = 0x%08lX\n", phy_id);
|
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|
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phy_reg = mii_phy_read(1);
|
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if (!(phy_reg & 0x0004)) printf("Link is down\n");
|
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if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n");
|
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if (phy_reg & 0x0002) printf("Jabber condition detected\n");
|
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if (phy_reg & 0x0010) printf("Remote fault condition detected \n");
|
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|
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if (known) {
|
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phy_reg = mii_phy_read(17);
|
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if (phy_reg & 0x0400)
|
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printf("Phy operating at %d MBit/s in %s-duplex mode\n",
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phy_reg & 0x4000 ? 100 : 10,
|
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phy_reg & 0x0200 ? "full" : "half");
|
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else
|
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printf("bad link!!\n");
|
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/*
|
||||
left off: no link, green 100MBit, yellow 10MBit
|
||||
right off: no activity, green full-duplex, yellow half-duplex
|
||||
*/
|
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mii_phy_write(20, 0x0452);
|
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}
|
||||
}
|
||||
|
||||
unsigned short
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mii_phy_read(unsigned short reg)
|
||||
{
|
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int i;
|
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unsigned short tmp, val = 0, adr = 0;
|
||||
t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
|
||||
|
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tmp = 0x6002 | (adr << 7) | (reg << 2);
|
||||
regs->bcsr4 = 0xC3;
|
||||
for (i = 0; i < 64; i++) {
|
||||
regs->bcsr4 ^= MII_MDCK;
|
||||
}
|
||||
for (i = 0; i < 16; i++) {
|
||||
regs->bcsr4 &= ~MII_MDCK;
|
||||
if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
|
||||
else regs->bcsr4 &= ~MII_MDIO;
|
||||
regs->bcsr4 |= MII_MDCK;
|
||||
tmp <<= 1;
|
||||
}
|
||||
regs->bcsr4 |= MII_MDIR;
|
||||
for (i = 0; i < 16; i++) {
|
||||
val <<= 1;
|
||||
regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK);
|
||||
if (regs->bcsr4 & MII_MDIO) val |= 1;
|
||||
regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK);
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
void
|
||||
mii_phy_write(unsigned short reg, unsigned short val)
|
||||
{
|
||||
int i;
|
||||
unsigned short tmp, adr = 0;
|
||||
t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
|
||||
|
||||
tmp = 0x5002 | (adr << 7) | (reg << 2);
|
||||
regs->bcsr4 = 0xC3;
|
||||
for (i = 0; i < 64; i++) {
|
||||
regs->bcsr4 ^= MII_MDCK;
|
||||
}
|
||||
for (i = 0; i < 16; i++) {
|
||||
regs->bcsr4 &= ~MII_MDCK;
|
||||
if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
|
||||
else regs->bcsr4 &= ~MII_MDIO;
|
||||
regs->bcsr4 |= MII_MDCK;
|
||||
tmp <<= 1;
|
||||
}
|
||||
for (i = 0; i < 16; i++) {
|
||||
regs->bcsr4 &= ~MII_MDCK;
|
||||
if (val & 0x8000) regs->bcsr4 |= MII_MDIO;
|
||||
else regs->bcsr4 &= ~MII_MDIO;
|
||||
regs->bcsr4 |= MII_MDCK;
|
||||
val <<= 1;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
Hi,
|
||||
|
||||
so this is the port to the Embedded Planet RPX Super Board.
|
||||
|
||||
ATTENTION
|
||||
This code is only tested on the AY-Version, which is an early release with some
|
||||
hardware bugs. The main problem is that this board uses the default Hard Reset
|
||||
Configuration Word and not the 4 bytes located at start of FLASH because at
|
||||
0xFE000000 is no FLASH. The FLASH consists out of 4 chips each 16bits wide. Be
|
||||
carefull, the bytes are swapped. So DQ0-7 is the high byte, DQ8-15 ist the low
|
||||
byte.
|
||||
|
||||
The icache can only manually be enabled after reset.
|
||||
The FLASH and main SDRAM is working with icache enabled.
|
||||
The local SDRAM can only be used as data memory when icache is enabled.
|
||||
If U-Boot runs in local SDRAM, TFTP does not work.
|
||||
The functions in mii_phy.c are all working. Call mii_phy_discover() out of
|
||||
eth_init() and solve the linker error.
|
||||
I2C, RTC/NVRAM and PCMCIA are not working yet.
|
||||
|
||||
TODO
|
||||
The 32MB local SDRAM is working but not shown in the startup messages of
|
||||
U-Boot. If you locate U-Boot or any other program to this area it won't run.
|
||||
Turning the ichache off does not solve this problem.
|
||||
|
||||
As I won't buy another RPX Super there might be some little work to do for you
|
||||
getting this U-Boot port running on the final board.
|
||||
|
||||
|
||||
frank.morauf@salzbrenner.com
|
||||
|
|
@ -1,289 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2001
|
||||
* Advent Networks, Inc. <http://www.adventnetworks.com>
|
||||
* Jay Monkman <jtm@smoothsmoothie.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ioports.h>
|
||||
#include <mpc8260.h>
|
||||
#include "rpxsuper.h"
|
||||
|
||||
/*
|
||||
* I/O Port configuration table
|
||||
*
|
||||
* if conf is 1, then that port pin will be configured at boot time
|
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry
|
||||
*/
|
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = {
|
||||
|
||||
/* Port A configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PA31 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */
|
||||
/* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */
|
||||
/* PA29 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */
|
||||
/* PA28 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */
|
||||
/* PA27 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */
|
||||
/* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */
|
||||
/* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */
|
||||
/* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */
|
||||
/* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */
|
||||
/* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */
|
||||
/* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */
|
||||
/* PA20 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */
|
||||
/* PA19 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */
|
||||
/* PA18 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */
|
||||
/* PA17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
|
||||
/* PA16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
|
||||
/* PA15 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
|
||||
/* PA14 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
|
||||
/* PA13 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
|
||||
/* PA12 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
|
||||
/* PA11 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
|
||||
/* PA10 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
|
||||
/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
|
||||
/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
|
||||
/* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* PA7 */
|
||||
/* PA6 */ { 1, 0, 0, 0, 0, 0 }, /* PA6 */
|
||||
/* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* PA5 */
|
||||
/* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* PA4 */
|
||||
/* PA3 */ { 1, 0, 0, 0, 0, 0 }, /* PA3 */
|
||||
/* PA2 */ { 1, 0, 0, 0, 0, 0 }, /* PA2 */
|
||||
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* PA1 */
|
||||
/* PA0 */ { 1, 0, 0, 0, 0, 0 } /* PA0 */
|
||||
},
|
||||
|
||||
/* Port B configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
|
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
|
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
|
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
|
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
|
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
|
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
|
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
|
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
|
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
|
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
|
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
|
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
|
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
|
||||
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
|
||||
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
|
||||
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
|
||||
/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
|
||||
/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
|
||||
/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
|
||||
/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
|
||||
/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
|
||||
/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
|
||||
/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
|
||||
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
|
||||
/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
|
||||
/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
|
||||
/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
|
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
},
|
||||
|
||||
/* Port C */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */
|
||||
/* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */
|
||||
/* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
|
||||
/* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */
|
||||
/* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
|
||||
/* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */
|
||||
/* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */
|
||||
/* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */
|
||||
/* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
|
||||
/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
|
||||
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
||||
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
|
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
|
||||
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
|
||||
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
|
||||
/* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* PC15 */
|
||||
/* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
|
||||
/* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */
|
||||
/* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */
|
||||
/* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */
|
||||
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
|
||||
/* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
|
||||
/* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */
|
||||
/* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */
|
||||
/* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */
|
||||
/* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */
|
||||
/* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */
|
||||
/* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */
|
||||
/* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */
|
||||
/* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */
|
||||
/* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */
|
||||
},
|
||||
|
||||
/* Port D */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
||||
/* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TxD */
|
||||
/* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TENA */
|
||||
/* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* PD28 */
|
||||
/* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* PD27 */
|
||||
/* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* PD26 */
|
||||
/* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* PD25 */
|
||||
/* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* PD24 */
|
||||
/* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* PD23 */
|
||||
/* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* PD22 */
|
||||
/* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* PD21 */
|
||||
/* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* PD20 */
|
||||
/* PD19 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */
|
||||
/* PD18 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */
|
||||
/* PD17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
|
||||
/* PD16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXPRTY */
|
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
||||
/* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
/* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
/* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
/* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
||||
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
||||
/* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* PD7 */
|
||||
/* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* PD6 */
|
||||
/* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* PD5 */
|
||||
/* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* PD4 */
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
}
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Setup CS4 to enable the Board Control/Status registers.
|
||||
* Otherwise the smcs won't work.
|
||||
*/
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile memctl8260_t *memctl = &immap->im_memctl;
|
||||
memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
|
||||
memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
|
||||
regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */
|
||||
regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
reset_phy(void)
|
||||
{
|
||||
volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
|
||||
regs->bcsr4 = 0xC3;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
|
||||
printf ("Board: Embedded Planet RPX Super, Revision %d\n",
|
||||
regs->bcsr0 >> 4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile memctl8260_t *memctl = &immap->im_memctl;
|
||||
volatile uchar c = 0, *ramaddr;
|
||||
ulong psdmr, lsdmr, bcr;
|
||||
long size = 0;
|
||||
int i;
|
||||
|
||||
psdmr = CONFIG_SYS_PSDMR;
|
||||
lsdmr = CONFIG_SYS_LSDMR;
|
||||
|
||||
/*
|
||||
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
|
||||
*
|
||||
* "At system reset, initialization software must set up the
|
||||
* programmable parameters in the memory controller banks registers
|
||||
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
|
||||
* system software should execute the following initialization sequence
|
||||
* for each SDRAM device.
|
||||
*
|
||||
* 1. Issue a PRECHARGE-ALL-BANKS command
|
||||
* 2. Issue eight CBR REFRESH commands
|
||||
* 3. Issue a MODE-SET command to initialize the mode register
|
||||
*
|
||||
* The initial commands are executed by setting P/LSDMR[OP] and
|
||||
* accessing the SDRAM with a single-byte transaction."
|
||||
*
|
||||
* The appropriate BRx/ORx registers have already been set when we
|
||||
* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
|
||||
*/
|
||||
|
||||
size = CONFIG_SYS_SDRAM0_SIZE;
|
||||
bcr = immap->im_siu_conf.sc_bcr;
|
||||
immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM);
|
||||
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
|
||||
|
||||
ramaddr = (uchar *)(CONFIG_SYS_SDRAM0_BASE);
|
||||
memctl->memc_psrt = CONFIG_SYS_PSRT;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
|
||||
for (i = 0; i < 8; i++)
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||
*ramaddr = c;
|
||||
|
||||
immap->im_siu_conf.sc_bcr = bcr;
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
/* size += CONFIG_SYS_SDRAM1_SIZE; */
|
||||
ramaddr = (uchar *)(CONFIG_SYS_SDRAM1_BASE);
|
||||
memctl->memc_lsrt = CONFIG_SYS_LSRT;
|
||||
|
||||
memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR;
|
||||
for (i = 0; i < 8; i++)
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW;
|
||||
*ramaddr = c;
|
||||
|
||||
memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||
*ramaddr = c;
|
||||
#endif
|
||||
|
||||
/* return total ram size */
|
||||
return (size * 1024 * 1024);
|
||||
}
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
#ifndef __RPX8260_H__
|
||||
#define __RPX8260_H__
|
||||
|
||||
typedef struct tt_rpx_regs
|
||||
{
|
||||
volatile unsigned char bcsr0;
|
||||
volatile unsigned char bcsr1;
|
||||
volatile unsigned char bcsr2;
|
||||
volatile unsigned char bcsr3;
|
||||
volatile unsigned char bcsr4;
|
||||
volatile unsigned char bcsr5;
|
||||
volatile unsigned char bcsr6;
|
||||
volatile unsigned char bcsr7;
|
||||
volatile unsigned char bcsr8;
|
||||
volatile unsigned char bcsr9;
|
||||
volatile unsigned char bcsr10;
|
||||
volatile unsigned char bcsr11;
|
||||
volatile unsigned char bcsr12;
|
||||
volatile unsigned char bcsr13;
|
||||
volatile unsigned char bcsr14;
|
||||
volatile unsigned char bcsr15;
|
||||
} t_rpx_regs;
|
||||
typedef t_rpx_regs* tp_rpx_regs;
|
||||
|
||||
#endif
|
||||
|
|
@ -1245,4 +1245,3 @@ Orphan arm pxa - - -
|
|||
Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - -
|
||||
Orphan powerpc mpc824x - - mousse MOUSSE - -
|
||||
Orphan powerpc mpc8260 - - - rsdproto - -
|
||||
Orphan powerpc mpc8260 - - rpxsuper RPXsuper - -
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
RPXsuper powerpc mpc8260 - 2014-04-04
|
||||
RPXClassic powerpc mpc8xx - 2014-04-04
|
||||
RPXlite powerpc mpc8xx - 2014-04-04
|
||||
genietv powerpc mpc8xx - 2014-04-04
|
||||
|
|
|
|||
|
|
@ -1,501 +0,0 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80F00000
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* These settings must match the way _your_ board is set up
|
||||
*
|
||||
*****************************************************************************/
|
||||
/* for the AY-Revision which does not use the HRCW */
|
||||
#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
|
||||
|
||||
/* What is the oscillator's (UX2) frequency in Hz? */
|
||||
#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
|
||||
|
||||
/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
|
||||
* only the 3 least significant bits are important.
|
||||
*/
|
||||
#define CONFIG_SYS_SBC_S2 0x04
|
||||
|
||||
/* What should MODCK_H be? It is dependent on the oscillator
|
||||
* frequency, MODCK[1-3], and desired CPM and core frequencies.
|
||||
* Some example values (all frequencies are in MHz):
|
||||
*
|
||||
* MODCK_H MODCK[1-3] Osc CPM Core
|
||||
* 0x2 0x2 33 133 133
|
||||
* 0x2 0x4 33 133 200
|
||||
* 0x5 0x5 66 133 133
|
||||
* 0x5 0x7 66 133 200
|
||||
*/
|
||||
#define CONFIG_SYS_SBC_MODCK_H 0x06
|
||||
|
||||
#define CONFIG_SYS_SBC_BOOT_LOW 1 /* only for HRCW */
|
||||
#undef CONFIG_SYS_SBC_BOOT_LOW
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
|
||||
* The main FLASH is whichever is connected to *CS0. U-Boot expects
|
||||
* this to be the SIMM.
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH0_BASE 0x80000000
|
||||
#define CONFIG_SYS_FLASH0_SIZE 16
|
||||
|
||||
/* What should the base address of the secondary FLASH be and how big
|
||||
* is it (in Mbytes)? The secondary FLASH is whichever is connected
|
||||
* to *CS6. U-Boot expects this to be the on board FLASH. If you don't
|
||||
* want it enabled, don't define these constants.
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH1_BASE 0
|
||||
#define CONFIG_SYS_FLASH1_SIZE 0
|
||||
#undef CONFIG_SYS_FLASH1_BASE
|
||||
#undef CONFIG_SYS_FLASH1_SIZE
|
||||
|
||||
/* What should be the base address of SDRAM DIMM and how big is
|
||||
* it (in Mbytes)?
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM0_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM0_SIZE 64
|
||||
|
||||
/* What should be the base address of SDRAM DIMM and how big is
|
||||
* it (in Mbytes)?
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM1_BASE 0x04000000
|
||||
#define CONFIG_SYS_SDRAM1_SIZE 32
|
||||
|
||||
/* What should be the base address of the LEDs and switch S0?
|
||||
* If you don't want them enabled, don't define this.
|
||||
*/
|
||||
#define CONFIG_SYS_LED_BASE 0x00000000
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*
|
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*
|
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must
|
||||
* defined elsewhere.
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on neither */
|
||||
#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
|
||||
|
||||
/*
|
||||
* select ethernet configuration
|
||||
*
|
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
|
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
|
||||
* for FCC)
|
||||
*
|
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
|
||||
* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
|
||||
#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
|
||||
|
||||
#if ( CONFIG_ETHER_INDEX == 3 )
|
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK15
|
||||
* - Tx-CLK is CLK16
|
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
|
||||
* - Enable Half Duplex in FSMR
|
||||
*/
|
||||
# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
|
||||
# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
|
||||
# define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
/*#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
|
||||
# define CONFIG_SYS_FCC_PSMR 0
|
||||
|
||||
#else /* CONFIG_ETHER_INDEX */
|
||||
# error "on RPX Super ethernet must be FCC3"
|
||||
#endif /* CONFIG_ETHER_INDEX */
|
||||
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
|
||||
/* Define this to reserve an entire FLASH sector (256 KB) for
|
||||
* environment variables. Otherwise, the environment will be
|
||||
* put in the same sector as U-Boot, and changing variables
|
||||
* will erase U-Boot temporarily
|
||||
*/
|
||||
#define CONFIG_ENV_IN_OWN_SECT
|
||||
|
||||
/* Define to allow the user to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* What should the console's baud rate be? */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Ethernet MAC address */
|
||||
#define CONFIG_ETHADDR 08:00:22:50:70:63
|
||||
|
||||
#define CONFIG_IPADDR 192.168.1.99
|
||||
#define CONFIG_SERVERIP 192.168.1.3
|
||||
|
||||
/* Set to a positive value to delay for running BOOTCOMMAND */
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
|
||||
/* undef this to save memory */
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
#undef CONFIG_CMD_KGDB
|
||||
|
||||
|
||||
/* Where do the internal registers live? */
|
||||
#define CONFIG_SYS_IMMR 0xF0000000
|
||||
|
||||
/* Where do the on board registers (CS4) live? */
|
||||
#define CONFIG_SYS_REGS_BASE 0xFA000000
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* You should not have to modify any of the following settings
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
|
||||
#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
|
||||
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words
|
||||
*/
|
||||
#if defined(CONFIG_SYS_SBC_BOOT_LOW)
|
||||
# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
|
||||
#else
|
||||
# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
|
||||
#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
|
||||
|
||||
/* get the HRCW ISB field from CONFIG_SYS_IMMR */
|
||||
#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
|
||||
((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\
|
||||
((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
|
||||
|
||||
#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 |\
|
||||
HRCW_DPPC11 |\
|
||||
CONFIG_SYS_SBC_HRCW_IMMR |\
|
||||
HRCW_MMR00 |\
|
||||
HRCW_LBPC11 |\
|
||||
HRCW_APPC10 |\
|
||||
HRCW_CS10PC00 |\
|
||||
(CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) |\
|
||||
CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
|
||||
|
||||
/* no slaves */
|
||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
* Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH0_BASE + 0x00F00000)
|
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
# define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
# define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
# ifdef CONFIG_ENV_IN_OWN_SECT
|
||||
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
|
||||
# define CONFIG_ENV_SECT_SIZE 0x40000
|
||||
# else
|
||||
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
|
||||
# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
|
||||
# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
|
||||
# endif /* CONFIG_ENV_IN_OWN_SECT */
|
||||
#else
|
||||
# define CONFIG_ENV_IS_IN_NVRAM 1
|
||||
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
# define CONFIG_ENV_SIZE 0x200
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11
|
||||
*-----------------------------------------------------------------------
|
||||
* HID0 also contains cache control - initially enable both caches and
|
||||
* invalidate contents, then the final state leaves only the instruction
|
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
|
||||
* but Soft reset does not.
|
||||
*
|
||||
* HID1 has only read-only information - nothing to set.
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT (/*HID0_ICE |*/\
|
||||
/*HID0_DCE |*/\
|
||||
HID0_ICFI |\
|
||||
HID0_DCI |\
|
||||
HID0_IFEM |\
|
||||
HID0_ABE)
|
||||
|
||||
#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\
|
||||
HID0_IFEM |\
|
||||
HID0_ABE |\
|
||||
HID0_EMCP)
|
||||
#define CONFIG_SYS_HID2 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RMR 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_BCR (BCR_EBM |\
|
||||
BCR_PLDP |\
|
||||
BCR_EAV |\
|
||||
BCR_NPQM0)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\
|
||||
SIUMCR_APPC10 |\
|
||||
SIUMCR_CS10PC01)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||||
*/
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
|
||||
SYPCR_BMT |\
|
||||
SYPCR_PBME |\
|
||||
SYPCR_LBME |\
|
||||
SYPCR_SWRI |\
|
||||
SYPCR_SWP)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||||
* and enable Time Counter
|
||||
*/
|
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
|
||||
TMCNTSC_ALR |\
|
||||
TMCNTSC_TCF |\
|
||||
TMCNTSC_TCE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
* Periodic timer
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS |\
|
||||
PISCR_PTF |\
|
||||
PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RCCR 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Device
|
||||
* ---- --- ------- ------ ------
|
||||
* 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90)
|
||||
* 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
|
||||
* 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
|
||||
* 3 unused
|
||||
* 4 60x GPCM 8 bit Board Regs, LEDs, switches
|
||||
* 5 unused
|
||||
* 6 unused
|
||||
* 7 unused
|
||||
* 8 PCMCIA
|
||||
* 9 unused
|
||||
* 10 unused
|
||||
* 11 unused
|
||||
*/
|
||||
|
||||
/* Bank 0 - FLASH
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_DECC_NONE |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_6_CLK |\
|
||||
ORxG_EHTR)
|
||||
|
||||
/* Bank 1 - SDRAM
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A8 |\
|
||||
ORxS_NUMR_12 |\
|
||||
ORxS_IBID)
|
||||
|
||||
#define CONFIG_SYS_PSDMR 0x014DA412
|
||||
#define CONFIG_SYS_PSRT 0x79
|
||||
|
||||
|
||||
/* Bank 2 - SDRAM
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_32 |\
|
||||
BRx_MS_SDRAM_L |\
|
||||
BRx_V)
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A9 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#define CONFIG_SYS_LSDMR 0x0169A512
|
||||
#define CONFIG_SYS_LSRT 0x79
|
||||
|
||||
#define CONFIG_SYS_MPTPR (0x0800 & MPTPR_PTP_MSK)
|
||||
|
||||
/* Bank 4 - On board registers
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_TRLX)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue