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net: designware: fix descriptor layout and warnings on 64-bit archs
All members of the DMA descriptor must be 32-bit, even on 64-bit architectures: change the type to u32 to ensure this. Also, fix other warnings. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Use phys_addr_t not unsigned long long to test that we're within DMA'able memory] Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Beniamino Galvani
Tom Rini
parent
5a07abb370
commit
0e1a3e30de
2 changed files with 34 additions and 29 deletions
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@ -98,8 +98,8 @@ static void tx_descs_init(struct dw_eth_dev *priv)
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for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = &desc_table_p[idx + 1];
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desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
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@ -117,11 +117,11 @@ static void tx_descs_init(struct dw_eth_dev *priv)
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = &desc_table_p[0];
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desc_p->dmamac_next = (ulong)&desc_table_p[0];
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/* Flush all Tx buffer descriptors at once */
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flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
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(unsigned int)priv->tx_mac_descrtable +
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flush_dcache_range((ulong)priv->tx_mac_descrtable,
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(ulong)priv->tx_mac_descrtable +
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sizeof(priv->tx_mac_descrtable));
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writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
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@ -142,13 +142,12 @@ static void rx_descs_init(struct dw_eth_dev *priv)
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* Otherwise there's a chance to get some of them flushed in RAM when
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* GMAC is already pushing data to RAM via DMA. This way incoming from
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* GMAC data will be corrupted. */
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flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
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RX_TOTAL_BUFSIZE);
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flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
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for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = &desc_table_p[idx + 1];
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desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
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desc_p->dmamac_cntl =
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(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
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@ -158,11 +157,11 @@ static void rx_descs_init(struct dw_eth_dev *priv)
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = &desc_table_p[0];
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desc_p->dmamac_next = (ulong)&desc_table_p[0];
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/* Flush all Rx buffer descriptors at once */
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flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
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(unsigned int)priv->rx_mac_descrtable +
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flush_dcache_range((ulong)priv->rx_mac_descrtable,
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(ulong)priv->rx_mac_descrtable +
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sizeof(priv->rx_mac_descrtable));
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writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
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@ -290,12 +289,11 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u32 desc_num = priv->tx_currdescnum;
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struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
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uint32_t desc_start = (uint32_t)desc_p;
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uint32_t desc_end = desc_start +
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ulong desc_start = (ulong)desc_p;
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ulong desc_end = desc_start +
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roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
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uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
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uint32_t data_end = data_start +
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roundup(length, ARCH_DMA_MINALIGN);
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ulong data_start = desc_p->dmamac_addr;
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ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
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/*
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* Strictly we only need to invalidate the "txrx_status" field
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* for the following check, but on some platforms we cannot
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@ -312,7 +310,7 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
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return -EPERM;
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}
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memcpy(desc_p->dmamac_addr, packet, length);
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memcpy((void *)data_start, packet, length);
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/* Flush data to be sent */
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flush_dcache_range(data_start, data_end);
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@ -352,11 +350,11 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
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u32 status, desc_num = priv->rx_currdescnum;
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struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
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int length = -EAGAIN;
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uint32_t desc_start = (uint32_t)desc_p;
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uint32_t desc_end = desc_start +
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ulong desc_start = (ulong)desc_p;
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ulong desc_end = desc_start +
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roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
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uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
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uint32_t data_end;
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ulong data_start = desc_p->dmamac_addr;
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ulong data_end;
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/* Invalidate entire buffer descriptor */
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invalidate_dcache_range(desc_start, desc_end);
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@ -372,7 +370,7 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
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/* Invalidate received data */
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data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(data_start, data_end);
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*packetp = desc_p->dmamac_addr;
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*packetp = (uchar *)(ulong)desc_p->dmamac_addr;
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}
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return length;
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@ -382,8 +380,8 @@ static int _dw_free_pkt(struct dw_eth_dev *priv)
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{
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u32 desc_num = priv->rx_currdescnum;
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struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
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uint32_t desc_start = (uint32_t)desc_p;
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uint32_t desc_end = desc_start +
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ulong desc_start = (ulong)desc_p;
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ulong desc_end = desc_start +
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roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
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/*
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@ -488,6 +486,11 @@ int designware_initialize(ulong base_addr, u32 interface)
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return -ENOMEM;
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}
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if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
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printf("designware: buffers are outside DMA memory\n");
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return -EINVAL;
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}
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memset(dev, 0, sizeof(struct eth_device));
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memset(priv, 0, sizeof(struct dw_eth_dev));
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@ -583,6 +586,7 @@ static int designware_eth_probe(struct udevice *dev)
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct dw_eth_dev *priv = dev_get_priv(dev);
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u32 iobase = pdata->iobase;
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ulong ioaddr;
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int ret;
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#ifdef CONFIG_DM_PCI
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@ -601,8 +605,9 @@ static int designware_eth_probe(struct udevice *dev)
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#endif
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debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
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priv->mac_regs_p = (struct eth_mac_regs *)iobase;
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priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
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ioaddr = iobase;
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priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
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priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
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priv->interface = pdata->phy_interface;
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priv->max_speed = pdata->max_speed;
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@ -110,8 +110,8 @@ struct eth_dma_regs {
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struct dmamacdescr {
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u32 txrx_status;
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u32 dmamac_cntl;
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void *dmamac_addr;
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struct dmamacdescr *dmamac_next;
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u32 dmamac_addr;
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u32 dmamac_next;
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} __aligned(ARCH_DMA_MINALIGN);
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/*
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