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arm: mvebu: Add Marvell's integrated CPUs

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Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham 2019-04-11 22:22:50 +12:00 committed by Stefan Roese
parent 237b629e4c
commit 0d0df46ee7
8 changed files with 80 additions and 4 deletions
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18
arch/arm/mach-mvebu/Kconfig
View file

@ -46,7 +46,7 @@ config ARMADA_8K
# Armada PLL frequency (used for NAND clock generation)
config SYS_MVEBU_PLL_CLOCK
int
default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K || ARMADA_MSYS
default "1000000000" if ARMADA_38X || ARMADA_375
# Armada XP/38x SoC types...
@ -63,6 +63,22 @@ config MV78460
bool
select ARMADA_XP
config ARMADA_MSYS
bool
select ARMADA_32BIT
config 98DX4251
bool
select ARMADA_MSYS
config 98DX3336
bool
select ARMADA_MSYS
config 98DX3236
bool
select ARMADA_MSYS
config 88F6820
bool
select ARMADA_38X

1
arch/arm/mach-mvebu/Makefile
View file

@ -25,6 +25,7 @@ ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
extra-y += kwbimage.cfg

31
arch/arm/mach-mvebu/cpu.c
View file

@ -23,6 +23,11 @@ static struct mbus_win windows[] = {
/* NOR */
{ MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
#ifdef CONFIG_ARMADA_MSYS
/* DFX */
{ MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
#endif
};
void lowlevel_init(void)
@ -121,6 +126,14 @@ static const struct sar_freq_modes sar_freq_tab[] = {
{ 0x13, 0x0, 2000, 1000, 933 },
{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
};
#elif defined(CONFIG_ARMADA_MSYS)
static const struct sar_freq_modes sar_freq_tab[] = {
{ 0x0, 0x0, 400, 400, 400 },
{ 0x2, 0x0, 667, 333, 667 },
{ 0x3, 0x0, 800, 400, 800 },
{ 0x5, 0x0, 800, 400, 800 },
{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
};
#else
/* SAR frequency values for Armada XP */
static const struct sar_freq_modes sar_freq_tab[] = {
@ -144,7 +157,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
u32 freq;
int i;
#if defined(CONFIG_ARMADA_375)
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
#else
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
@ -160,7 +173,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
#endif
for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
if (sar_freq_tab[i].val == freq) {
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
*sar_freq = sar_freq_tab[i];
return;
#else
@ -270,6 +283,20 @@ int print_cpuinfo(void)
}
}
if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
switch (revid) {
case 3:
puts("A0");
break;
case 4:
puts("A1");
break;
default:
printf("?? (%x)", revid);
break;
}
}
get_sar_freq(&sar_freq);
printf(" at %d MHz\n", sar_freq.p_clk);

2
arch/arm/mach-mvebu/include/mach/config.h
View file

@ -17,7 +17,7 @@
#include <asm/arch/soc.h>
#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
|| defined(CONFIG_ARMADA_38X)
|| defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
/*
* Set this for the common xor register definitions needed in dram.c
* for A38x as well here.

3
arch/arm/mach-mvebu/include/mach/cpu.h
View file

@ -34,6 +34,7 @@ enum cpu_target {
CPU_TARGET_PCIE02 = 0x4,
CPU_TARGET_ETH01 = 0x7,
CPU_TARGET_PCIE13 = 0x8,
CPU_TARGET_DFX = 0x8,
CPU_TARGET_SASRAM = 0x9,
CPU_TARGET_SATA01 = 0xa, /* A38X */
CPU_TARGET_NAND = 0xd,
@ -79,6 +80,8 @@ enum {
#define MBUS_PCI_IO_SIZE (64 << 10)
#define MBUS_SPI_BASE 0xF4000000
#define MBUS_SPI_SIZE (8 << 20)
#define MBUS_DFX_BASE 0xF6000000
#define MBUS_DFX_SIZE (1 << 20)
#define MBUS_BOOTROM_BASE 0xF8000000
#define MBUS_BOOTROM_SIZE (8 << 20)

20
arch/arm/mach-mvebu/include/mach/soc.h
View file

@ -76,7 +76,11 @@
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
#ifdef CONFIG_ARMADA_MSYS
#define MVEBU_DFX_BASE (MBUS_DFX_BASE)
#else
#define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
#endif
#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
#define MBUS_ERR_PROP_EN (1 << 8)
@ -149,6 +153,22 @@
#define BOOT_FROM_SPI 0x32
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
#elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */
#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
#define SAR_CPU_FREQ_OFFS 18
#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
#define SAR_BOOT_DEVICE_OFFS 11
#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS)
#define BOOT_DEV_SEL_OFFS 11
#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS)
#define BOOT_FROM_NAND 0x1
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
#else
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))

5
arch/arm/mach-mvebu/mbus.c
View file

@ -344,6 +344,11 @@ static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
}
}
mbus_dram_info.num_cs = cs;
#if defined(CONFIG_ARMADA_MSYS)
/* Disable MBUS Err Prop - in order to avoid data aborts */
clrbits_le32(mbus->mbuswins_base + 0x200, BIT(8));
#endif
}
static const struct mvebu_mbus_soc_data

4
drivers/ddr/marvell/axp/xor_regs.h
View file

@ -13,7 +13,11 @@
#define XOR_UNIT(chan) ((chan) >> 1)
#define XOR_CHAN(chan) ((chan) & 1)
#ifdef CONFIG_ARMADA_MSYS
#define MV_XOR_REGS_OFFSET(unit) (0xF0800)
#else
#define MV_XOR_REGS_OFFSET(unit) (0x60900)
#endif
#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
/* XOR Engine Control Register Map */