mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Merge branch '2022-11-10-symbol-migrations'
- Migrate a number of CONFIG symbols to Kconfig and start migrating some symbol families from CONFIG to the CFG namespace.
This commit is contained in:
commit
0cbeed4f66
1156 changed files with 4269 additions and 5612 deletions
11
Kconfig
11
Kconfig
|
@ -583,6 +583,17 @@ config SYS_SRAM_SIZE
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|||
default 0x10000 if TARGET_TRICORDER
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default 0x0
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config SYS_MONITOR_LEN
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int "Maximum size in bytes reserved for U-Boot in memory"
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default 1048576 if X86
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default 0
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help
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Size of memory reserved for monitor code, used to determine
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_at_compile_time_ (!) if the environment is embedded within the
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U-Boot image, or in a separate flash sector, among other uses where
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we need to set a maximum size of the U-Boot binary itself that will
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be loaded.
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config MP
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bool "Support for multiprocessor"
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help
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|
64
README
64
README
|
@ -298,7 +298,7 @@ The following options need to be configured:
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|||
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Enables a workaround for erratum A004510. If set,
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then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
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CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
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CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
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CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
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CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
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|
@ -314,7 +314,7 @@ The following options need to be configured:
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See Freescale App Note 4493 for more information about
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this erratum.
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CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
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CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
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This is the value to write into CCSR offset 0x18600
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according to the A004510 workaround.
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|
@ -330,7 +330,7 @@ The following options need to be configured:
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Freescale DDR driver in use. This type of DDR controller is
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found in mpc83xx, mpc85xx as well as some ARM core SoCs.
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CONFIG_SYS_FSL_DDR_ADDR
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CFG_SYS_FSL_DDR_ADDR
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Freescale DDR memory-mapped register base.
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CONFIG_SYS_FSL_IFC_CLK_DIV
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|
@ -339,7 +339,7 @@ The following options need to be configured:
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CONFIG_SYS_FSL_LBC_CLK_DIV
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Defines divider of platform clock(clock input to eLBC controller).
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CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
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CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
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Physical address from the view of DDR controllers. It is the
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same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
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it could be different for ARM SoCs.
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|
@ -435,15 +435,6 @@ The following options need to be configured:
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Define this variable to enable hw flow control in serial driver.
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Current user of this option is drivers/serial/nsl16550.c driver
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- Serial Download Echo Mode:
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CONFIG_LOADS_ECHO
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If defined to 1, all characters received during a
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serial download (using the "loads" command) are
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echoed back. This might be needed by some terminal
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emulations (like "cu"), but may as well just take
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time on others. This setting #define's the initial
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value of the "loads_echo" environment variable.
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- Removal of commands
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If no commands are needed to boot, you can disable
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CONFIG_CMDLINE to remove them. In this case, the command line
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|
@ -762,11 +753,6 @@ The following options need to be configured:
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entering dfuMANIFEST state. Host waits this timeout, before
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sending again an USB request to the device.
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- Journaling Flash filesystem support:
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CONFIG_SYS_JFFS2_FIRST_SECTOR,
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CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
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Define these for a default partition on a NOR device
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- Keyboard Support:
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See Kconfig help for available keyboard drivers.
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|
@ -1052,17 +1038,6 @@ The following options need to be configured:
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|||
You should define these to the GPIO value as given directly to
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the generic GPIO functions.
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CONFIG_SYS_I2C_INIT_BOARD
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When a board is reset during an i2c bus transfer
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chips might think that the current transfer is still
|
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in progress. On some boards it is possible to access
|
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the i2c SCLK line directly, either by using the
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processor pin as a GPIO or by having a second pin
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connected to the bus. If this option is defined a
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custom i2c_init_board() routine in boards/xxx/board.c
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is run early in the boot sequence.
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CONFIG_I2C_MULTI_BUS
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This option allows the use of multiple I2C buses, each of which
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|
@ -1471,21 +1446,12 @@ Configuration Settings:
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|||
the RAM base is not zero, or RAM is divided into banks,
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this variable needs to be recalcuated to get the address.
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- CONFIG_SYS_LOADS_BAUD_CHANGE:
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Enable temporary baudrate change while serial download
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- CONFIG_SYS_SDRAM_BASE:
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Physical start address of SDRAM. _Must_ be 0 here.
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- CONFIG_SYS_FLASH_BASE:
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Physical start address of Flash memory.
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- CONFIG_SYS_MONITOR_LEN:
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Size of memory reserved for monitor code, used to
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determine _at_compile_time_ (!) if the environment is
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embedded within the U-Boot image, or in a separate
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flash sector.
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- CONFIG_SYS_MALLOC_LEN:
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Size of DRAM reserved for malloc() use.
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|
@ -1507,25 +1473,6 @@ Configuration Settings:
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|||
boards which do not use the full malloc in SPL (which is
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enabled with CONFIG_SYS_SPL_MALLOC).
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- CONFIG_SYS_NONCACHED_MEMORY:
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Size of non-cached memory area. This area of memory will be
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typically located right below the malloc() area and mapped
|
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uncached in the MMU. This is useful for drivers that would
|
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otherwise require a lot of explicit cache maintenance. For
|
||||
some drivers it's also impossible to properly maintain the
|
||||
cache. For example if the regions that need to be flushed
|
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are not a multiple of the cache-line size, *and* padding
|
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cannot be allocated between the regions to align them (i.e.
|
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if the HW requires a contiguous array of regions, and the
|
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size of each region is not cache-aligned), then a flush of
|
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one region may result in overwriting data that hardware has
|
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written to another region in the same cache-line. This can
|
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happen for example in network drivers where descriptors for
|
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buffers are typically smaller than the CPU cache-line (e.g.
|
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16 bytes vs. 32 or 64 bytes).
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Non-cached memory is only supported on 32-bit ARM at present.
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- CONFIG_SYS_BOOTMAPSZ:
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Maximum size of memory mapped by the startup code of
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the Linux kernel; all data that must be processed by
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|
@ -1751,9 +1698,6 @@ Low Level (hardware related) configuration options:
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- CONFIG_SYS_OR_TIMING_SDRAM:
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SDRAM timing
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- CONFIG_SYS_MAMR_PTA:
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periodic timer for refresh
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- CONFIG_SYS_SRIO:
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Chip has SRIO or not
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|
|
|
@ -5,4 +5,9 @@ config API
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|||
help
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||||
This option enables the U-Boot API. See api/README for more information.
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config SYS_MMC_MAX_DEVICE
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int "Maximum number of MMC devices exposed via the API"
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depends on API
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default 1
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endmenu
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|
|
|
@ -44,10 +44,6 @@ struct stor_spec {
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|||
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static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
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#ifndef CONFIG_SYS_MMC_MAX_DEVICE
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#define CONFIG_SYS_MMC_MAX_DEVICE 1
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#endif
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void dev_stor_init(void)
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{
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#if defined(CONFIG_IDE)
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|
|
24
arch/Kconfig
24
arch/Kconfig
|
@ -438,6 +438,30 @@ config TPL_SKIP_LOWLEVEL_INIT_ONLY
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normal CP15 init (such as enabling the instruction cache) is still
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performed.
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config SYS_HAS_NONCACHED_MEMORY
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bool "Enable reserving a non-cached memory area for drivers"
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depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
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help
|
||||
This is useful for drivers that would otherwise require a lot of
|
||||
explicit cache maintenance. For some drivers it's also impossible to
|
||||
properly maintain the cache. For example if the regions that need to
|
||||
be flushed are not a multiple of the cache-line size, *and* padding
|
||||
cannot be allocated between the regions to align them (i.e. if the
|
||||
HW requires a contiguous array of regions, and the size of each
|
||||
region is not cache-aligned), then a flush of one region may result
|
||||
in overwriting data that hardware has written to another region in
|
||||
the same cache-line. This can happen for example in network drivers
|
||||
where descriptors for buffers are typically smaller than the CPU
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cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
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config SYS_NONCACHED_MEMORY
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hex "Size in bytes of the non-cached memory area"
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depends on SYS_HAS_NONCACHED_MEMORY
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default 0x100000
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help
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Size of non-cached memory area. This area of memory will be typically
|
||||
located right below the malloc() area and mapped uncached in the MMU.
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source "arch/arc/Kconfig"
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source "arch/arm/Kconfig"
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source "arch/m68k/Kconfig"
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|
|
|
@ -15,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR;
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void get_sys_info(struct sys_info *sys_info)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
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struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
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struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
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unsigned int cpu;
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const u8 core_cplx_pll[6] = {
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[0] = 0, /* CC1 PPL / 1 */
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|
|
|
@ -228,7 +228,7 @@ void enable_caches(void)
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uint get_svr(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
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return in_be32(&gur->svr);
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}
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|
@ -237,7 +237,7 @@ uint get_svr(void)
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int print_cpuinfo(void)
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{
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char buf1[32], buf2[32];
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
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unsigned int svr, major, minor, ver, i;
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svr = in_be32(&gur->svr);
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|
@ -316,7 +316,7 @@ int arch_cpu_init(void)
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void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
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void *rcpm2_base =
|
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(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
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struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
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struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
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u32 state;
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|
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icache_enable();
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|
@ -355,7 +355,7 @@ int arch_cpu_init(void)
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/* Set the address at which the secondary core starts from.*/
|
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void smp_set_core_boot_addr(unsigned long addr, int corenr)
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{
|
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
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struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
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|
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out_be32(&gur->scratchrw[0], addr);
|
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}
|
||||
|
@ -363,7 +363,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
|
|||
/* Release the secondary core from holdoff state and kick it */
|
||||
void smp_kick_all_cpus(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
|
||||
out_be32(&gur->brrl, 0x2);
|
||||
|
||||
|
|
|
@ -92,7 +92,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
|
|||
int off;
|
||||
int val;
|
||||
const char *sysclk_path;
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int svr;
|
||||
svr = in_be32(&gur->svr);
|
||||
|
||||
|
@ -105,7 +105,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
|
|||
else {
|
||||
ccsr_sec_t __iomem *sec;
|
||||
|
||||
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
|
||||
sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
|
||||
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -39,7 +39,7 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg = in_be32(&gur->rcwsr[4]);
|
||||
int i;
|
||||
|
||||
|
@ -74,7 +74,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
|||
|
||||
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u64 serdes_prtcl_map = 0;
|
||||
u32 cfg;
|
||||
int lane;
|
||||
|
@ -103,14 +103,14 @@ void fsl_serdes_init(void)
|
|||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
if (!(serdes1_prtcl_map & (1ULL << NONE)))
|
||||
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
|
||||
CONFIG_SYS_FSL_SERDES_ADDR,
|
||||
CFG_SYS_FSL_SERDES_ADDR,
|
||||
RCWSR4_SRDS1_PRTCL_MASK,
|
||||
RCWSR4_SRDS1_PRTCL_SHIFT);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
if (!(serdes2_prtcl_map & (1ULL << NONE)))
|
||||
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
|
||||
CONFIG_SYS_FSL_SERDES_ADDR +
|
||||
CFG_SYS_FSL_SERDES_ADDR +
|
||||
FSL_SRDS_2 * 0x1000,
|
||||
RCWSR4_SRDS2_PRTCL_MASK,
|
||||
RCWSR4_SRDS2_PRTCL_SHIFT);
|
||||
|
|
|
@ -31,7 +31,7 @@ static void __secure ls1_save_ddr_head(void)
|
|||
{
|
||||
const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
|
||||
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
|
||||
int i;
|
||||
|
||||
out_le32(&scfg->sparecr[2], dest);
|
||||
|
@ -57,8 +57,8 @@ static void __secure ls1_fsm_setup(void)
|
|||
|
||||
static void __secure ls1_deepsleep_irq_cfg(void)
|
||||
{
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
|
||||
u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
|
||||
|
||||
/* Mask interrupts from GIC */
|
||||
|
@ -120,8 +120,8 @@ static void __secure ls1_start_fsm(void)
|
|||
{
|
||||
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
|
||||
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
|
||||
|
||||
/* Set HRSTCR */
|
||||
setbits_be32(&scfg->hrstcr, 0x80000000);
|
||||
|
@ -155,9 +155,9 @@ static void __secure ls1_start_fsm(void)
|
|||
|
||||
static void __secure ls1_deep_sleep(u32 entry_point)
|
||||
{
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
||||
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
|
||||
struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
|
||||
#ifdef QIXIS_BASE
|
||||
u32 tmp;
|
||||
void *qixis_base = (void *)QIXIS_BASE;
|
||||
|
@ -213,8 +213,8 @@ static void __secure ls1_deep_sleep(u32 entry_point)
|
|||
#else
|
||||
static void __secure ls1_sleep(void)
|
||||
{
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
|
||||
|
||||
#ifdef QIXIS_BASE
|
||||
u32 tmp;
|
||||
|
|
|
@ -129,8 +129,8 @@ psci_cpu_on:
|
|||
mov r1, r4
|
||||
|
||||
@ Get DCFG base address
|
||||
movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
|
||||
movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
|
||||
movw r4, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
|
||||
movt r4, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
|
||||
|
||||
@ Detect target CPU state
|
||||
ldr r2, [r4, #DCFG_CCSR_BRR]
|
||||
|
@ -141,8 +141,8 @@ psci_cpu_on:
|
|||
|
||||
@ Reset target CPU
|
||||
@ Get SCFG base address
|
||||
movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
|
||||
movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
|
||||
movw r0, #(CFG_SYS_FSL_SCFG_ADDR & 0xffff)
|
||||
movt r0, #(CFG_SYS_FSL_SCFG_ADDR >> 16)
|
||||
|
||||
@ Enable CORE Soft Reset
|
||||
movw r5, #0
|
||||
|
@ -216,8 +216,8 @@ psci_affinity_info:
|
|||
mov r1, r4
|
||||
|
||||
@ Get RCPM base address
|
||||
movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
|
||||
movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
|
||||
movw r4, #(CFG_SYS_FSL_RCPM_ADDR & 0xffff)
|
||||
movt r4, #(CFG_SYS_FSL_RCPM_ADDR >> 16)
|
||||
|
||||
mov r0, #PSCI_AFFINITY_LEVEL_ON
|
||||
|
||||
|
@ -236,8 +236,8 @@ out_affinity_info:
|
|||
.globl psci_system_reset
|
||||
psci_system_reset:
|
||||
@ Get DCFG base address
|
||||
movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
|
||||
movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
|
||||
movw r1, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
|
||||
movt r1, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
|
||||
|
||||
mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
|
||||
rev r2, r2
|
||||
|
|
|
@ -54,7 +54,7 @@ struct smmu_stream_id dev_stream_id[] = {
|
|||
|
||||
unsigned int get_soc_major_rev(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int svr, major;
|
||||
|
||||
svr = in_be32(&gur->svr);
|
||||
|
@ -113,7 +113,7 @@ static void erratum_a008850_early(void)
|
|||
/* part 1 of 2 */
|
||||
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
|
||||
|
||||
/* disables propagation of barrier transactions to DDRC from CCI400 */
|
||||
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
|
||||
|
@ -129,7 +129,7 @@ void erratum_a008850_post(void)
|
|||
/* part 2 of 2 */
|
||||
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
|
||||
u32 tmp;
|
||||
|
||||
/* enable propagation of barrier transactions to DDRC from CCI400 */
|
||||
|
@ -161,7 +161,7 @@ void erratum_a010315(void)
|
|||
|
||||
int arch_soc_init(void)
|
||||
{
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
unsigned int major;
|
||||
|
|
|
@ -96,11 +96,11 @@ static struct mm_region early_map[] = {
|
|||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
|
||||
SYS_FSL_OCRAM_SPACE_SIZE,
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
|
||||
{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE1,
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
|
||||
#ifdef CONFIG_FSL_IFC
|
||||
|
@ -159,7 +159,7 @@ static struct mm_region early_map[] = {
|
|||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
|
||||
SYS_FSL_OCRAM_SPACE_SIZE,
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
|
@ -168,7 +168,7 @@ static struct mm_region early_map[] = {
|
|||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
|
||||
{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE,
|
||||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
|
@ -204,7 +204,7 @@ static struct mm_region final_map[] = {
|
|||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
|
||||
SYS_FSL_OCRAM_SPACE_SIZE,
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
|
@ -213,12 +213,12 @@ static struct mm_region final_map[] = {
|
|||
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
|
||||
},
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
|
||||
{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE1,
|
||||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
|
||||
{ CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE2,
|
||||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
|
@ -333,7 +333,7 @@ static struct mm_region final_map[] = {
|
|||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
|
||||
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
|
||||
SYS_FSL_OCRAM_SPACE_SIZE,
|
||||
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
|
||||
},
|
||||
|
@ -342,7 +342,7 @@ static struct mm_region final_map[] = {
|
|||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
},
|
||||
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
|
||||
{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
|
||||
CONFIG_SYS_FSL_QSPI_SIZE,
|
||||
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
|
@ -401,7 +401,7 @@ struct mm_region *mem_map = early_map;
|
|||
|
||||
void cpu_name(char *name)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int i, svr, ver;
|
||||
|
||||
svr = gur_in32(&gur->svr);
|
||||
|
@ -430,7 +430,7 @@ void cpu_name(char *name)
|
|||
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
|
||||
/*
|
||||
* To start MMU before DDR is available, we create MMU table in SRAM.
|
||||
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
|
||||
* The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three
|
||||
* levels of translation tables here to cover 40-bit address space.
|
||||
* We use 4KB granule size, with 40 bits physical address, T0SZ=24
|
||||
* Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
|
||||
|
@ -443,7 +443,7 @@ static inline void early_mmu_setup(void)
|
|||
|
||||
/* global data is already setup, no allocation yet */
|
||||
if (el == 3)
|
||||
gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
|
||||
gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
|
||||
else
|
||||
gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
|
||||
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
|
||||
|
@ -466,7 +466,7 @@ static void fix_pcie_mmu_map(void)
|
|||
#ifdef CONFIG_ARCH_LS2080A
|
||||
unsigned int i;
|
||||
u32 svr, ver;
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
|
||||
svr = gur_in32(&gur->svr);
|
||||
ver = SVR_SOC_VER(svr);
|
||||
|
@ -775,7 +775,7 @@ enum boot_src get_boot_src(void)
|
|||
#if defined(CONFIG_FSL_LSCH3)
|
||||
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
#endif
|
||||
|
||||
if (current_el() == 2) {
|
||||
|
@ -863,7 +863,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio)
|
|||
|
||||
u32 initiator_type(u32 cluster, int init_id)
|
||||
{
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
|
||||
u32 type = 0;
|
||||
|
||||
|
@ -876,7 +876,7 @@ u32 initiator_type(u32 cluster, int init_id)
|
|||
|
||||
u32 cpu_pos_mask(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
int i = 0;
|
||||
u32 cluster, type, mask = 0;
|
||||
|
||||
|
@ -897,7 +897,7 @@ u32 cpu_pos_mask(void)
|
|||
|
||||
u32 cpu_mask(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
int i = 0, count = 0;
|
||||
u32 cluster, type, mask = 0;
|
||||
|
||||
|
@ -930,7 +930,7 @@ int cpu_numcores(void)
|
|||
int fsl_qoriq_core_to_cluster(unsigned int core)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur =
|
||||
(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
(void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
int i = 0, count = 0;
|
||||
u32 cluster;
|
||||
|
||||
|
@ -954,7 +954,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
|
|||
u32 fsl_qoriq_core_to_type(unsigned int core)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur =
|
||||
(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
(void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
int i = 0, count = 0;
|
||||
u32 cluster, type;
|
||||
|
||||
|
@ -979,7 +979,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
|
|||
#ifndef CONFIG_FSL_LSCH3
|
||||
uint get_svr(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
|
||||
return gur_in32(&gur->svr);
|
||||
}
|
||||
|
@ -988,7 +988,7 @@ uint get_svr(void)
|
|||
#ifdef CONFIG_DISPLAY_CPUINFO
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
struct sys_info sysinfo;
|
||||
char buf[32];
|
||||
unsigned int i, core;
|
||||
|
@ -1179,9 +1179,9 @@ int arch_early_init_r(void)
|
|||
|
||||
int timer_init(void)
|
||||
{
|
||||
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
|
||||
u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
|
||||
u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
|
||||
defined(CONFIG_ARCH_LS1028A)
|
||||
|
@ -1230,7 +1230,7 @@ int timer_init(void)
|
|||
}
|
||||
|
||||
#if !CONFIG_IS_ENABLED(SYSRESET)
|
||||
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
|
||||
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
|
||||
|
||||
void __efi_runtime reset_cpu(void)
|
||||
{
|
||||
|
|
|
@ -171,9 +171,9 @@ static void fdt_fixup_gic(void *blob)
|
|||
{
|
||||
int offset, err;
|
||||
u64 reg[8];
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int val;
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
|
||||
int align_64k = 0;
|
||||
|
||||
val = gur_in32(&gur->svr);
|
||||
|
@ -355,7 +355,7 @@ static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
|
|||
|
||||
static void fdt_fixup_msi(void *blob)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int rev;
|
||||
|
||||
rev = gur_in32(&gur->svr);
|
||||
|
@ -620,7 +620,7 @@ void fdt_fixup_pfe_firmware(void *blob)
|
|||
|
||||
void ft_cpu_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int svr = gur_in32(&gur->svr);
|
||||
|
||||
/* delete crypto node if not on an E-processor */
|
||||
|
@ -635,7 +635,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
|
|||
fdt_fixup_kaslr(blob);
|
||||
#endif
|
||||
|
||||
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
|
||||
sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
|
||||
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg = gur_in32(&gur->rcwsr[4]);
|
||||
int i;
|
||||
|
||||
|
@ -76,7 +76,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
|||
|
||||
int get_serdes_protocol(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg = gur_in32(&gur->rcwsr[4]) &
|
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
|
||||
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
|
@ -101,7 +101,7 @@ const char *serdes_clock_to_string(u32 clock)
|
|||
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
|
||||
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg;
|
||||
int lane;
|
||||
|
||||
|
@ -142,7 +142,7 @@ __weak int set_serdes_volt(int svdd)
|
|||
|
||||
int setup_serdes_volt(u32 svdd)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_serdes *serdes1_base;
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
struct ccsr_serdes *serdes2_base;
|
||||
|
@ -168,7 +168,7 @@ int setup_serdes_volt(u32 svdd)
|
|||
if (svdd_cur == svdd_tar)
|
||||
return 0;
|
||||
|
||||
serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR;
|
||||
serdes1_base = (void *)CFG_SYS_FSL_SERDES_ADDR;
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
serdes2_base = (void *)serdes1_base + 0x10000;
|
||||
#endif
|
||||
|
@ -406,14 +406,14 @@ void fsl_serdes_init(void)
|
|||
{
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
serdes_init(FSL_SRDS_1,
|
||||
CONFIG_SYS_FSL_SERDES_ADDR,
|
||||
CFG_SYS_FSL_SERDES_ADDR,
|
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
|
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
|
||||
serdes1_prtcl_map);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
serdes_init(FSL_SRDS_2,
|
||||
CONFIG_SYS_FSL_SERDES_ADDR,
|
||||
CFG_SYS_FSL_SERDES_ADDR,
|
||||
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
|
||||
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
|
||||
serdes2_prtcl_map);
|
||||
|
|
|
@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
void get_sys_info(struct sys_info *sys_info)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
|
||||
* mux 2 clock for LS1043A/LS1046A.
|
||||
*/
|
||||
|
@ -29,7 +29,7 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
defined(CONFIG_ARCH_LS1043A)
|
||||
u32 rcw_tmp;
|
||||
#endif
|
||||
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
|
||||
struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
|
||||
unsigned int cpu;
|
||||
const u8 core_cplx_pll[8] = {
|
||||
[0] = 0, /* CC1 PPL / 1 */
|
||||
|
|
|
@ -86,7 +86,7 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg = 0;
|
||||
int i;
|
||||
|
||||
|
@ -134,7 +134,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
|||
void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
|
||||
u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u32 cfg;
|
||||
int lane;
|
||||
|
||||
|
@ -399,18 +399,18 @@ static void do_pll_lock(u32 cfg,
|
|||
|
||||
int setup_serdes_volt(u32 svdd)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_serdes __iomem *serdes1_base =
|
||||
(void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
|
||||
(void *)CFG_SYS_FSL_LSCH3_SERDES_ADDR;
|
||||
u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
struct ccsr_serdes __iomem *serdes2_base =
|
||||
(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
|
||||
(void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
|
||||
u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NXP_SRDS_3
|
||||
struct ccsr_serdes __iomem *serdes3_base =
|
||||
(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
|
||||
(void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
|
||||
u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
|
||||
#endif
|
||||
u32 cfg_tmp;
|
||||
|
@ -585,7 +585,7 @@ void fsl_serdes_init(void)
|
|||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
serdes_init(FSL_SRDS_1,
|
||||
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
|
||||
CFG_SYS_FSL_LSCH3_SERDES_ADDR,
|
||||
FSL_CHASSIS3_SRDS1_REGSR,
|
||||
FSL_CHASSIS3_SRDS1_PRTCL_MASK,
|
||||
FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
|
||||
|
@ -593,7 +593,7 @@ void fsl_serdes_init(void)
|
|||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
serdes_init(FSL_SRDS_2,
|
||||
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
|
||||
CFG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
|
||||
FSL_CHASSIS3_SRDS2_REGSR,
|
||||
FSL_CHASSIS3_SRDS2_PRTCL_MASK,
|
||||
FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
|
||||
|
@ -601,7 +601,7 @@ void fsl_serdes_init(void)
|
|||
#endif
|
||||
#ifdef CONFIG_SYS_NXP_SRDS_3
|
||||
serdes_init(NXP_SRDS_3,
|
||||
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
|
||||
CFG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
|
||||
FSL_CHASSIS3_SRDS3_REGSR,
|
||||
FSL_CHASSIS3_SRDS3_PRTCL_MASK,
|
||||
FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
|
||||
|
@ -611,7 +611,7 @@ void fsl_serdes_init(void)
|
|||
|
||||
int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
char scfg[16], snum[16];
|
||||
int cfgr = 0;
|
||||
u32 cfg;
|
||||
|
|
|
@ -23,13 +23,13 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
void get_sys_info(struct sys_info *sys_info)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
|
||||
(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
|
||||
(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
|
||||
(void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR),
|
||||
(void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR)
|
||||
};
|
||||
struct ccsr_clk_ctrl __iomem *clk_ctrl =
|
||||
(void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
|
||||
(void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR);
|
||||
unsigned int cpu;
|
||||
const u8 core_cplx_pll[16] = {
|
||||
[0] = 0, /* CC1 PPL / 1 */
|
||||
|
@ -68,7 +68,7 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
|
||||
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
|
||||
unsigned long sysclk = get_board_sys_clk();
|
||||
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
|
||||
int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
|
||||
u32 c_pll_sel, cplx_pll;
|
||||
void *offset;
|
||||
|
||||
|
|
|
@ -27,7 +27,7 @@ static void set_icid(struct icid_id_table *tbl, int size)
|
|||
void set_fman_icids(struct fman_icid_id_table *tbl, int size)
|
||||
{
|
||||
int i;
|
||||
ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
|
||||
ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
|
||||
|
|
|
@ -325,8 +325,8 @@ ENDPROC(fsl_ocram_init)
|
|||
|
||||
ENTRY(fsl_clear_ocram)
|
||||
/* Clear OCRAM */
|
||||
ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
|
||||
ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
|
||||
ldr x0, =CFG_SYS_FSL_OCRAM_BASE
|
||||
ldr x1, =(CFG_SYS_FSL_OCRAM_BASE + CFG_SYS_FSL_OCRAM_SIZE)
|
||||
mov x2, #0
|
||||
clear_loop:
|
||||
str x2, [x0]
|
||||
|
|
|
@ -53,7 +53,7 @@ static struct serdes_config *serdes_cfg_tbl[] = {
|
|||
|
||||
bool soc_has_mac1(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
unsigned int svr = gur_in32(&gur->svr);
|
||||
unsigned int version = SVR_SOC_VER(svr);
|
||||
|
||||
|
|
|
@ -48,8 +48,8 @@ void update_os_arch_secondary_cores(uint8_t os_arch)
|
|||
#ifdef CONFIG_FSL_LSCH3
|
||||
static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
|
||||
u32 mpidr = 0;
|
||||
|
||||
mpidr = ((cluster << 8) | core);
|
||||
|
@ -73,13 +73,13 @@ static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
|
|||
|
||||
int fsl_layerscape_wake_seconday_cores(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
|
||||
struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
|
||||
u32 svr, ver, cluster, type;
|
||||
int j = 0, cluster_cores = 0;
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
|
||||
struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
|
||||
#endif
|
||||
u32 cores, cpu_up_mask = 1;
|
||||
int i, timeout = 10;
|
||||
|
|
|
@ -253,7 +253,7 @@ int ppa_init(void)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_LSCH3
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
boot_loc_ptr_l = &gur->bootlocptrl;
|
||||
boot_loc_ptr_h = &gur->bootlocptrh;
|
||||
|
||||
|
@ -261,7 +261,7 @@ int ppa_init(void)
|
|||
loadable_l = &gur->scratchrw[4];
|
||||
loadable_h = &gur->scratchrw[5];
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
|
||||
struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
|
||||
boot_loc_ptr_l = &scfg->scratchrw[1];
|
||||
boot_loc_ptr_h = &scfg->scratchrw[0];
|
||||
|
||||
|
|
|
@ -80,7 +80,7 @@ int ls_gic_rd_tables_init(void *blob)
|
|||
|
||||
bool soc_has_dp_ddr(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u32 svr = gur_in32(&gur->svr);
|
||||
|
||||
/* LS2085A, LS2088A, LS2048A has DP_DDR */
|
||||
|
@ -94,7 +94,7 @@ bool soc_has_dp_ddr(void)
|
|||
|
||||
bool soc_has_aiop(void)
|
||||
{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u32 svr = gur_in32(&gur->svr);
|
||||
|
||||
/* LS2085A has AIOP */
|
||||
|
@ -249,13 +249,13 @@ static void erratum_a008336(void)
|
|||
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
|
||||
u32 *eddrtqcr1;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
|
||||
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
|
||||
#ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
|
||||
eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
|
||||
if (fsl_ddr_get_version(0) == 0x50200)
|
||||
out_le32(eddrtqcr1, 0x63b30002);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
|
||||
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
|
||||
#ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
|
||||
eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
|
||||
if (fsl_ddr_get_version(0) == 0x50200)
|
||||
out_le32(eddrtqcr1, 0x63b30002);
|
||||
#endif
|
||||
|
@ -271,8 +271,8 @@ static void erratum_a008514(void)
|
|||
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
|
||||
u32 *eddrtqcr1;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
|
||||
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
|
||||
#ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
|
||||
eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
|
||||
out_le32(eddrtqcr1, 0x63b20002);
|
||||
#endif
|
||||
#endif
|
||||
|
@ -412,7 +412,7 @@ void fsl_lsch3_early_init_f(void)
|
|||
/* Get VDD in the unit mV from voltage ID */
|
||||
int get_core_volt_from_fuse(void)
|
||||
{
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
int vdd;
|
||||
u32 fusesr;
|
||||
u8 vid;
|
||||
|
@ -462,7 +462,7 @@ int get_core_volt_from_fuse(void)
|
|||
static void erratum_a009660(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
|
||||
u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
|
||||
u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
|
||||
out_be32(eddrtqcr1, 0x63b20042);
|
||||
#endif
|
||||
}
|
||||
|
@ -473,7 +473,7 @@ static void erratum_a008850_early(void)
|
|||
/* part 1 of 2 */
|
||||
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
|
||||
|
||||
/* Skip if running at lower exception level */
|
||||
if (current_el() < 3)
|
||||
|
@ -493,7 +493,7 @@ void erratum_a008850_post(void)
|
|||
/* part 2 of 2 */
|
||||
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
|
||||
u32 tmp;
|
||||
|
||||
/* Skip if running at lower exception level */
|
||||
|
@ -526,21 +526,21 @@ void erratum_a010315(void)
|
|||
static void erratum_a010539(void)
|
||||
{
|
||||
#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
u32 porsr1;
|
||||
|
||||
porsr1 = in_be32(&gur->porsr1);
|
||||
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
|
||||
out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
|
||||
porsr1);
|
||||
out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
|
||||
out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Get VDD in the unit mV from voltage ID */
|
||||
int get_core_volt_from_fuse(void)
|
||||
{
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
|
||||
int vdd;
|
||||
u32 fusesr;
|
||||
u8 vid;
|
||||
|
@ -588,7 +588,7 @@ static int setup_core_volt(u32 vdd)
|
|||
#ifdef CONFIG_SYS_FSL_DDR
|
||||
static void ddr_enable_0v9_volt(bool en)
|
||||
{
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
|
||||
u32 tmp;
|
||||
|
||||
tmp = ddr_in32(&ddr->ddr_cdr1);
|
||||
|
@ -629,7 +629,7 @@ int setup_chip_volt(void)
|
|||
#ifdef CONFIG_FSL_PFE
|
||||
void init_pfe_scfg_dcfg_regs(void)
|
||||
{
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
|
||||
u32 ecccr2;
|
||||
|
||||
out_be32(&scfg->pfeasbcr,
|
||||
|
@ -653,7 +653,7 @@ void fsl_lsch2_early_init_f(void)
|
|||
{
|
||||
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
|
||||
CONFIG_SYS_CCI400_OFFSET);
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
|
||||
#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
|
||||
enum boot_src src;
|
||||
#endif
|
||||
|
|
|
@ -24,7 +24,7 @@
|
|||
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
|
||||
|
||||
#ifdef CONFIG_ARCH_LS2080A
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
|
||||
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
|
||||
#define SRDS_MAX_LANES 8
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
#ifndef L1_CACHE_BYTES
|
||||
|
@ -32,9 +32,9 @@
|
|||
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
|
@ -95,7 +95,7 @@
|
|||
#define EPU_EPGCR 0x700060000ULL
|
||||
|
||||
#elif defined(CONFIG_ARCH_LS1088A)
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
||||
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
|
||||
#define SRDS_MAX_LANES 4
|
||||
|
@ -126,9 +126,9 @@
|
|||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
||||
|
||||
/* DCFG - GUR */
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
|
||||
/* LX2160A/LX2162A Soc Support */
|
||||
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||
|
@ -139,13 +139,13 @@
|
|||
#define L1_CACHE_SHIFT 6
|
||||
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
|
||||
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
|
||||
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
|
||||
#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
|
@ -161,7 +161,7 @@
|
|||
/* DCFG - GUR */
|
||||
|
||||
#elif defined(CONFIG_ARCH_LS1028A)
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
||||
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
||||
#define CONFIG_FSL_TZASC_400
|
||||
|
||||
/* TZ Protection Controller Definitions */
|
||||
|
@ -180,9 +180,9 @@
|
|||
#define SRDS_MAX_LANES 4
|
||||
#define SRDS_BITS_PER_LANE 4
|
||||
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
|
||||
#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
|
||||
|
||||
/* Generic Interrupt Controller Definitions */
|
||||
#define GICD_BASE 0x06000000
|
||||
|
@ -200,9 +200,9 @@
|
|||
/* DCFG - GUR */
|
||||
|
||||
#elif defined(CONFIG_FSL_LSCH2)
|
||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
|
||||
#define CFG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
|
||||
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
||||
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
||||
|
||||
#define DCSR_DCFG_SBEESR2 0x20140534
|
||||
#define DCSR_DCFG_MBEESR2 0x20140544
|
||||
|
|
|
@ -10,7 +10,7 @@
|
|||
#ifdef CONFIG_FSL_LSCH3
|
||||
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
|
||||
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
|
||||
#define CFG_SYS_FSL_QSPI_BASE1 0x20000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
|
||||
#ifndef CONFIG_NXP_LSCH3_2
|
||||
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
|
||||
|
@ -19,7 +19,7 @@
|
|||
#endif
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
|
||||
#define CFG_SYS_FSL_QSPI_BASE2 0x400000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
|
||||
#ifndef CONFIG_NXP_LSCH3_2
|
||||
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
|
||||
|
@ -73,7 +73,7 @@
|
|||
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
|
||||
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
|
||||
#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
|
||||
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
|
||||
#define CFG_SYS_FSL_QSPI_BASE 0x40000000
|
||||
#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
|
||||
#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
|
||||
#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
|
||||
|
|
|
@ -70,7 +70,7 @@ void fdt_fixup_icid(void *blob);
|
|||
|
||||
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
|
||||
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
|
||||
offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
|
||||
offsetof(struct ccsr_scfg, name) + CFG_SYS_FSL_SCFG_ADDR, \
|
||||
compataddr, SCFG_IS_LE)
|
||||
|
||||
#define SET_USB_ICID(usb_num, compat, streamid) \
|
||||
|
@ -83,7 +83,7 @@ void fdt_fixup_icid(void *blob);
|
|||
|
||||
#define SET_SDHC_ICID(streamid) \
|
||||
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
|
||||
CONFIG_SYS_FSL_ESDHC_ADDR)
|
||||
CFG_SYS_FSL_ESDHC_ADDR)
|
||||
|
||||
#define SET_EDMA_ICID(streamid) \
|
||||
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
|
||||
|
@ -102,14 +102,14 @@ void fdt_fixup_icid(void *blob);
|
|||
#define SET_QMAN_ICID(streamid) \
|
||||
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
|
||||
offsetof(struct ccsr_qman, liodnr) + \
|
||||
CONFIG_SYS_FSL_QMAN_ADDR, \
|
||||
CONFIG_SYS_FSL_QMAN_ADDR, false)
|
||||
CFG_SYS_FSL_QMAN_ADDR, \
|
||||
CFG_SYS_FSL_QMAN_ADDR, false)
|
||||
|
||||
#define SET_BMAN_ICID(streamid) \
|
||||
SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
|
||||
offsetof(struct ccsr_bman, liodnr) + \
|
||||
CONFIG_SYS_FSL_BMAN_ADDR, \
|
||||
CONFIG_SYS_FSL_BMAN_ADDR, false)
|
||||
CFG_SYS_FSL_BMAN_ADDR, \
|
||||
CFG_SYS_FSL_BMAN_ADDR, false)
|
||||
|
||||
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
|
||||
{ .port_id = (_port_id), .icid = (streamid) }
|
||||
|
@ -119,8 +119,8 @@ void fdt_fixup_icid(void *blob);
|
|||
#define SET_SEC_QI_ICID(streamid) \
|
||||
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
|
||||
0, offsetof(ccsr_sec_t, qilcr_ls) + \
|
||||
CONFIG_SYS_FSL_SEC_ADDR, \
|
||||
CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
|
||||
CFG_SYS_FSL_SEC_ADDR, \
|
||||
CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
|
||||
|
||||
extern struct fman_icid_id_table fman_icid_tbl[];
|
||||
extern int fman_icid_tbl_sz;
|
||||
|
@ -137,7 +137,7 @@ extern int fman_icid_tbl_sz;
|
|||
|
||||
#define SET_GUR_ICID(compat, streamid, name, compataddr) \
|
||||
SET_ICID_ENTRY(compat, streamid, streamid, \
|
||||
offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
|
||||
offsetof(struct ccsr_gur, name) + CFG_SYS_FSL_GUTS_ADDR, \
|
||||
compataddr, GUR_IS_LE)
|
||||
|
||||
#define SET_USB_ICID(usb_num, compat, streamid) \
|
||||
|
@ -180,24 +180,24 @@ extern int fman_icid_tbl_sz;
|
|||
SET_ICID_ENTRY( \
|
||||
(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
|
||||
(FSL_SEC_JR##jr_num##_OFFSET == \
|
||||
SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
|
||||
SEC_JR3_OFFSET + CFG_SYS_FSL_SEC_OFFSET) \
|
||||
? NULL \
|
||||
: "fsl,sec-v4.0-job-ring"), \
|
||||
streamid, \
|
||||
SEC_ICID_REG_VAL(streamid), \
|
||||
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_ADDR, \
|
||||
CFG_SYS_FSL_SEC_ADDR, \
|
||||
FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
|
||||
|
||||
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
|
||||
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
|
||||
offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
|
||||
CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
|
||||
|
||||
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
|
||||
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
|
||||
offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
|
||||
CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
|
||||
|
||||
extern struct icid_id_table icid_tbl[];
|
||||
extern int icid_tbl_sz;
|
||||
|
|
|
@ -14,18 +14,18 @@
|
|||
#define CONFIG_SYS_DCSRBAR 0x20000000
|
||||
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
|
||||
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
|
||||
#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
|
||||
#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
|
||||
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
|
||||
#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
|
||||
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
|
||||
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
|
||||
#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
|
||||
#define CFG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
|
||||
#define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
|
||||
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
|
||||
#define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
|
||||
|
@ -65,7 +65,7 @@
|
|||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
|
||||
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
|
||||
#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
|
||||
|
@ -165,24 +165,24 @@ struct sys_info {
|
|||
unsigned long freq_qman;
|
||||
};
|
||||
|
||||
#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
|
||||
#define CFG_SYS_FSL_FM1_OFFSET 0xa00000
|
||||
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
|
||||
#define CONFIG_SYS_FSL_FM1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
|
||||
#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
|
||||
#define CFG_SYS_FSL_FM1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
|
||||
#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
|
||||
#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
|
||||
#define CFG_SYS_FSL_SEC_OFFSET 0x700000ull
|
||||
#define CFG_SYS_FSL_JR0_OFFSET 0x710000ull
|
||||
#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
|
||||
#define FSL_SEC_JR1_OFFSET 0x720000ull
|
||||
#define FSL_SEC_JR2_OFFSET 0x730000ull
|
||||
#define FSL_SEC_JR3_OFFSET 0x740000ull
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CFG_SYS_FSL_SEC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
|
||||
#define CFG_SYS_FSL_JR0_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
|
||||
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
|
||||
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
|
||||
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
|
||||
|
|
|
@ -9,19 +9,19 @@
|
|||
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
|
||||
#define __ARCH_FSL_LSCH3_IMMAP_H_
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
|
||||
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
||||
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
||||
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CFG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
|
||||
#define CFG_SYS_FSL_DDR3_ADDR 0x08210000
|
||||
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
|
||||
#define CFG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
|
||||
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
|
||||
#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
||||
#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
|
||||
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
|
||||
#define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
|
||||
#define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
|
||||
#define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
|
||||
#ifndef CONFIG_NXP_LSCH3_2
|
||||
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
|
||||
#else
|
||||
|
@ -29,8 +29,8 @@
|
|||
#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18
|
||||
#define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
|
||||
#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR
|
||||
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
|
||||
#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
|
||||
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
|
||||
#ifndef CONFIG_NXP_LSCH3_2
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
|
||||
|
@ -38,20 +38,20 @@
|
|||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
|
||||
#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
|
||||
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
|
||||
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
|
||||
#define CFG_SYS_FSL_TIMER_ADDR 0x023e0000
|
||||
#define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \
|
||||
0x18A0)
|
||||
#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
|
||||
#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
|
||||
#define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0)
|
||||
#define FSL_LSCH3_SVR (CFG_SYS_FSL_GUTS_ADDR + 0xA4)
|
||||
|
||||
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
|
||||
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
|
||||
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
|
||||
#define CFG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
|
||||
#define CFG_SYS_FSL_WRIOP1_MDIO1 (CFG_SYS_FSL_WRIOP1_ADDR + 0x16000)
|
||||
#define CFG_SYS_FSL_WRIOP1_MDIO2 (CFG_SYS_FSL_WRIOP1_ADDR + 0x17000)
|
||||
#define CFG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
|
||||
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
|
||||
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
|
||||
#define CFG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
|
||||
#define CFG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
|
||||
#define CFG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
|
||||
|
@ -108,16 +108,16 @@
|
|||
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
|
||||
|
||||
/* SEC */
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
|
||||
#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
|
||||
#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull
|
||||
#define CFG_SYS_FSL_JR0_OFFSET 0x07010000ull
|
||||
#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
|
||||
#define FSL_SEC_JR1_OFFSET 0x07020000ull
|
||||
#define FSL_SEC_JR2_OFFSET 0x07030000ull
|
||||
#define FSL_SEC_JR3_OFFSET 0x07040000ull
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CFG_SYS_FSL_SEC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
|
||||
#define CFG_SYS_FSL_JR0_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
|
||||
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
|
||||
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
|
||||
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
|
||||
|
|
|
@ -47,6 +47,6 @@
|
|||
#define USB_BASE_ADDR 0x5b0d0000
|
||||
#define USB_PHY0_BASE_ADDR 0x5b100000
|
||||
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
|
||||
#define CFG_SYS_FSL_SEC_ADDR (0x31400000)
|
||||
|
||||
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
|
||||
|
|
|
@ -87,12 +87,12 @@
|
|||
#define CAAM_ARB_BASE_ADDR (0x00100000)
|
||||
#define CAAM_ARB_END_ADDR (0x00107FFF)
|
||||
#define CAAM_IPS_BASE_ADDR (0x30900000)
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET (0)
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
|
||||
CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CFG_SYS_FSL_SEC_OFFSET (0)
|
||||
#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
|
||||
CFG_SYS_FSL_SEC_OFFSET)
|
||||
#define CFG_SYS_FSL_JR0_OFFSET (0x1000)
|
||||
#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
|
||||
CFG_SYS_FSL_JR0_OFFSET)
|
||||
#if !defined(__ASSEMBLY__)
|
||||
#include <asm/types.h>
|
||||
#include <linux/bitops.h>
|
||||
|
|
|
@ -17,25 +17,25 @@
|
|||
#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
|
||||
|
||||
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
|
||||
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
|
||||
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
|
||||
#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
|
||||
#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
|
||||
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
|
||||
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
|
||||
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
|
||||
#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
|
||||
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
|
||||
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
|
||||
#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
|
||||
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
|
||||
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
|
||||
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
|
||||
#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
|
||||
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
|
||||
|
||||
|
|
|
@ -29,30 +29,30 @@
|
|||
#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
|
||||
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
|
||||
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
|
||||
CFG_SYS_FSL_SEC_OFFSET, \
|
||||
CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
|
||||
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
|
||||
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
|
||||
CFG_SYS_FSL_SEC_OFFSET, \
|
||||
CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
|
||||
|
||||
/* This is a bit evil since we treat rtic param as both a string & hex value */
|
||||
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
|
||||
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
|
||||
liodnA, \
|
||||
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
|
||||
CFG_SYS_FSL_SEC_OFFSET, \
|
||||
CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
|
||||
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
|
||||
liodnA, \
|
||||
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
|
||||
CFG_SYS_FSL_SEC_OFFSET, \
|
||||
CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
|
||||
|
||||
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
|
||||
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
|
||||
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, 0)
|
||||
CFG_SYS_FSL_SEC_OFFSET, 0)
|
||||
|
||||
struct liodn_id_table {
|
||||
const char *compat;
|
||||
|
|
|
@ -238,12 +238,12 @@
|
|||
#endif
|
||||
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
|
||||
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
|
||||
CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CFG_SYS_FSL_SEC_OFFSET 0
|
||||
#define CFG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
|
||||
CFG_SYS_FSL_SEC_OFFSET)
|
||||
#define CFG_SYS_FSL_JR0_OFFSET 0x1000
|
||||
#define CFG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
|
||||
CFG_SYS_FSL_JR0_OFFSET)
|
||||
|
||||
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
|
||||
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
|
||||
|
|
|
@ -215,12 +215,12 @@
|
|||
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
#define SNVS_LPGPR 0x68
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
|
||||
CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CFG_SYS_FSL_SEC_OFFSET 0
|
||||
#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
|
||||
CFG_SYS_FSL_SEC_OFFSET)
|
||||
#define CFG_SYS_FSL_JR0_OFFSET 0x1000
|
||||
#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
|
||||
CFG_SYS_FSL_JR0_OFFSET)
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/mach-imx/regs-lcdif.h>
|
||||
#include <asm/types.h>
|
||||
|
|
|
@ -228,12 +228,12 @@
|
|||
|
||||
#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */
|
||||
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
|
||||
CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CFG_SYS_FSL_SEC_OFFSET 0
|
||||
#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
|
||||
CFG_SYS_FSL_SEC_OFFSET)
|
||||
#define CFG_SYS_FSL_JR0_OFFSET 0x1000
|
||||
#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
|
||||
CFG_SYS_FSL_JR0_OFFSET)
|
||||
|
||||
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
|
||||
#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))
|
||||
|
|
|
@ -40,7 +40,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
|
|||
|
||||
hab_caam_clock_enable(1);
|
||||
|
||||
u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
|
||||
u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
|
||||
FSL_CAAM_ORSR_JRa_OFFSET);
|
||||
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
|
||||
sec_init();
|
||||
|
|
|
@ -41,7 +41,7 @@ static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const arg
|
|||
/* Enable HAB clock */
|
||||
hab_caam_clock_enable(1);
|
||||
|
||||
u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
|
||||
u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
|
||||
FSL_CAAM_ORSR_JRa_OFFSET);
|
||||
|
||||
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
|
||||
|
|
|
@ -30,9 +30,9 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
int get_clocks(void)
|
||||
{
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
|
||||
#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
|
||||
#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
#else
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
|
|
|
@ -18,9 +18,9 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
int get_clocks(void)
|
||||
{
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
|
||||
#if CFG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
|
||||
#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
@ -21,21 +21,21 @@ int get_clocks(void)
|
|||
{
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
|
||||
#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
|
||||
#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
|
||||
#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
#else
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
#endif
|
||||
#else
|
||||
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
|
||||
#if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
|
||||
#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
|
||||
#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
#else
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include <asm/sections.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <dt-bindings/clock/mt8512-clk.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
File diff suppressed because one or more lines are too long
|
@ -17,19 +17,19 @@ int iocsr_get_config_table(const unsigned int chain_id,
|
|||
switch (chain_id) {
|
||||
case 0:
|
||||
*table = iocsr_scan_chain0_table;
|
||||
*table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
|
||||
*table_len = CFG_HPS_IOCSR_SCANCHAIN0_LENGTH;
|
||||
break;
|
||||
case 1:
|
||||
*table = iocsr_scan_chain1_table;
|
||||
*table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
|
||||
*table_len = CFG_HPS_IOCSR_SCANCHAIN1_LENGTH;
|
||||
break;
|
||||
case 2:
|
||||
*table = iocsr_scan_chain2_table;
|
||||
*table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
|
||||
*table_len = CFG_HPS_IOCSR_SCANCHAIN2_LENGTH;
|
||||
break;
|
||||
case 3:
|
||||
*table = iocsr_scan_chain3_table;
|
||||
*table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
|
||||
*table_len = CFG_HPS_IOCSR_SCANCHAIN3_LENGTH;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
|
|
|
@ -8,116 +8,116 @@
|
|||
#include <qts/pll_config.h>
|
||||
|
||||
#define MAIN_VCO_BASE ( \
|
||||
(CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
|
||||
(CFG_HPS_MAINPLLGRP_VCO_DENOM << \
|
||||
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
|
||||
(CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
|
||||
(CFG_HPS_MAINPLLGRP_VCO_NUMER << \
|
||||
CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
|
||||
)
|
||||
|
||||
#define PERI_VCO_BASE ( \
|
||||
(CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
|
||||
(CFG_HPS_PERPLLGRP_VCO_PSRC << \
|
||||
CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
|
||||
(CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
|
||||
(CFG_HPS_PERPLLGRP_VCO_DENOM << \
|
||||
CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
|
||||
(CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
|
||||
(CFG_HPS_PERPLLGRP_VCO_NUMER << \
|
||||
CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
|
||||
)
|
||||
|
||||
#define SDR_VCO_BASE ( \
|
||||
(CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
|
||||
(CFG_HPS_SDRPLLGRP_VCO_SSRC << \
|
||||
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
|
||||
(CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
|
||||
(CFG_HPS_SDRPLLGRP_VCO_DENOM << \
|
||||
CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
|
||||
(CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
|
||||
(CFG_HPS_SDRPLLGRP_VCO_NUMER << \
|
||||
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
|
||||
)
|
||||
|
||||
static const struct cm_config cm_default_cfg = {
|
||||
/* main group */
|
||||
MAIN_VCO_BASE,
|
||||
(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
|
||||
(CFG_HPS_MAINPLLGRP_MPUCLK_CNT <<
|
||||
CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
|
||||
(CFG_HPS_MAINPLLGRP_MAINCLK_CNT <<
|
||||
CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
|
||||
(CFG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
|
||||
CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
|
||||
(CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
|
||||
CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
|
||||
(CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
|
||||
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
|
||||
(CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
|
||||
CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
|
||||
(CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
|
||||
CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
|
||||
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
|
||||
(CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
|
||||
CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
|
||||
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
|
||||
(CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
|
||||
CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
|
||||
(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
|
||||
(CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
|
||||
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
|
||||
(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
|
||||
(CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
|
||||
CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
|
||||
(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
|
||||
(CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
|
||||
CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
|
||||
(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
|
||||
(CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
|
||||
CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
|
||||
(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
|
||||
(CFG_HPS_MAINPLLGRP_L4SRC_L4MP <<
|
||||
CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
|
||||
(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
|
||||
(CFG_HPS_MAINPLLGRP_L4SRC_L4SP <<
|
||||
CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
|
||||
|
||||
/* peripheral group */
|
||||
PERI_VCO_BASE,
|
||||
(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
|
||||
(CFG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
|
||||
CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
|
||||
(CFG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
|
||||
CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
|
||||
(CFG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
|
||||
CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
|
||||
(CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
|
||||
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
|
||||
(CFG_HPS_PERPLLGRP_PERBASECLK_CNT <<
|
||||
CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
|
||||
(CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
|
||||
CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
|
||||
(CFG_HPS_PERPLLGRP_DIV_USBCLK <<
|
||||
CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
|
||||
(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
|
||||
(CFG_HPS_PERPLLGRP_DIV_SPIMCLK <<
|
||||
CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
|
||||
(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
|
||||
(CFG_HPS_PERPLLGRP_DIV_CAN0CLK <<
|
||||
CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
|
||||
(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
|
||||
(CFG_HPS_PERPLLGRP_DIV_CAN1CLK <<
|
||||
CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
|
||||
(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
|
||||
(CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
|
||||
CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
|
||||
(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
|
||||
(CFG_HPS_PERPLLGRP_SRC_QSPI <<
|
||||
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
|
||||
(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
|
||||
(CFG_HPS_PERPLLGRP_SRC_NAND <<
|
||||
CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
|
||||
(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
|
||||
(CFG_HPS_PERPLLGRP_SRC_SDMMC <<
|
||||
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
|
||||
|
||||
/* sdram pll group */
|
||||
SDR_VCO_BASE,
|
||||
(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
|
||||
(CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
|
||||
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
|
||||
(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
|
||||
(CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
|
||||
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
|
||||
(CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
|
||||
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
|
||||
(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
|
||||
(CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
|
||||
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
|
||||
(CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
|
||||
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
|
||||
(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
|
||||
(CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
|
||||
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
|
||||
(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
|
||||
(CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
|
||||
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
|
||||
(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
|
||||
(CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
|
||||
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
|
||||
|
||||
/* altera group */
|
||||
CONFIG_HPS_ALTERAGRP_MPUCLK,
|
||||
CFG_HPS_ALTERAGRP_MPUCLK,
|
||||
};
|
||||
|
||||
const struct cm_config * const cm_get_default_config(void)
|
||||
|
@ -128,19 +128,19 @@ const struct cm_config * const cm_get_default_config(void)
|
|||
const unsigned int cm_get_osc_clk_hz(const int osc)
|
||||
{
|
||||
if (osc == 1)
|
||||
return CONFIG_HPS_CLK_OSC1_HZ;
|
||||
return CFG_HPS_CLK_OSC1_HZ;
|
||||
else if (osc == 2)
|
||||
return CONFIG_HPS_CLK_OSC2_HZ;
|
||||
return CFG_HPS_CLK_OSC2_HZ;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
const unsigned int cm_get_f2s_per_ref_clk_hz(void)
|
||||
{
|
||||
return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
|
||||
return CFG_HPS_CLK_F2S_PER_REF_HZ;
|
||||
}
|
||||
|
||||
const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
|
||||
{
|
||||
return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
|
||||
return CFG_HPS_CLK_F2S_SDR_REF_HZ;
|
||||
}
|
||||
|
|
|
@ -12,180 +12,180 @@
|
|||
|
||||
static const struct socfpga_sdram_config sdram_config = {
|
||||
.ctrl_cfg =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
|
||||
SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
|
||||
SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
|
||||
SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
|
||||
SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
|
||||
SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
|
||||
SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
|
||||
SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
|
||||
SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
|
||||
SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
|
||||
.dram_timing1 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
|
||||
SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
|
||||
SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
|
||||
SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
|
||||
SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
|
||||
SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
|
||||
SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
|
||||
.dram_timing2 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
|
||||
SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
|
||||
SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
|
||||
SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
|
||||
SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
|
||||
SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
|
||||
.dram_timing3 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
|
||||
SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
|
||||
SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
|
||||
SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
|
||||
SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
|
||||
SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
|
||||
.dram_timing4 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
|
||||
SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
|
||||
SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
|
||||
.lowpwr_timing =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
|
||||
(CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
|
||||
SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
|
||||
(CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
|
||||
SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
|
||||
.dram_odt =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
|
||||
SDR_CTRLGRP_DRAMODT_READ_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
|
||||
SDR_CTRLGRP_DRAMODT_WRITE_LSB),
|
||||
#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
|
||||
#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
|
||||
.extratime1 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
|
||||
(CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
|
||||
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
|
||||
(CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
|
||||
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
|
||||
(CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
|
||||
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
|
||||
#endif
|
||||
.dram_addrw =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
|
||||
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
|
||||
SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
|
||||
SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
|
||||
((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
|
||||
((CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
|
||||
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
|
||||
.dram_if_width =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
|
||||
SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
|
||||
.dram_dev_width =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
|
||||
SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
|
||||
.dram_intr =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
|
||||
(CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
|
||||
SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
|
||||
.lowpwr_eq =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
|
||||
(CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
|
||||
SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
|
||||
.static_cfg =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
|
||||
(CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
|
||||
SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
|
||||
(CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
|
||||
SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
|
||||
.ctrl_width =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
|
||||
SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
|
||||
.cport_width =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
|
||||
SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
|
||||
.cport_wmap =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
|
||||
SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
|
||||
.cport_rmap =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
|
||||
SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
|
||||
.rfifo_cmap =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
|
||||
(CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
|
||||
SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
|
||||
.wfifo_cmap =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
|
||||
(CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
|
||||
SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
|
||||
.cport_rdwr =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
|
||||
(CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
|
||||
SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
|
||||
.port_cfg =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
|
||||
(CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
|
||||
SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
|
||||
.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
|
||||
.fpgaport_rst = CFG_HPS_SDR_CTRLCFG_FPGAPORTRST,
|
||||
.fifo_cfg =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
|
||||
(CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
|
||||
SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
|
||||
(CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
|
||||
SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
|
||||
.mp_priority =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
|
||||
SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
|
||||
.mp_weight0 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
|
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
|
||||
.mp_weight1 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
|
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
|
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
|
||||
.mp_weight2 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
|
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
|
||||
.mp_weight3 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
|
||||
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
|
||||
.mp_pacing0 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
|
||||
SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
|
||||
.mp_pacing1 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
|
||||
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
|
||||
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
|
||||
.mp_pacing2 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
|
||||
SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
|
||||
.mp_pacing3 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
|
||||
SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
|
||||
.mp_threshold0 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
|
||||
.mp_threshold1 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
|
||||
.mp_threshold2 =
|
||||
(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
|
||||
(CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
|
||||
.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
|
||||
.phy_ctrl0 = CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
|
||||
};
|
||||
|
||||
static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
|
||||
|
@ -202,7 +202,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
|
|||
.guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
|
||||
.idle_loop1 = RW_MGR_IDLE_LOOP1,
|
||||
.idle_loop2 = RW_MGR_IDLE_LOOP2,
|
||||
#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
|
||||
#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
|
||||
.emr = RW_MGR_EMR,
|
||||
.emr2 = RW_MGR_EMR2,
|
||||
.emr3 = RW_MGR_EMR3,
|
||||
|
@ -213,7 +213,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
|
|||
.mr_user = RW_MGR_MR_USER,
|
||||
.mr_dll_reset = RW_MGR_MR_DLL_RESET,
|
||||
.emr_ocd_enable = RW_MGR_EMR_OCD_ENABLE,
|
||||
#elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
|
||||
#elif (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
|
||||
.activate_1 = RW_MGR_ACTIVATE_1,
|
||||
.idle = RW_MGR_IDLE,
|
||||
.init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
|
||||
|
@ -287,7 +287,7 @@ static const struct socfpga_sdram_io_config io_config = {
|
|||
};
|
||||
|
||||
static const struct socfpga_sdram_misc_config misc_config = {
|
||||
#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
|
||||
#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
|
||||
.afi_clk_freq = AFI_CLK_FREQ,
|
||||
#endif
|
||||
.afi_rate_ratio = AFI_RATE_RATIO,
|
||||
|
|
|
@ -40,6 +40,10 @@ config HIGH_BATS
|
|||
Enable BATs (block address translation registers) 4-7 on machines
|
||||
that support them.
|
||||
|
||||
config SYS_INIT_RAM_LOCK
|
||||
bool "Lock some portion of L1 for initial ram stack"
|
||||
depends on MPC83xx || MPC85xx
|
||||
|
||||
source "arch/powerpc/cpu/mpc83xx/Kconfig"
|
||||
source "arch/powerpc/cpu/mpc85xx/Kconfig"
|
||||
source "arch/powerpc/cpu/mpc8xx/Kconfig"
|
||||
|
|
|
@ -113,6 +113,7 @@ config TARGET_P1010RDB_PA
|
|||
select BOARD_LATE_INIT if CHAIN_OF_TRUST
|
||||
select SUPPORT_SPL
|
||||
select SUPPORT_TPL
|
||||
select SYS_L2_SIZE_256KB
|
||||
imply CMD_EEPROM
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
@ -123,6 +124,7 @@ config TARGET_P1010RDB_PB
|
|||
select BOARD_LATE_INIT if CHAIN_OF_TRUST
|
||||
select SUPPORT_SPL
|
||||
select SUPPORT_TPL
|
||||
select SYS_L2_SIZE_256KB
|
||||
imply CMD_EEPROM
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
@ -132,6 +134,7 @@ config TARGET_P1020RDB_PC
|
|||
select SUPPORT_SPL
|
||||
select SUPPORT_TPL
|
||||
select ARCH_P1020
|
||||
select SYS_L2_SIZE_256KB
|
||||
imply CMD_EEPROM
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
@ -141,6 +144,7 @@ config TARGET_P1020RDB_PD
|
|||
select SUPPORT_SPL
|
||||
select SUPPORT_TPL
|
||||
select ARCH_P1020
|
||||
select SYS_L2_SIZE_256KB
|
||||
imply CMD_EEPROM
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
@ -150,6 +154,7 @@ config TARGET_P2020RDB
|
|||
select SUPPORT_SPL
|
||||
select SUPPORT_TPL
|
||||
select ARCH_P2020
|
||||
select SYS_L2_SIZE_512KB
|
||||
imply CMD_EEPROM
|
||||
imply CMD_SATA
|
||||
imply SATA_SIL
|
||||
|
@ -160,6 +165,7 @@ config TARGET_P2041RDB
|
|||
select BOARD_LATE_INIT if CHAIN_OF_TRUST
|
||||
select FSL_CORENET
|
||||
select PHYS_64BIT
|
||||
select SYS_L3_SIZE_1024KB
|
||||
imply CMD_SATA
|
||||
imply FSL_SATA
|
||||
|
||||
|
@ -177,6 +183,7 @@ config TARGET_T1024RDB
|
|||
select SUPPORT_SPL
|
||||
select PHYS_64BIT
|
||||
select FSL_DDR_INTERACTIVE
|
||||
select SYS_L3_SIZE_256KB
|
||||
imply CMD_EEPROM
|
||||
imply PANIC_HANG
|
||||
|
||||
|
@ -186,6 +193,7 @@ config TARGET_T1042RDB
|
|||
select BOARD_LATE_INIT if CHAIN_OF_TRUST
|
||||
select SUPPORT_SPL
|
||||
select PHYS_64BIT
|
||||
select SYS_L3_SIZE_256KB
|
||||
|
||||
config TARGET_T1042D4RDB
|
||||
bool "Support T1042D4RDB"
|
||||
|
@ -193,6 +201,7 @@ config TARGET_T1042D4RDB
|
|||
select BOARD_LATE_INIT if CHAIN_OF_TRUST
|
||||
select SUPPORT_SPL
|
||||
select PHYS_64BIT
|
||||
select SYS_L3_SIZE_256KB
|
||||
imply PANIC_HANG
|
||||
|
||||
config TARGET_T1042RDB_PI
|
||||
|
@ -201,6 +210,7 @@ config TARGET_T1042RDB_PI
|
|||
select BOARD_LATE_INIT if CHAIN_OF_TRUST
|
||||
select SUPPORT_SPL
|
||||
select PHYS_64BIT
|
||||
select SYS_L3_SIZE_256KB
|
||||
imply PANIC_HANG
|
||||
|
||||
config TARGET_T2080QDS
|
||||
|
@ -211,6 +221,7 @@ config TARGET_T2080QDS
|
|||
select PHYS_64BIT
|
||||
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
|
||||
select FSL_DDR_INTERACTIVE
|
||||
select SYS_L3_SIZE_512KB
|
||||
imply CMD_SATA
|
||||
|
||||
config TARGET_T2080RDB
|
||||
|
@ -219,6 +230,7 @@ config TARGET_T2080RDB
|
|||
select BOARD_LATE_INIT if CHAIN_OF_TRUST
|
||||
select SUPPORT_SPL
|
||||
select PHYS_64BIT
|
||||
select SYS_L3_SIZE_512KB
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
||||
|
@ -228,6 +240,7 @@ config TARGET_T4240RDB
|
|||
select SUPPORT_SPL
|
||||
select PHYS_64BIT
|
||||
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
|
||||
select SYS_L3_SIZE_512KB
|
||||
imply CMD_SATA
|
||||
imply PANIC_HANG
|
||||
|
||||
|
@ -239,6 +252,7 @@ config TARGET_KMCENT2
|
|||
bool "Support kmcent2"
|
||||
select VENDOR_KM
|
||||
select FSL_CORENET
|
||||
select SYS_L3_SIZE_256KB
|
||||
|
||||
endchoice
|
||||
|
||||
|
@ -1277,9 +1291,35 @@ config SYS_ETVPE_CLK
|
|||
default 1
|
||||
endif
|
||||
|
||||
config SYS_L2_SIZE_256KB
|
||||
bool
|
||||
|
||||
config SYS_L2_SIZE_512KB
|
||||
bool
|
||||
|
||||
config SYS_L2_SIZE
|
||||
int
|
||||
default 262144 if SYS_L2_SIZE_256KB
|
||||
default 524288 if SYS_L2_SIZE_512KB
|
||||
|
||||
config BACKSIDE_L2_CACHE
|
||||
bool
|
||||
|
||||
config SYS_L3_SIZE_256KB
|
||||
bool
|
||||
|
||||
config SYS_L3_SIZE_512KB
|
||||
bool
|
||||
|
||||
config SYS_L3_SIZE_1024KB
|
||||
bool
|
||||
|
||||
config SYS_L3_SIZE
|
||||
int
|
||||
default 262144 if SYS_L3_SIZE_256KB
|
||||
default 524288 if SYS_L3_SIZE_512KB
|
||||
default 1048576 if SYS_L3_SIZE_512KB
|
||||
|
||||
config SYS_PPC64
|
||||
bool
|
||||
|
||||
|
|
|
@ -76,7 +76,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
|
||||
|
|
|
@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
|
||||
|
|
|
@ -84,7 +84,7 @@ static void check_erratum_a4849(uint32_t svr)
|
|||
static void check_erratum_a4580(uint32_t svr)
|
||||
{
|
||||
const serdes_corenet_t __iomem *srds_regs =
|
||||
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
(void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
unsigned int lane;
|
||||
|
||||
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
|
||||
|
|
|
@ -59,7 +59,7 @@ int checkcpu (void)
|
|||
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
|
||||
defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
|
||||
ccsr_gur_t __iomem *gur =
|
||||
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
(void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
@ -98,7 +98,7 @@ int checkcpu (void)
|
|||
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
|
||||
if (SVR_SOC_VER(svr) == SVR_T4080) {
|
||||
ccsr_rcpm_t *rcpm =
|
||||
(void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
|
||||
(void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
|
||||
|
||||
setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
|
||||
FSL_CORENET_DEVDISR2_DTSEC1_9);
|
||||
|
@ -124,7 +124,7 @@ int checkcpu (void)
|
|||
puts("Unicore software on multiprocessor system!!\n"
|
||||
"To enable mutlticore build define CONFIG_MP\n");
|
||||
#endif
|
||||
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
|
||||
volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
|
||||
printf("CPU%d: ", pic->whoami);
|
||||
} else {
|
||||
puts("CPU: ");
|
||||
|
@ -319,7 +319,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
|||
val |= 0x70000000;
|
||||
mtspr(DBCR0,val);
|
||||
#else
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
||||
/* Call board-specific preparation for reset */
|
||||
board_reset_prepare();
|
||||
|
@ -436,7 +436,7 @@ int dram_init(void)
|
|||
|
||||
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
unsigned int x = 10;
|
||||
unsigned int i;
|
||||
|
||||
|
@ -540,16 +540,16 @@ static void dump_spd_ddr_reg(void)
|
|||
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR;
|
||||
break;
|
||||
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
|
||||
#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
|
||||
case 1:
|
||||
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
|
||||
ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR;
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
|
||||
#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
|
||||
case 2:
|
||||
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
||||
ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR;
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
|
||||
|
|
|
@ -160,7 +160,7 @@ void disable_cpc_sram(void)
|
|||
{
|
||||
int i;
|
||||
|
||||
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
|
||||
cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
|
||||
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
|
||||
|
@ -217,7 +217,7 @@ void enable_cpc(void)
|
|||
char cpc_subarg[16];
|
||||
bool have_hwconfig = false;
|
||||
int cpc_args = 0;
|
||||
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
|
||||
cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
|
||||
|
||||
/* Extract hwconfig from environment */
|
||||
ret = env_get_f("hwconfig", buffer, sizeof(buffer));
|
||||
|
@ -271,7 +271,7 @@ void enable_cpc(void)
|
|||
static void invalidate_cpc(void)
|
||||
{
|
||||
int i;
|
||||
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
|
||||
cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
|
||||
/* skip CPC when it used as all SRAM */
|
||||
|
@ -300,9 +300,9 @@ static void invalidate_cpc(void)
|
|||
static void corenet_tb_init(void)
|
||||
{
|
||||
volatile ccsr_rcpm_t *rcpm =
|
||||
(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
|
||||
(void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
|
||||
volatile ccsr_pic_t *pic =
|
||||
(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
|
||||
(void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
|
||||
u32 whoami = in_be32(&pic->whoami);
|
||||
|
||||
/* Enable the timebase register for this core */
|
||||
|
@ -313,7 +313,7 @@ static void corenet_tb_init(void)
|
|||
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
|
||||
void fsl_erratum_a007212_workaround(void)
|
||||
{
|
||||
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 ddr_pll_ratio;
|
||||
u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
|
||||
u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
|
||||
|
@ -379,13 +379,13 @@ ulong cpu_init_f(void)
|
|||
{
|
||||
extern void m8560_cpm_reset (void);
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
#endif
|
||||
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
|
||||
struct law_entry law;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_MPC8548
|
||||
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
|
||||
ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
|
||||
uint svr = get_svr();
|
||||
|
||||
/*
|
||||
|
@ -455,7 +455,7 @@ int enable_cluster_l2(void)
|
|||
{
|
||||
int i = 0;
|
||||
u32 cluster, svr = get_svr();
|
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
struct ccsr_cluster_l2 __iomem *l2cache;
|
||||
|
||||
/* only the L2 of first cluster should be enabled as expected on T4080,
|
||||
|
@ -476,7 +476,7 @@ int enable_cluster_l2(void)
|
|||
do {
|
||||
int j, cluster_valid = 0;
|
||||
|
||||
l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
|
||||
l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
|
||||
|
||||
cluster = in_be32(&gur->tp_cluster[i].lower);
|
||||
|
||||
|
@ -516,9 +516,9 @@ int l2cache_init(void)
|
|||
{
|
||||
__maybe_unused u32 svr = get_svr();
|
||||
#ifdef CONFIG_L2_CACHE
|
||||
ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
|
||||
ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
|
||||
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
|
||||
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
|
||||
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2;
|
||||
#endif
|
||||
|
||||
puts ("L2: ");
|
||||
|
@ -664,7 +664,7 @@ int cpu_init_r(void)
|
|||
const char *spin;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
|
||||
ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
|
||||
ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
|
||||
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
|
||||
|
@ -821,7 +821,7 @@ int cpu_init_r(void)
|
|||
#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
{
|
||||
struct ccsr_usb_phy __iomem *usb_phy1 =
|
||||
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
|
||||
(void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
if (has_erratum_a006261())
|
||||
fsl_erratum_a006261_workaround(usb_phy1);
|
||||
|
@ -833,7 +833,7 @@ int cpu_init_r(void)
|
|||
#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
||||
{
|
||||
struct ccsr_usb_phy __iomem *usb_phy2 =
|
||||
(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
|
||||
(void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR;
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
||||
if (has_erratum_a006261())
|
||||
fsl_erratum_a006261_workaround(usb_phy2);
|
||||
|
@ -859,7 +859,7 @@ int cpu_init_r(void)
|
|||
|
||||
#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
|
||||
struct ccsr_usb_phy __iomem *usb_phy =
|
||||
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
|
||||
(void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
|
||||
setbits_be32(&usb_phy->pllprg[1],
|
||||
CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
|
||||
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
|
||||
|
@ -928,11 +928,11 @@ int cpu_init_r(void)
|
|||
fsl_sata_reg_t *reg;
|
||||
|
||||
/* first SATA controller */
|
||||
reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
|
||||
reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR;
|
||||
clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
|
||||
|
||||
/* second SATA controller */
|
||||
reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
|
||||
reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR;
|
||||
clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -85,10 +85,10 @@ void cpu_init_early_f(void *fdt)
|
|||
{
|
||||
u32 mas0, mas1, mas2, mas3, mas7;
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
#endif
|
||||
#ifdef CONFIG_A003399_NOR_WORKAROUND
|
||||
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
|
||||
ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
|
||||
u32 *dst, *src;
|
||||
void (*setup_ifc_sram)(void);
|
||||
int i;
|
||||
|
|
|
@ -164,7 +164,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
|
|||
static inline void ft_fixup_l3cache(void *blob, int off)
|
||||
{
|
||||
u32 line_size, num_ways, size, num_sets;
|
||||
cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
|
||||
cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR;
|
||||
u32 cfg0 = in_be32(&cpc->cpccfg0);
|
||||
|
||||
size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
|
||||
|
@ -222,7 +222,7 @@ static inline void ft_fixup_l2cache_compatible(void *blob, int off)
|
|||
/* return size in kilobytes */
|
||||
static inline u32 l2cache_size(void)
|
||||
{
|
||||
volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
|
||||
volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
|
||||
volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
|
||||
u32 ver = SVR_SOC_VER(get_svr());
|
||||
|
||||
|
@ -299,7 +299,7 @@ static inline void ft_fixup_l2cache(void *blob)
|
|||
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
|
||||
#else
|
||||
struct ccsr_cluster_l2 *l2cache =
|
||||
(struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
|
||||
(struct ccsr_cluster_l2 __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2);
|
||||
u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
|
||||
#endif
|
||||
u32 size, line_size, num_ways, num_sets;
|
||||
|
@ -466,11 +466,11 @@ static void ft_fixup_dpaa_clks(void *blob)
|
|||
|
||||
get_sys_info(&sysinfo);
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
|
||||
ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET,
|
||||
sysinfo.freq_fman[0]);
|
||||
|
||||
#if (CONFIG_SYS_NUM_FMAN == 2)
|
||||
ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
|
||||
ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET,
|
||||
sysinfo.freq_fman[1]);
|
||||
#endif
|
||||
#endif
|
||||
|
@ -509,7 +509,7 @@ static void ft_fixup_qe_snum(void *blob)
|
|||
#if defined(CONFIG_ARCH_P4080)
|
||||
static void fdt_fixup_usb(void *fdt)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
|
||||
int off;
|
||||
|
||||
|
@ -532,7 +532,7 @@ void fdt_fixup_dma3(void *blob)
|
|||
{
|
||||
/* the 3rd DMA is not functional if SRIO2 is chosen */
|
||||
int nodeoff;
|
||||
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
||||
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
|
||||
#if defined(CONFIG_ARCH_T2080)
|
||||
|
@ -611,7 +611,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
|
|||
else {
|
||||
ccsr_sec_t __iomem *sec;
|
||||
|
||||
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
|
||||
sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
|
||||
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -21,10 +21,10 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
|
|||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_3
|
||||
#ifdef CFG_SYS_FSL_SRDS_3
|
||||
static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_4
|
||||
#ifdef CFG_SYS_FSL_SRDS_4
|
||||
static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
|
||||
#endif
|
||||
|
||||
|
@ -104,13 +104,13 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
|
||||
ret |= serdes2_prtcl_map[device];
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_3
|
||||
#ifdef CFG_SYS_FSL_SRDS_3
|
||||
if (!serdes3_prtcl_map[NONE])
|
||||
fsl_serdes_init();
|
||||
|
||||
ret |= serdes3_prtcl_map[device];
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_4
|
||||
#ifdef CFG_SYS_FSL_SRDS_4
|
||||
if (!serdes4_prtcl_map[NONE])
|
||||
fsl_serdes_init();
|
||||
|
||||
|
@ -122,7 +122,7 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
||||
{
|
||||
const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 cfg = in_be32(&gur->rcwsr[4]);
|
||||
int i;
|
||||
|
||||
|
@ -139,13 +139,13 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
|||
cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_3
|
||||
#ifdef CFG_SYS_FSL_SRDS_3
|
||||
case FSL_SRDS_3:
|
||||
cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
|
||||
cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_4
|
||||
#ifdef CFG_SYS_FSL_SRDS_4
|
||||
case FSL_SRDS_4:
|
||||
cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
|
||||
cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
|
||||
|
@ -193,7 +193,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
|
|||
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
|
||||
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
|
||||
{
|
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 cfg;
|
||||
int lane;
|
||||
|
||||
|
@ -351,28 +351,28 @@ void fsl_serdes_init(void)
|
|||
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
serdes_init(FSL_SRDS_1,
|
||||
CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
|
||||
CFG_SYS_FSL_CORENET_SERDES_ADDR,
|
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
|
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
|
||||
serdes1_prtcl_map);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
serdes_init(FSL_SRDS_2,
|
||||
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
|
||||
CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
|
||||
FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
|
||||
FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
|
||||
serdes2_prtcl_map);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_3
|
||||
#ifdef CFG_SYS_FSL_SRDS_3
|
||||
serdes_init(FSL_SRDS_3,
|
||||
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
|
||||
CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
|
||||
FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
|
||||
FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
|
||||
serdes3_prtcl_map);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_4
|
||||
#ifdef CFG_SYS_FSL_SRDS_4
|
||||
serdes_init(FSL_SRDS_4,
|
||||
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
|
||||
CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
|
||||
FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
|
||||
FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
|
||||
serdes4_prtcl_map);
|
||||
|
|
|
@ -108,8 +108,8 @@ int serdes_get_bank_by_lane(int lane)
|
|||
|
||||
int serdes_lane_enabled(int lane)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
|
||||
int bank = lanes[lane].bank;
|
||||
int word = lanes[lane].lpd / 32;
|
||||
|
@ -133,7 +133,7 @@ int serdes_lane_enabled(int lane)
|
|||
|
||||
int is_serdes_configured(enum srds_prtcl device)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
||||
/* Is serdes enabled at all? */
|
||||
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
|
||||
|
@ -169,7 +169,7 @@ int serdes_get_first_lane(enum srds_prtcl device)
|
|||
u32 prtcl;
|
||||
const ccsr_gur_t *gur;
|
||||
|
||||
gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
/* Is serdes enabled at all? */
|
||||
if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
|
||||
|
@ -251,13 +251,13 @@ void serdes_reset_rx(enum srds_prtcl device)
|
|||
if (unlikely(device == NONE))
|
||||
return;
|
||||
|
||||
gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
/* Is serdes enabled at all? */
|
||||
if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
|
||||
return;
|
||||
|
||||
regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
regs = (typeof(regs))CFG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
|
||||
|
||||
__serdes_reset_rx(regs, prtcl, device);
|
||||
|
@ -466,7 +466,7 @@ static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
|
|||
static void wait_for_rstdone(unsigned int bank)
|
||||
{
|
||||
serdes_corenet_t *srds_regs =
|
||||
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
(void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
unsigned long long end_tick;
|
||||
u32 rstctl;
|
||||
|
||||
|
@ -491,7 +491,7 @@ void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
int cfg;
|
||||
serdes_corenet_t *srds_regs;
|
||||
#ifdef CONFIG_ARCH_P5040
|
||||
|
@ -527,7 +527,7 @@ void fsl_serdes_init(void)
|
|||
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
|
||||
return;
|
||||
|
||||
srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
|
||||
srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
|
||||
cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
|
||||
debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
|
||||
|
||||
|
@ -601,7 +601,7 @@ void fsl_serdes_init(void)
|
|||
serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
|
||||
break;
|
||||
default:
|
||||
srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
|
||||
srds2_regs = (void *)CFG_SYS_FSL_CORENET_SERDES2_ADDR;
|
||||
|
||||
/* We don't need bank 4, so power it down */
|
||||
setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
void interrupt_init_cpu(unsigned *decrementer_count)
|
||||
{
|
||||
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
|
||||
ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
/*
|
||||
|
|
|
@ -76,7 +76,7 @@ static void set_fman_liodn(struct fman_liodn_id_table *tbl, int size)
|
|||
|
||||
static void setup_sec_liodn_base(void)
|
||||
{
|
||||
ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
|
||||
ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
|
||||
u32 base;
|
||||
|
||||
if (!IS_E_PROCESSOR(get_svr()))
|
||||
|
@ -101,12 +101,12 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
|
|||
|
||||
switch(dev) {
|
||||
case FSL_HW_PORTAL_FMAN1:
|
||||
fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
|
||||
fm = (void *)CFG_SYS_FSL_FM1_ADDR;
|
||||
break;
|
||||
|
||||
#if (CONFIG_SYS_NUM_FMAN == 2)
|
||||
case FSL_HW_PORTAL_FMAN2:
|
||||
fm = (void *)CONFIG_SYS_FSL_FM2_ADDR;
|
||||
fm = (void *)CFG_SYS_FSL_FM2_ADDR;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
|
@ -130,7 +130,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
|
|||
static void setup_pme_liodn_base(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_DPAA_PME
|
||||
ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
|
||||
ccsr_pme_t *pme = (void *)CFG_SYS_FSL_CORENET_PME_ADDR;
|
||||
u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) |
|
||||
liodn_bases[FSL_HW_PORTAL_PME].id[1];
|
||||
|
||||
|
@ -141,7 +141,7 @@ static void setup_pme_liodn_base(void)
|
|||
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
|
||||
static void setup_raide_liodn_base(void)
|
||||
{
|
||||
struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR;
|
||||
struct ccsr_raide *raide = (void *)CFG_SYS_FSL_RAID_ENGINE_ADDR;
|
||||
|
||||
/* setup raid engine liodn base for data/desc ; both set to 47 */
|
||||
u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) |
|
||||
|
@ -155,7 +155,7 @@ static void setup_raide_liodn_base(void)
|
|||
static void set_rman_liodn(struct liodn_id_table *tbl, int size)
|
||||
{
|
||||
int i;
|
||||
struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
|
||||
struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
/* write the RMan block number */
|
||||
|
@ -168,7 +168,7 @@ static void set_rman_liodn(struct liodn_id_table *tbl, int size)
|
|||
static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size)
|
||||
{
|
||||
int i;
|
||||
struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
|
||||
struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
|
||||
u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0];
|
||||
|
||||
out_be32(&rman->mmliodnbr, base);
|
||||
|
|
|
@ -50,7 +50,7 @@ int hold_cores_in_reset(int verbose)
|
|||
|
||||
int cpu_reset(u32 nr)
|
||||
{
|
||||
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
|
||||
volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
|
||||
out_be32(&pic->pir, 1 << nr);
|
||||
/* the dummy read works around an errata on early 85xx MP PICs */
|
||||
(void)in_be32(&pic->pir);
|
||||
|
@ -87,7 +87,7 @@ int cpu_status(u32 nr)
|
|||
#ifdef CONFIG_FSL_CORENET
|
||||
int cpu_disable(u32 nr)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
||||
setbits_be32(&gur->coredisrl, 1 << nr);
|
||||
|
||||
|
@ -95,7 +95,7 @@ int cpu_disable(u32 nr)
|
|||
}
|
||||
|
||||
int is_core_disabled(int nr) {
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 coredisrl = in_be32(&gur->coredisrl);
|
||||
|
||||
return (coredisrl & (1 << nr));
|
||||
|
@ -103,7 +103,7 @@ int is_core_disabled(int nr) {
|
|||
#else
|
||||
int cpu_disable(u32 nr)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
||||
switch (nr) {
|
||||
case 0:
|
||||
|
@ -121,7 +121,7 @@ int cpu_disable(u32 nr)
|
|||
}
|
||||
|
||||
int is_core_disabled(int nr) {
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 devdisr = in_be32(&gur->devdisr);
|
||||
|
||||
switch (nr) {
|
||||
|
@ -264,10 +264,10 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
|
|||
u32 mask = cpu_mask();
|
||||
struct law_entry e;
|
||||
|
||||
gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
|
||||
rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
|
||||
pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
|
||||
gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR);
|
||||
rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
|
||||
pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
|
||||
|
||||
whoami = in_be32(&pic->whoami);
|
||||
cpu_up_mask = 1 << whoami;
|
||||
|
@ -336,9 +336,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
|
|||
u32 up, cpu_up_mask, whoami;
|
||||
u32 *table = (u32 *)&__spin_table;
|
||||
volatile u32 bpcr;
|
||||
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
|
||||
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
|
||||
u32 devdisr;
|
||||
int timeout = 10;
|
||||
|
||||
|
|
|
@ -89,8 +89,8 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
|
||||
void *guts = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
void *sd = (void *)CFG_SYS_MPC85xx_SERDES2_ADDR;
|
||||
u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
|
||||
u32 srds1_io_sel, srds2_io_sel;
|
||||
u32 tmp;
|
||||
|
|
|
@ -52,7 +52,7 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
|
||||
|
|
|
@ -32,7 +32,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
|
||||
|
|
|
@ -51,7 +51,7 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
|
||||
|
|
|
@ -50,8 +50,8 @@ int is_serdes_configured(enum srds_prtcl prtcl)
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85xx_SERDES1_ADDR;
|
||||
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
|
|
|
@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
|
||||
|
|
|
@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
|
|||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
|
||||
|
|
|
@ -20,7 +20,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
|
|||
u32 pin_2bit_assign;
|
||||
u32 pin_1bit_mask;
|
||||
u32 tmp_val;
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile par_io_t *par_io = (volatile par_io_t *)
|
||||
&(gur->qe_par_io);
|
||||
|
||||
|
|
|
@ -24,16 +24,16 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
void get_sys_info(sys_info_t *sys_info)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
#ifdef CONFIG_FSL_CORENET
|
||||
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
|
||||
volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
|
||||
unsigned int cpu;
|
||||
#ifdef CONFIG_HETROGENOUS_CLUSTERS
|
||||
unsigned int dsp_cpu;
|
||||
uint rcw_tmp1, rcw_tmp2;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
|
||||
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
|
||||
int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
|
||||
#endif
|
||||
__maybe_unused u32 svr;
|
||||
|
||||
|
@ -575,7 +575,7 @@ int get_clocks(void)
|
|||
{
|
||||
sys_info_t sys_info;
|
||||
#ifdef CONFIG_ARCH_MPC8544
|
||||
volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR;
|
||||
#endif
|
||||
get_sys_info (&sys_info);
|
||||
gd->cpu_clk = sys_info.freq_processor[0];
|
||||
|
|
|
@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
ulong cpu_init_f(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_INIT_L2_ADDR
|
||||
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
|
||||
ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
|
||||
|
||||
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
|
||||
|
||||
|
|
|
@ -80,7 +80,7 @@
|
|||
|
||||
/* Definitions from C header file asm/immap_85xx.h */
|
||||
|
||||
#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
|
||||
#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000
|
||||
|
||||
#define MPC85xx_L2CTL 0x000
|
||||
#define MPC85xx_L2CTL_L2E 0x80000000
|
||||
|
@ -127,13 +127,13 @@ bootsect:
|
|||
.org 0x80 /* Start of configuration */
|
||||
.Lconf_pair_start:
|
||||
|
||||
.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
|
||||
.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
|
||||
.long CONFIG_SYS_INIT_L2_ADDR
|
||||
|
||||
.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
|
||||
.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
|
||||
.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
|
||||
|
||||
.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
|
||||
.long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
|
||||
.long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE
|
||||
|
||||
.long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */
|
||||
|
@ -966,7 +966,7 @@ delete_ccsr_l2_tlb:
|
|||
erratum_set_dcsr 0xb0e38 0xe0400000
|
||||
erratum_set_dcsr 0xb0008 0x00900000
|
||||
erratum_set_dcsr 0xb0e40 0xe00a0000
|
||||
erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
|
||||
erratum_set_ccsr 0x18600 CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
erratum_set_ccsr 0x10f00 0x495e5000
|
||||
#else
|
||||
|
|
|
@ -260,7 +260,7 @@ void UnknownException(struct pt_regs *regs)
|
|||
|
||||
void ExtIntException(struct pt_regs *regs)
|
||||
{
|
||||
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
|
||||
volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
|
||||
|
||||
uint vect;
|
||||
|
||||
|
|
|
@ -104,7 +104,7 @@ static struct cpu_type cpu_type_list[] = {
|
|||
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
|
||||
static inline u32 init_type(u32 cluster, int init_id)
|
||||
{
|
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
|
||||
u32 type = in_be32(&gur->tp_ityp[idx]);
|
||||
|
||||
|
@ -116,7 +116,7 @@ static inline u32 init_type(u32 cluster, int init_id)
|
|||
|
||||
u32 compute_ppc_cpumask(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
int i = 0, count = 0;
|
||||
u32 cluster, type, mask = 0;
|
||||
|
||||
|
@ -140,7 +140,7 @@ u32 compute_ppc_cpumask(void)
|
|||
#ifdef CONFIG_HETROGENOUS_CLUSTERS
|
||||
u32 compute_dsp_cpumask(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
int i = CONFIG_DSP_CLUSTER_START, count = 0;
|
||||
u32 cluster, type, dsp_mask = 0;
|
||||
|
||||
|
@ -163,7 +163,7 @@ u32 compute_dsp_cpumask(void)
|
|||
|
||||
int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
|
||||
{
|
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
int count = 0, i = CONFIG_DSP_CLUSTER_START;
|
||||
u32 cluster;
|
||||
|
||||
|
@ -186,7 +186,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
|
|||
|
||||
int fsl_qoriq_core_to_cluster(unsigned int core)
|
||||
{
|
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
|
||||
int i = 0, count = 0;
|
||||
u32 cluster;
|
||||
|
||||
|
@ -235,7 +235,7 @@ struct cpu_type *identify_cpu(u32 ver)
|
|||
*/
|
||||
__weak u32 cpu_mask(void)
|
||||
{
|
||||
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
|
||||
ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
|
||||
struct cpu_type *cpu = gd->arch.cpu;
|
||||
|
||||
/* better to query feature reporting register than just assume 1 */
|
||||
|
@ -252,7 +252,7 @@ __weak u32 cpu_mask(void)
|
|||
#ifdef CONFIG_HETROGENOUS_CLUSTERS
|
||||
__weak u32 cpu_dsp_mask(void)
|
||||
{
|
||||
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
|
||||
ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
|
||||
struct cpu_type *cpu = gd->arch.cpu;
|
||||
|
||||
/* better to query feature reporting register than just assume 1 */
|
||||
|
|
|
@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
|
||||
|
||||
#ifdef CONFIG_FSL_CORENET
|
||||
#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
|
||||
#define LAW_BASE (CFG_SYS_FSL_CORENET_CCM_ADDR)
|
||||
#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
|
||||
#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
|
||||
#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
|
||||
|
@ -301,7 +301,7 @@ void init_laws(void)
|
|||
|
||||
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
|
||||
/* check RCW to get which port is used for boot */
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
|
||||
u32 bootloc = in_be32(&gur->rcwsr[6]);
|
||||
/*
|
||||
* in SRIO or PCIE boot we need to set specail LAWs for
|
||||
|
|
|
@ -33,12 +33,12 @@
|
|||
#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
|
||||
#endif
|
||||
#define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
|
||||
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
|
||||
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
|
||||
#elif defined(CONFIG_MPC85xx)
|
||||
#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
|
||||
#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
|
||||
#define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
|
||||
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
|
||||
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
|
||||
#elif defined(CONFIG_MPC86xx)
|
||||
#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
|
||||
#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
|
||||
|
@ -79,9 +79,9 @@ static int srio_erratum_a004034(u8 port)
|
|||
int idx, first, last;
|
||||
u32 i;
|
||||
unsigned long long end_tick;
|
||||
struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
|
||||
struct ccsr_rio *srio_regs = (void *)CFG_SYS_FSL_SRIO_ADDR;
|
||||
|
||||
srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
|
||||
srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
|
||||
conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
|
||||
>> (12 - port * 4)) & 0x3;
|
||||
init_lane = (in_be32((void *)&srio_regs->lp_serial
|
||||
|
@ -291,7 +291,7 @@ void srio_init(void)
|
|||
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
|
||||
void srio_boot_master(int port)
|
||||
{
|
||||
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
|
||||
struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
|
||||
|
||||
/* set port accept-all */
|
||||
out_be32((void *)&srio->impl.port[port - 1].ptaacr,
|
||||
|
@ -343,7 +343,7 @@ void srio_boot_master(int port)
|
|||
|
||||
void srio_boot_master_release_slave(int port)
|
||||
{
|
||||
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
|
||||
struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
|
||||
u32 escsr;
|
||||
debug("SRIOBOOT - MASTER: "
|
||||
"Check the port status and release slave core ...\n");
|
||||
|
|
|
@ -45,9 +45,7 @@ extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
|
|||
extern void flush_dcache(void);
|
||||
extern void invalidate_dcache(void);
|
||||
extern void invalidate_icache(void);
|
||||
#ifdef CONFIG_SYS_INIT_RAM_LOCK
|
||||
extern void unlock_ram_in_cache(void);
|
||||
#endif /* CONFIG_SYS_INIT_RAM_LOCK */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
|
||||
|
|
|
@ -17,10 +17,10 @@
|
|||
#include <fsl_ddrc_version.h>
|
||||
|
||||
#if defined(CONFIG_ARCH_MPC8548)
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
#define CFG_SYS_FSL_SRIO_MAX_PORTS 1
|
||||
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
|
||||
#elif defined(CONFIG_ARCH_P1010)
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
|
@ -59,30 +59,30 @@
|
|||
#define QE_NUM_OF_SNUM 28
|
||||
|
||||
#elif defined(CONFIG_ARCH_P2020)
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
|
||||
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
|
||||
#elif defined(CONFIG_ARCH_P3041)
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
|
||||
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
|
||||
#define CONFIG_SYS_NUM_FMAN 2
|
||||
|
@ -91,11 +91,11 @@
|
|||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
|
||||
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
|
||||
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
|
||||
|
||||
#elif defined(CONFIG_ARCH_P5040)
|
||||
#define CONFIG_SYS_NUM_FMAN 2
|
||||
|
@ -104,7 +104,7 @@
|
|||
#define CONFIG_SYS_NUM_FM2_DTSEC 5
|
||||
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
|
||||
|
||||
#elif defined(CONFIG_ARCH_BSC9131)
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
|
@ -118,7 +118,7 @@
|
|||
|
||||
#elif defined(CONFIG_ARCH_T4240)
|
||||
#ifdef CONFIG_ARCH_T4240
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
|
||||
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
||||
#define CONFIG_SYS_NUM_FM2_DTSEC 8
|
||||
|
@ -131,17 +131,17 @@
|
|||
#endif
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_FSL_SRDS_3
|
||||
#define CONFIG_SYS_FSL_SRDS_4
|
||||
#define CFG_SYS_FSL_SRDS_3
|
||||
#define CFG_SYS_FSL_SRDS_4
|
||||
#define CONFIG_SYS_NUM_FMAN 2
|
||||
#define CONFIG_SYS_PME_CLK 0
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_SYS_FM1_CLK 3
|
||||
#define CONFIG_SYS_FM2_CLK 3
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
|
||||
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
|
@ -154,21 +154,21 @@
|
|||
#ifdef CONFIG_ARCH_B4860
|
||||
#define CONFIG_MAX_DSP_CPUS 12
|
||||
#define CONFIG_NUM_DSP_CPUS 6
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#else
|
||||
#define CONFIG_MAX_DSP_CPUS 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
|
||||
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 4
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 0
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
||||
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 5
|
||||
|
@ -184,8 +184,7 @@
|
|||
#define QE_NUM_OF_SNUM 28
|
||||
|
||||
#elif defined(CONFIG_ARCH_T1024)
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
||||
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 4
|
||||
|
@ -202,15 +201,15 @@
|
|||
|
||||
#elif defined(CONFIG_ARCH_T2080)
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#if defined(CONFIG_ARCH_T2080)
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 4
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#endif
|
||||
#define CONFIG_PME_PLAT_CLK_DIV 1
|
||||
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
|
||||
|
@ -224,7 +223,7 @@
|
|||
#define CONFIG_FSL_SDHC_V2_3
|
||||
#define CONFIG_TSECV2_1
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
|
||||
#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
@ -18,22 +18,22 @@ struct srio_liodn_id_table {
|
|||
#define SET_SRIO_LIODN_1(port, idA) \
|
||||
{ .id = { idA }, .num_ids = 1, .portid = port, \
|
||||
.reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
|
||||
+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
|
||||
+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
|
||||
}
|
||||
|
||||
#define SET_SRIO_LIODN_2(port, idA, idB) \
|
||||
{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
|
||||
.reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
|
||||
+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
|
||||
+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
|
||||
.reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
|
||||
+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
|
||||
+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
|
||||
}
|
||||
|
||||
#define SET_SRIO_LIODN_BASE(port, id_a) \
|
||||
{ .id = { id_a }, .num_ids = 1, .portid = port, \
|
||||
.reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
|
||||
+ (port - 1) * 0x200 \
|
||||
+ CONFIG_SYS_FSL_SRIO_ADDR, \
|
||||
+ CFG_SYS_FSL_SRIO_ADDR, \
|
||||
}
|
||||
|
||||
struct liodn_id_table {
|
||||
|
@ -90,69 +90,69 @@ extern void fdt_fixup_liodn(void *blob);
|
|||
|
||||
#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
|
||||
SET_LIODN_ENTRY_1(compat, liodn, \
|
||||
offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
|
||||
offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \
|
||||
compatoff)
|
||||
|
||||
#define SET_USB_LIODN(usbNum, compat, liodn) \
|
||||
SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
|
||||
CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
|
||||
CFG_SYS_MPC85xx_USB##usbNum##_OFFSET)
|
||||
|
||||
#define SET_SATA_LIODN(sataNum, liodn) \
|
||||
SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
|
||||
CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
|
||||
CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
|
||||
|
||||
#define SET_PCI_LIODN(compat, pciNum, liodn) \
|
||||
SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
|
||||
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
|
||||
CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
|
||||
|
||||
#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
|
||||
SET_LIODN_ENTRY_1(compat, liodn,\
|
||||
offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
|
||||
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
|
||||
offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
|
||||
CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
|
||||
|
||||
/* reg nodes for DMA start @ 0x300 */
|
||||
#define SET_DMA_LIODN(dmaNum, compat, liodn) \
|
||||
SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
|
||||
CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
|
||||
CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
|
||||
|
||||
#define SET_SDHC_LIODN(sdhcNum, liodn) \
|
||||
SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
|
||||
CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
|
||||
CFG_SYS_MPC85xx_ESDHC_OFFSET)
|
||||
|
||||
#define SET_QE_LIODN(liodn) \
|
||||
SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
|
||||
CONFIG_SYS_MPC85xx_QE_OFFSET)
|
||||
CFG_SYS_MPC85xx_QE_OFFSET)
|
||||
|
||||
#define SET_TDM_LIODN(liodn) \
|
||||
SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
|
||||
CONFIG_SYS_MPC85xx_TDM_OFFSET)
|
||||
CFG_SYS_MPC85xx_TDM_OFFSET)
|
||||
|
||||
#define SET_QMAN_LIODN(liodn) \
|
||||
SET_LIODN_ENTRY_1("fsl,qman", liodn, \
|
||||
offsetof(struct ccsr_qman, liodnr) + \
|
||||
CONFIG_SYS_FSL_QMAN_OFFSET, \
|
||||
CONFIG_SYS_FSL_QMAN_OFFSET)
|
||||
CFG_SYS_FSL_QMAN_OFFSET, \
|
||||
CFG_SYS_FSL_QMAN_OFFSET)
|
||||
|
||||
#define SET_BMAN_LIODN(liodn) \
|
||||
SET_LIODN_ENTRY_1("fsl,bman", liodn, \
|
||||
offsetof(struct ccsr_bman, liodnr) + \
|
||||
CONFIG_SYS_FSL_BMAN_OFFSET, \
|
||||
CONFIG_SYS_FSL_BMAN_OFFSET)
|
||||
CFG_SYS_FSL_BMAN_OFFSET, \
|
||||
CFG_SYS_FSL_BMAN_OFFSET)
|
||||
|
||||
#define SET_PME_LIODN(liodn) \
|
||||
SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
|
||||
CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
|
||||
CONFIG_SYS_FSL_CORENET_PME_OFFSET)
|
||||
CFG_SYS_FSL_CORENET_PME_OFFSET, \
|
||||
CFG_SYS_FSL_CORENET_PME_OFFSET)
|
||||
|
||||
#define SET_PMAN_LIODN(num, liodn) \
|
||||
SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
|
||||
offsetof(struct ccsr_pman, ppa1) + \
|
||||
CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
|
||||
CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
|
||||
CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
|
||||
CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
|
||||
|
||||
/* -1 from portID due to how immap has the registers */
|
||||
#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
|
||||
CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
|
||||
CFG_SYS_FSL_FM##fmNum##_OFFSET + \
|
||||
offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
|
||||
|
||||
#ifdef CONFIG_SYS_FMAN_V3
|
||||
|
@ -160,31 +160,31 @@ extern void fdt_fixup_liodn(void *blob);
|
|||
#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
|
||||
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
|
||||
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
|
||||
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
|
||||
CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
|
||||
|
||||
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
|
||||
#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
|
||||
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
|
||||
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
|
||||
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
|
||||
CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
|
||||
|
||||
/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
|
||||
#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
|
||||
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
|
||||
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
|
||||
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
|
||||
CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
|
||||
#else
|
||||
/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
|
||||
#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
|
||||
SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
|
||||
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
|
||||
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
|
||||
CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
|
||||
|
||||
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
|
||||
#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
|
||||
SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
|
||||
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
|
||||
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
|
||||
CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
|
||||
#endif
|
||||
/*
|
||||
* handle both old and new versioned SEC properties:
|
||||
|
@ -193,44 +193,44 @@ extern void fdt_fixup_liodn(void *blob);
|
|||
#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
|
||||
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
|
||||
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
|
||||
CFG_SYS_FSL_SEC_OFFSET, \
|
||||
CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
|
||||
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
|
||||
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
|
||||
CFG_SYS_FSL_SEC_OFFSET, \
|
||||
CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
|
||||
|
||||
/* This is a bit evil since we treat rtic param as both a string & hex value */
|
||||
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
|
||||
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
|
||||
liodnA, \
|
||||
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
|
||||
CFG_SYS_FSL_SEC_OFFSET, \
|
||||
CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
|
||||
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
|
||||
liodnA, \
|
||||
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
|
||||
CFG_SYS_FSL_SEC_OFFSET, \
|
||||
CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
|
||||
|
||||
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
|
||||
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
|
||||
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
|
||||
CONFIG_SYS_FSL_SEC_OFFSET, 0)
|
||||
CFG_SYS_FSL_SEC_OFFSET, 0)
|
||||
|
||||
#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
|
||||
SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
|
||||
liodnA, \
|
||||
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
|
||||
CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
|
||||
CFG_SYS_FSL_RAID_ENGINE_OFFSET, \
|
||||
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
|
||||
CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
|
||||
CFG_SYS_FSL_RAID_ENGINE_OFFSET)
|
||||
|
||||
#define SET_RMAN_LIODN(ibNum, liodn) \
|
||||
SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
|
||||
offsetof(struct ccsr_rman, mmitdr) + \
|
||||
CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \
|
||||
CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
|
||||
CFG_SYS_FSL_CORENET_RMAN_OFFSET, \
|
||||
CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
|
||||
|
||||
extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
|
||||
extern struct liodn_id_table raide_liodn_tbl[];
|
||||
|
|
|
@ -861,15 +861,15 @@ struct ccsr_gpio {
|
|||
};
|
||||
};
|
||||
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
|
||||
#define CONFIG_SYS_MPC83xx_DMA_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
|
||||
#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
|
||||
#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
|
||||
#define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
|
||||
#define CFG_SYS_FSL_DDR_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000)
|
||||
#define CFG_SYS_MPC83xx_DMA_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_DMA_OFFSET)
|
||||
#define CFG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
|
||||
#define CFG_SYS_MPC83xx_ESDHC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
|
||||
|
||||
|
|
|
@ -963,7 +963,7 @@ struct rio_lp_serial {
|
|||
u32 prtoccsr; /* Port Response Time-out CCSR */
|
||||
u8 res1[20];
|
||||
u32 pgccsr; /* Port General CSR */
|
||||
struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
|
||||
struct rio_lp_serial_port port[CFG_SYS_FSL_SRIO_MAX_PORTS];
|
||||
};
|
||||
|
||||
/* Logical error reporting registers */
|
||||
|
@ -993,7 +993,7 @@ struct rio_phys_err_port {
|
|||
|
||||
/* Physical error reporting registers */
|
||||
struct rio_phys_err {
|
||||
struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
|
||||
struct rio_phys_err_port port[CFG_SYS_FSL_SRIO_MAX_PORTS];
|
||||
};
|
||||
|
||||
/* Implementation Space: General Port-Common */
|
||||
|
@ -1033,7 +1033,7 @@ struct rio_impl_port_spec {
|
|||
/* Implementation Space: register */
|
||||
struct rio_implement {
|
||||
struct rio_impl_common com;
|
||||
struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
|
||||
struct rio_impl_port_spec port[CFG_SYS_FSL_SRIO_MAX_PORTS];
|
||||
};
|
||||
|
||||
/* Revision Control Register */
|
||||
|
@ -1061,13 +1061,13 @@ struct rio_atmu_riw {
|
|||
|
||||
/* ATMU window registers */
|
||||
struct rio_atmu_win {
|
||||
struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
|
||||
struct rio_atmu_row outbw[CFG_SYS_FSL_SRIO_OB_WIN_NUM];
|
||||
u8 res0[64];
|
||||
struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
|
||||
struct rio_atmu_riw inbw[CFG_SYS_FSL_SRIO_IB_WIN_NUM];
|
||||
};
|
||||
|
||||
struct rio_atmu {
|
||||
struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
|
||||
struct rio_atmu_win port[CFG_SYS_FSL_SRIO_MAX_PORTS];
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_RMU
|
||||
|
@ -1154,7 +1154,7 @@ struct ccsr_rio {
|
|||
struct rio_atmu atmu;
|
||||
#ifdef CONFIG_SYS_FSL_RMU
|
||||
u8 res5[8192];
|
||||
struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
|
||||
struct rio_msg msg[CFG_SYS_FSL_SRIO_MSG_UNIT_NUM];
|
||||
u8 res6[512];
|
||||
struct rio_dbell dbell;
|
||||
u8 res7[100];
|
||||
|
@ -1162,7 +1162,7 @@ struct ccsr_rio {
|
|||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRIO_LIODN
|
||||
u8 res5[8192];
|
||||
struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
|
||||
struct rio_liodn liodn[CFG_SYS_FSL_SRIO_MAX_PORTS];
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
@ -2431,17 +2431,17 @@ struct ccsr_pman {
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_CORENET
|
||||
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
|
||||
#define CFG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
|
||||
#ifdef CONFIG_SYS_PMAN
|
||||
#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
|
||||
#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
|
||||
#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
|
||||
#define CFG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
|
||||
#define CFG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
|
||||
#define CFG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
|
||||
#endif
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
|
||||
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
|
||||
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
|
||||
#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x8000
|
||||
#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
|
||||
#define CFG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
|
||||
#define CFG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
|
||||
#define CFG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
|
||||
#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
/* In SFPv3, OSPR register is now at offset 0x200.
|
||||
* * So directly mapping sfp register map to this address */
|
||||
|
@ -2450,97 +2450,97 @@ struct ccsr_pman {
|
|||
#else
|
||||
#define CONFIG_SYS_SFP_OFFSET 0xE8000
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
|
||||
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
|
||||
#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
|
||||
#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
|
||||
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
|
||||
#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
|
||||
#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
|
||||
#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
|
||||
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
|
||||
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
|
||||
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
|
||||
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
|
||||
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
|
||||
#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
|
||||
#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
|
||||
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
|
||||
#define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
|
||||
#define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
|
||||
#define CFG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
|
||||
#define CFG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
|
||||
#define CFG_SYS_FSL_CPC_OFFSET 0x10000
|
||||
#define CFG_SYS_FSL_SCFG_OFFSET 0xFC000
|
||||
#define CFG_SYS_FSL_PAMU_OFFSET 0x20000
|
||||
#define CFG_SYS_MPC85xx_DMA1_OFFSET 0x100000
|
||||
#define CFG_SYS_MPC85xx_DMA2_OFFSET 0x101000
|
||||
#define CFG_SYS_MPC85xx_DMA3_OFFSET 0x102000
|
||||
#define CFG_SYS_MPC85xx_DMA_OFFSET CFG_SYS_MPC85xx_DMA1_OFFSET
|
||||
#define CFG_SYS_MPC85xx_ESPI_OFFSET 0x110000
|
||||
#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
|
||||
#define CFG_SYS_MPC85xx_LBC_OFFSET 0x124000
|
||||
#define CFG_SYS_MPC85xx_IFC_OFFSET 0x124000
|
||||
#define CFG_SYS_MPC85xx_GPIO_OFFSET 0x130000
|
||||
#define CFG_SYS_MPC85xx_TDM_OFFSET 0x185000
|
||||
#define CFG_SYS_MPC85xx_QE_OFFSET 0x140000
|
||||
#define CFG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
|
||||
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
|
||||
!defined(CONFIG_ARCH_B4420)
|
||||
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
|
||||
#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
|
||||
#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
|
||||
#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
|
||||
#define CFG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
|
||||
#else
|
||||
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
|
||||
#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
|
||||
#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
|
||||
#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
|
||||
#define CFG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
|
||||
#endif
|
||||
#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
|
||||
#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
|
||||
#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
|
||||
#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
|
||||
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
|
||||
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
|
||||
#define CFG_SYS_MPC85xx_USB1_OFFSET 0x210000
|
||||
#define CFG_SYS_MPC85xx_USB2_OFFSET 0x211000
|
||||
#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
|
||||
#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
|
||||
#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x220000
|
||||
#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000
|
||||
#define CFG_SYS_FSL_SEC_OFFSET 0x300000
|
||||
#define CFG_SYS_FSL_JR0_OFFSET 0x301000
|
||||
#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
|
||||
#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
|
||||
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
|
||||
#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
|
||||
#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
|
||||
#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
|
||||
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
|
||||
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
|
||||
#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
|
||||
#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
|
||||
#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
|
||||
#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
|
||||
#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
|
||||
#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
|
||||
#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
|
||||
#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
|
||||
#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
|
||||
#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
|
||||
#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
|
||||
#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
|
||||
#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
|
||||
#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
|
||||
#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
|
||||
#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
|
||||
#define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000
|
||||
#define CFG_SYS_FSL_QMAN_OFFSET 0x318000
|
||||
#define CFG_SYS_FSL_BMAN_OFFSET 0x31a000
|
||||
#define CFG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
|
||||
#define CFG_SYS_FSL_FM1_OFFSET 0x400000
|
||||
#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
|
||||
#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
|
||||
#define CFG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
|
||||
#define CFG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
|
||||
#define CFG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
|
||||
#define CFG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
|
||||
#define CFG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
|
||||
#define CFG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
|
||||
#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
|
||||
#define CFG_SYS_FSL_FM2_OFFSET 0x500000
|
||||
#define CFG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
|
||||
#define CFG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
|
||||
#define CFG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
|
||||
#define CFG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
|
||||
#define CFG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
|
||||
#define CFG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
|
||||
#define CFG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
|
||||
#define CFG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
|
||||
#define CFG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
|
||||
#else
|
||||
#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
|
||||
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
|
||||
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
|
||||
#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
|
||||
#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
|
||||
#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
|
||||
#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
|
||||
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
|
||||
#define CFG_SYS_MPC85xx_ECM_OFFSET 0x0000
|
||||
#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x2000
|
||||
#define CFG_SYS_MPC85xx_LBC_OFFSET 0x5000
|
||||
#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
|
||||
#define CFG_SYS_MPC85xx_ESPI_OFFSET 0x7000
|
||||
#define CFG_SYS_MPC85xx_PCI1_OFFSET 0x8000
|
||||
#define CFG_SYS_MPC85xx_PCIX_OFFSET 0x8000
|
||||
#define CFG_SYS_MPC85xx_PCI2_OFFSET 0x9000
|
||||
#define CFG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
|
||||
#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
|
||||
#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
|
||||
#if defined(CONFIG_ARCH_P2020)
|
||||
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
|
||||
#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
|
||||
#else
|
||||
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
|
||||
#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
|
||||
#endif
|
||||
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
|
||||
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
|
||||
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
|
||||
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
|
||||
#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
|
||||
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
|
||||
#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
|
||||
#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
|
||||
#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
|
||||
#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
|
||||
#define CFG_SYS_MPC85xx_GPIO_OFFSET 0xF000
|
||||
#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x18000
|
||||
#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x19000
|
||||
#define CFG_SYS_MPC85xx_IFC_OFFSET 0x1e000
|
||||
#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000
|
||||
#define CFG_SYS_MPC85xx_DMA_OFFSET 0x21000
|
||||
#define CFG_SYS_MPC85xx_USB1_OFFSET 0x22000
|
||||
#define CFG_SYS_MPC85xx_USB2_OFFSET 0x23000
|
||||
#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
|
||||
#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
|
||||
#ifdef CONFIG_TSECV2
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
|
||||
#elif defined(CONFIG_TSECV2_1)
|
||||
|
@ -2549,131 +2549,131 @@ struct ccsr_pman {
|
|||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
||||
#endif
|
||||
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
|
||||
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
|
||||
#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
|
||||
#if defined(CONFIG_ARCH_C29X)
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
|
||||
#define CFG_SYS_FSL_SEC_OFFSET 0x80000
|
||||
#define CFG_SYS_FSL_JR0_OFFSET 0x81000
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
|
||||
#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
|
||||
#define CFG_SYS_FSL_SEC_OFFSET 0x30000
|
||||
#define CFG_SYS_FSL_JR0_OFFSET 0x31000
|
||||
#endif
|
||||
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
|
||||
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
|
||||
#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
|
||||
#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
|
||||
#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
|
||||
#define CONFIG_SYS_SFP_OFFSET 0xE7000
|
||||
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
|
||||
#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
|
||||
#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
|
||||
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
|
||||
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
|
||||
#define CFG_SYS_FSL_QMAN_OFFSET 0x88000
|
||||
#define CFG_SYS_FSL_BMAN_OFFSET 0x8a000
|
||||
#define CFG_SYS_FSL_FM1_OFFSET 0x100000
|
||||
#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
|
||||
#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
|
||||
#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
|
||||
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
|
||||
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
|
||||
#define CFG_SYS_MPC85xx_PIC_OFFSET 0x40000
|
||||
#define CFG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
|
||||
#define CFG_SYS_FSL_SRIO_OFFSET 0xC0000
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC_ADDR \
|
||||
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR \
|
||||
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
|
||||
#define CONFIG_SYS_FSL_QMAN_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
|
||||
#define CONFIG_SYS_FSL_BMAN_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
|
||||
#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
|
||||
#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
|
||||
#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
|
||||
#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
|
||||
#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
|
||||
#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_ECM_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_FSL_DDR2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
|
||||
#define CONFIG_SYS_FSL_DDR3_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
|
||||
#define CFG_SYS_FSL_CPC_ADDR \
|
||||
(CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
|
||||
#define CFG_SYS_FSL_SCFG_ADDR \
|
||||
(CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
|
||||
#define CFG_SYS_FSL_QMAN_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET)
|
||||
#define CFG_SYS_FSL_BMAN_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_BMAN_OFFSET)
|
||||
#define CFG_SYS_FSL_CORENET_PME_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_PME_OFFSET)
|
||||
#define CFG_SYS_FSL_RAID_ENGINE_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_RAID_ENGINE_OFFSET)
|
||||
#define CFG_SYS_FSL_CORENET_RMAN_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RMAN_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_GUTS_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
|
||||
#define CFG_SYS_FSL_CORENET_CCM_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CCM_OFFSET)
|
||||
#define CFG_SYS_FSL_CORENET_CLK_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CLK_OFFSET)
|
||||
#define CFG_SYS_FSL_CORENET_RCPM_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RCPM_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_ECM_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
|
||||
#define CFG_SYS_FSL_DDR_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CFG_SYS_FSL_DDR2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
|
||||
#define CFG_SYS_FSL_DDR3_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
|
||||
#define CONFIG_SYS_LBC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
|
||||
#define CONFIG_SYS_IFC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_L2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_DMA_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
|
||||
#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_USB1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_USB2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
|
||||
#define CONFIG_SYS_FSL_SEC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
|
||||
#define CONFIG_SYS_FSL_JR0_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
|
||||
#define CONFIG_SYS_FSL_FM1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
|
||||
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
|
||||
#define CONFIG_SYS_FSL_FM2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
|
||||
#define CONFIG_SYS_FSL_SRIO_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_ESPI_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_PCIX_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_PCIX2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX2_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_GPIO_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GPIO_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_SATA1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA1_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_SATA2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA2_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_L2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_L2_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_DMA_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_DMA_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_ESDHC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESDHC_OFFSET)
|
||||
#define CFG_SYS_MPC8xxx_PIC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_SERDES1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_SERDES2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
|
||||
#define CFG_SYS_FSL_CORENET_SERDES_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET)
|
||||
#define CFG_SYS_FSL_CORENET_SERDES2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES2_OFFSET)
|
||||
#define CFG_SYS_FSL_CORENET_SERDES3_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET)
|
||||
#define CFG_SYS_FSL_CORENET_SERDES4_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES4_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_USB1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_USB2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_USB1_PHY_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
|
||||
#define CFG_SYS_FSL_SEC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
|
||||
#define CFG_SYS_FSL_JR0_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
|
||||
#define CFG_SYS_FSL_FM1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
|
||||
#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
|
||||
#define CFG_SYS_FSL_FM2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET)
|
||||
#define CFG_SYS_FSL_SRIO_ADDR \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET)
|
||||
#define CONFIG_SYS_PAMU_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_PCI1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
|
||||
#define CONFIG_SYS_PCI2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET)
|
||||
#define CONFIG_SYS_PCIE1_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET)
|
||||
#define CONFIG_SYS_PCIE2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
|
||||
#define CONFIG_SYS_PCIE3_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET)
|
||||
#define CONFIG_SYS_PCIE4_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_SFP_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
|
||||
|
@ -2739,8 +2739,8 @@ struct ccsr_cluster_l2 {
|
|||
u32 l2erraddr; /* 0xe54 L2 cache error address */
|
||||
u32 l2errctl; /* 0xe58 L2 cache error control */
|
||||
};
|
||||
#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
|
||||
#define CFG_SYS_FSL_CLUSTER_1_L2 \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET)
|
||||
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
|
||||
|
||||
#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
|
||||
|
@ -2752,9 +2752,9 @@ struct dcsr_dcfg_regs {
|
|||
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
|
||||
};
|
||||
|
||||
#define CONFIG_SYS_MPC85xx_SCFG \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
|
||||
#define CFG_SYS_MPC85xx_SCFG \
|
||||
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SCFG_OFFSET)
|
||||
#define CFG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
|
||||
/* The supplement configuration unit register */
|
||||
struct ccsr_scfg {
|
||||
u32 dpslpcr; /* 0x000 Deep Sleep Control register */
|
||||
|
|
|
@ -20,7 +20,7 @@
|
|||
static inline void mpc85xx_gpio_set(unsigned int mask,
|
||||
unsigned int dir, unsigned int val)
|
||||
{
|
||||
ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
|
||||
ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
|
||||
|
||||
/* First mask off the unwanted parts of "dir" and "val" */
|
||||
dir &= mask;
|
||||
|
@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)
|
|||
|
||||
static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
|
||||
{
|
||||
ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
|
||||
ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
|
||||
|
||||
/* Read the requested values */
|
||||
return in_be32(&gpio->gpdat) & mask;
|
||||
|
|
|
@ -129,7 +129,7 @@ int board_mmc_init(struct bd_info *bis)
|
|||
* mmc0 USDHC1
|
||||
* mmc1 USDHC2
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
init_clk_usdhc(1);
|
||||
|
|
|
@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
|
||||
{USDHC1_BASE_ADDR, 0, 8},
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
{USDHC3_BASE_ADDR, 0, 4},
|
||||
|
@ -108,7 +108,7 @@ int board_mmc_init(struct bd_info *bis)
|
|||
* mmc1 USDHC2
|
||||
* mmc2 USDHC3
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
|
||||
|
|
|
@ -6,10 +6,10 @@
|
|||
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
|
||||
#define __SOCFPGA_IOCSR_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[] = {
|
||||
0x00000000,
|
||||
|
|
|
@ -6,79 +6,79 @@
|
|||
#ifndef __SOCFPGA_PLL_CONFIG_H__
|
||||
#define __SOCFPGA_PLL_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||
#define CFG_HPS_DBCTRL_STAYOSC1 1
|
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CFG_HPS_MAINPLLGRP_VCO_NUMER 41
|
||||
#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
|
||||
#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
#define CFG_HPS_PERPLLGRP_VCO_DENOM 1
|
||||
#define CFG_HPS_PERPLLGRP_VCO_NUMER 79
|
||||
#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
|
||||
#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||
#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
|
||||
#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
|
||||
#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4
|
||||
#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
|
||||
#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1
|
||||
#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CFG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_NUMER 127
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ 350000000
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||
#define CFG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CFG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CFG_HPS_CLK_MAINVCO_HZ 1050000000
|
||||
#define CFG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CFG_HPS_CLK_SDRVCO_HZ 1066000000
|
||||
#define CFG_HPS_CLK_EMAC0_HZ 250000000
|
||||
#define CFG_HPS_CLK_EMAC1_HZ 250000000
|
||||
#define CFG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CFG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CFG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CFG_HPS_CLK_QSPI_HZ 350000000
|
||||
#define CFG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CFG_HPS_CLK_CAN0_HZ 100000000
|
||||
#define CFG_HPS_CLK_CAN1_HZ 100000000
|
||||
#define CFG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CFG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CFG_HPS_CLK_L4_SP_HZ 100000000
|
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 0
|
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 2
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
|
||||
#define CFG_HPS_ALTERAGRP_MPUCLK 0
|
||||
#define CFG_HPS_ALTERAGRP_MAINCLK 2
|
||||
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
||||
|
|
|
@ -7,76 +7,76 @@
|
|||
#define __SOCFPGA_SDRAM_CONFIG_H__
|
||||
|
||||
/* SDRAM configuration */
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
|
||||
/* Sequencer auto configuration */
|
||||
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
|
||||
|
|
|
@ -6,10 +6,10 @@
|
|||
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
|
||||
#define __SOCFPGA_IOCSR_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[] = {
|
||||
0x00000000,
|
||||
|
|
|
@ -6,79 +6,79 @@
|
|||
#ifndef __SOCFPGA_PLL_CONFIG_H__
|
||||
#define __SOCFPGA_PLL_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||
#define CFG_HPS_DBCTRL_STAYOSC1 1
|
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73
|
||||
#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
|
||||
#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
|
||||
#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||
#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
|
||||
#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
|
||||
#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CFG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ 370000000
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||
#define CFG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CFG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CFG_HPS_CLK_MAINVCO_HZ 1850000000
|
||||
#define CFG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CFG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CFG_HPS_CLK_EMAC0_HZ 1953125
|
||||
#define CFG_HPS_CLK_EMAC1_HZ 250000000
|
||||
#define CFG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CFG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CFG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CFG_HPS_CLK_QSPI_HZ 370000000
|
||||
#define CFG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CFG_HPS_CLK_CAN0_HZ 100000000
|
||||
#define CFG_HPS_CLK_CAN1_HZ 12500000
|
||||
#define CFG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CFG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CFG_HPS_CLK_L4_SP_HZ 100000000
|
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
|
||||
#define CFG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CFG_HPS_ALTERAGRP_MAINCLK 4
|
||||
#define CFG_HPS_ALTERAGRP_DBGATCLK 4
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
||||
|
|
|
@ -7,76 +7,76 @@
|
|||
#define __SOCFPGA_SDRAM_CONFIG_H__
|
||||
|
||||
/* SDRAM configuration */
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
|
||||
/* Sequencer auto configuration */
|
||||
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
|
||||
|
|
|
@ -6,10 +6,10 @@
|
|||
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
|
||||
#define __SOCFPGA_IOCSR_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[] = {
|
||||
0x00000000,
|
||||
|
|
|
@ -6,79 +6,79 @@
|
|||
#ifndef __SOCFPGA_PLL_CONFIG_H__
|
||||
#define __SOCFPGA_PLL_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||
#define CFG_HPS_DBCTRL_STAYOSC1 1
|
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
|
||||
#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
|
||||
#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
|
||||
#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
|
||||
#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
|
||||
#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1
|
||||
#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CFG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ 3125000
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||
#define CFG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CFG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
|
||||
#define CFG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CFG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CFG_HPS_CLK_EMAC0_HZ 250000000
|
||||
#define CFG_HPS_CLK_EMAC1_HZ 1953125
|
||||
#define CFG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CFG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CFG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CFG_HPS_CLK_QSPI_HZ 3125000
|
||||
#define CFG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CFG_HPS_CLK_CAN0_HZ 100000000
|
||||
#define CFG_HPS_CLK_CAN1_HZ 100000000
|
||||
#define CFG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CFG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CFG_HPS_CLK_L4_SP_HZ 100000000
|
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
|
||||
#define CFG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CFG_HPS_ALTERAGRP_MAINCLK 3
|
||||
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
||||
|
|
|
@ -7,76 +7,76 @@
|
|||
#define __SOCFPGA_SDRAM_CONFIG_H__
|
||||
|
||||
/* SDRAM configuration */
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
|
||||
#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
|
||||
#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
|
||||
#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
|
||||
#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
|
||||
#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
|
||||
#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
|
||||
#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
|
||||
#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
|
||||
#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
|
||||
#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
|
||||
#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
|
||||
|
||||
/* Sequencer auto configuration */
|
||||
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
|
||||
|
|
|
@ -562,7 +562,7 @@ int board_mmc_init(struct bd_info *bis)
|
|||
* mmc0 USDHC2
|
||||
* mmc1 USDHC4
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
SETUP_IOMUX_PADS(usdhc2_pads);
|
||||
|
|
|
@ -90,7 +90,7 @@ int board_mmc_init(struct bd_info *bis)
|
|||
* mmc0 USDHC1
|
||||
* mmc2 USDHC3 (eMMC)
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
cl_som_imx7_usdhc1_pads_set();
|
||||
|
|
|
@ -622,7 +622,7 @@ int board_init(void)
|
|||
int i;
|
||||
|
||||
cm_fx6_set_usdhc_iomux();
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
|
||||
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++)
|
||||
enable_usdhc_clk(1, i);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -114,7 +114,7 @@ int board_early_init_f(void)
|
|||
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
|
||||
{USDHC1_BASE_ADDR, 0, 8},
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
{USDHC3_BASE_ADDR, 0, 4},
|
||||
|
@ -173,7 +173,7 @@ int board_mmc_init(struct bd_info *bis)
|
|||
* mmc1 (external SD card) USDHC2
|
||||
* mmc2 (onboard µSD) USDHC3
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
/* onboard eMMC */
|
||||
|
|
|
@ -6,10 +6,10 @@
|
|||
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
|
||||
#define __SOCFPGA_IOCSR_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
|
||||
#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[] = {
|
||||
0x00000000,
|
||||
|
|
|
@ -6,79 +6,79 @@
|
|||
#ifndef __SOCFPGA_PLL_CONFIG_H__
|
||||
#define __SOCFPGA_PLL_CONFIG_H__
|
||||
|
||||
#define CONFIG_HPS_DBCTRL_STAYOSC1 1
|
||||
#define CFG_HPS_DBCTRL_STAYOSC1 1
|
||||
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
|
||||
#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
|
||||
#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
|
||||
#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
|
||||
#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
|
||||
#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
|
||||
#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
|
||||
#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
|
||||
#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
|
||||
#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
|
||||
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
|
||||
#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
|
||||
#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
|
||||
#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
|
||||
#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
|
||||
#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
|
||||
#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
|
||||
#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
|
||||
#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
|
||||
#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
|
||||
#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
|
||||
#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
|
||||
#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
|
||||
#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
|
||||
#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
|
||||
#define CFG_HPS_PERPLLGRP_SRC_NAND 2
|
||||
#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
|
||||
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
|
||||
#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
|
||||
#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
|
||||
#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
|
||||
#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
|
||||
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ 400000000
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ 12500000
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
|
||||
#define CFG_HPS_CLK_OSC1_HZ 25000000
|
||||
#define CFG_HPS_CLK_OSC2_HZ 25000000
|
||||
#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
|
||||
#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
|
||||
#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
|
||||
#define CFG_HPS_CLK_PERVCO_HZ 1000000000
|
||||
#define CFG_HPS_CLK_SDRVCO_HZ 800000000
|
||||
#define CFG_HPS_CLK_EMAC0_HZ 1953125
|
||||
#define CFG_HPS_CLK_EMAC1_HZ 250000000
|
||||
#define CFG_HPS_CLK_USBCLK_HZ 200000000
|
||||
#define CFG_HPS_CLK_NAND_HZ 50000000
|
||||
#define CFG_HPS_CLK_SDMMC_HZ 200000000
|
||||
#define CFG_HPS_CLK_QSPI_HZ 400000000
|
||||
#define CFG_HPS_CLK_SPIM_HZ 200000000
|
||||
#define CFG_HPS_CLK_CAN0_HZ 12500000
|
||||
#define CFG_HPS_CLK_CAN1_HZ 12500000
|
||||
#define CFG_HPS_CLK_GPIODB_HZ 32000
|
||||
#define CFG_HPS_CLK_L4_MP_HZ 100000000
|
||||
#define CFG_HPS_CLK_L4_SP_HZ 100000000
|
||||
|
||||
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
|
||||
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
|
||||
#define CFG_HPS_ALTERAGRP_MPUCLK 1
|
||||
#define CFG_HPS_ALTERAGRP_MAINCLK 3
|
||||
#define CFG_HPS_ALTERAGRP_DBGATCLK 3
|
||||
|
||||
|
||||
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
|
||||
|
|
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Reference in a new issue