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dts: qcs404-evb: Add USB controller and PHY nodes

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QCS404 SoC provides support for two USB controllers: one USB3 and the
other one being USB2. The USB3 controller supports further 2 PHY: one high
speed PHY and the other super speed PHY. The USB2 controller supports a
single high speed PHY. So add corresponding DT nodes.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Sumit Garg 2022-08-04 19:57:16 +05:30 committed by Tom Rini
parent 968597b85c
commit 0c1eab6f75
1 changed files with 87 additions and 0 deletions
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87
arch/arm/dts/qcs404-evb.dts
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@ -52,6 +52,7 @@
reg = <0x1800000 0x80000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <1>;
};
reset: gcc-reset@1800000 {
@ -81,6 +82,92 @@
mmc-ddr-1_8v;
mmc-hs400-1_8v;
};
usb3_phy: phy@78000 {
compatible = "qcom,usb-ss-28nm-phy";
#phy-cells = <0>;
reg = <0x78000 0x400>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "ahb", "pipe";
resets = <&reset GCC_USB3_PHY_BCR>,
<&reset GCC_USB3PHY_PHY_BCR>;
reset-names = "com", "phy";
};
usb2_phy_prim: phy@7a000 {
compatible = "qcom,usb-hs-28nm-femtophy";
#phy-cells = <0>;
reg = <0x7a000 0x200>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ahb", "sleep";
resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>,
<&reset GCC_USB2A_PHY_BCR>;
reset-names = "phy", "por";
};
usb2_phy_sec: phy@7c000 {
compatible = "qcom,usb-hs-28nm-femtophy";
#phy-cells = <0>;
reg = <0x7c000 0x200>;
clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ahb", "sleep";
resets = <&reset GCC_QUSB2_PHY_BCR>,
<&reset GCC_USB2_HS_PHY_ONLY_BCR>;
reset-names = "phy", "por";
};
usb3: usb@7678800 {
compatible = "qcom,dwc3";
reg = <0x7678800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
clock-names = "core", "iface", "sleep", "mock_utmi";
dwc3@7580000 {
compatible = "snps,dwc3";
reg = <0x7580000 0xcd00>;
phys = <&usb2_phy_prim>, <&usb3_phy>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
};
usb2: usb@79b8800 {
compatible = "qcom,dwc3";
reg = <0x79b8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
<&gcc GCC_PCNOC_USB2_CLK>,
<&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>;
clock-names = "core", "iface", "sleep", "mock_utmi";
dwc3@78c0000 {
compatible = "snps,dwc3";
reg = <0x78c0000 0xcc00>;
phys = <&usb2_phy_sec>;
phy-names = "usb2-phy";
dr_mode = "peripheral";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
maximum-speed = "high-speed";
};
};
};
};