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Merge branch 'master' of git://git.denx.de/u-boot-arm

Browse source 
Conflicts:

	board/eukrea/cpu9260/cpu9260.c
	drivers/serial/serial_s5pc1xx.c
	include/asm-arm/arch-s5pc1xx/clock.h
	include/asm-arm/arch-s5pc1xx/gpio.h
	include/asm-arm/arch-s5pc1xx/pwm.h
	include/asm-arm/arch-s5pc1xx/uart.h
	include/configs/cpu9260.h
	include/configs/cpuat91.h
	include/configs/davinci_dm355evm.h
	include/linux/mtd/samsung_onenand.h
This commit is contained in:
Minkyu Kang 2009-10-30 12:14:40 +09:00
commit 0bf7de8380
514 changed files with 6011 additions and 4402 deletions
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8
MAINTAINERS
View file

@ -612,6 +612,13 @@ Sergey Kubushyn <ksi@koi8.net>
SONATA ARM926EJS
SCHMOOGIE ARM926EJS
Sandeep Paulraj <s-paulraj@ti.com>
davinci_dm355evm ARM926EJS
davinci_dm355leopard ARM926EJS
davinci_dm365evm ARM926EJS
davinci_dm6467evm ARM926EJS
Prakash Kumar <prakash@embedx.com>
cerf250 xscale
@ -628,6 +635,7 @@ Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Nishanth Menon <nm@ti.com>
omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC)
omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
David Müller <d.mueller@elsoft.ch>

3
MAKEALL
View file

@ -567,6 +567,8 @@ LIST_ARM9=" \
davinci_sffsdr \
davinci_sonata \
davinci_dm355evm \
davinci_dm355leopard \
davinci_dm6467evm \
"
#########################################################################
@ -603,6 +605,7 @@ LIST_ARM_CORTEX_A8=" \
omap3_overo \
omap3_evm \
omap3_pandora \
omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
smdkc100 \

9
Makefile
View file

@ -2927,9 +2927,15 @@ davinci_sonata_config : unconfig
davinci_dm355evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm355evm davinci davinci
davinci_dm355leopard_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm355leopard davinci davinci
davinci_dm365evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm365evm davinci davinci
davinci_dm6467evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci
imx27lite_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
@ -3138,6 +3144,9 @@ omap3_evm_config : unconfig
omap3_pandora_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora NULL omap3
omap3_sdp3430_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3
omap3_zoom1_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 logicpd omap3

1
board/LEOX/elpt860/u-boot.lds
View file

@ -80,7 +80,6 @@ SECTIONS
common/env_embedded.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/LEOX/elpt860/u-boot.lds.debug
View file

@ -73,7 +73,6 @@ SECTIONS
common/env_embedded.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/MAI/AmigaOneG3SE/u-boot.lds
View file

@ -65,7 +65,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/Marvell/db64360/u-boot.lds
View file

@ -63,7 +63,6 @@ SECTIONS
/* common/env_embedded.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/Marvell/db64460/u-boot.lds
View file

@ -63,7 +63,6 @@ SECTIONS
/* common/env_embedded.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/RPXClassic/u-boot.lds
View file

@ -67,7 +67,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/RPXClassic/u-boot.lds.debug
View file

@ -64,7 +64,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/RPXlite/u-boot.lds
View file

@ -67,7 +67,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/RPXlite/u-boot.lds.debug
View file

@ -64,7 +64,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/RPXlite_dw/u-boot.lds
View file

@ -67,7 +67,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/RPXlite_dw/u-boot.lds.debug
View file

@ -64,7 +64,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/RRvision/u-boot.lds
View file

@ -69,7 +69,6 @@ SECTIONS
common/env_embedded.o (.ppcenv)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/adder/u-boot.lds
View file

@ -54,7 +54,6 @@ SECTIONS
{
cpu/mpc8xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.eh_frame)

12
board/altera/ep1c20/ep1c20.c
View file

@ -22,6 +22,7 @@
*/
#include <common.h>
#include <netdev.h>
int board_early_init_f (void)
{
@ -38,3 +39,14 @@ phys_size_t initdram (int board_type)
{
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

12
board/altera/ep1s10/ep1s10.c
View file

@ -22,6 +22,7 @@
*/
#include <common.h>
#include <netdev.h>
int board_early_init_f (void)
{
@ -38,3 +39,14 @@ phys_size_t initdram (int board_type)
{
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

12
board/altera/ep1s40/ep1s40.c
View file

@ -22,6 +22,7 @@
*/
#include <common.h>
#include <netdev.h>
int checkboard (void)
{
@ -33,3 +34,14 @@ phys_size_t initdram (int board_type)
{
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

1
board/amcc/acadia/u-boot-nand.lds
View file

@ -62,7 +62,6 @@ SECTIONS
. = ALIGN(0x10000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/acadia/u-boot.lds
View file

@ -63,7 +63,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

28
board/amcc/bamboo/bamboo.c
View file

@ -542,22 +542,22 @@ void pci_target_init(struct pci_controller *hose)
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers

1
board/amcc/bamboo/u-boot-nand.lds
View file

@ -62,7 +62,6 @@ SECTIONS
. = ALIGN(0x10000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/bamboo/u-boot.lds
View file

@ -70,7 +70,6 @@ SECTIONS
board/amcc/bamboo/bamboo.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/bubinga/u-boot.lds
View file

@ -63,7 +63,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

25
board/amcc/canyonlands/canyonlands.c
View file

@ -28,6 +28,7 @@
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>
#include <asm/gpio.h>
#include <asm/errno.h>
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
@ -338,27 +339,27 @@ void pci_target_init(struct pci_controller * hose )
/*
* Disable everything
*/
out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
/*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*/
out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
out_le32((void *)PCIX0_PIM0LAH, 0);
out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
out_le32((void *)PCIX0_BAR0, 0);
out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
out_le32((void *)PCIL0_PIM0LAH, 0);
out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
out_le32((void *)PCIL0_BAR0, 0);
/*
* Program the board's subsystem id/vendor id
*/
out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
@ -414,6 +415,8 @@ void pcie_setup_hoses(int busno)
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
if (ret == -ENODEV)
continue;
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");

1
board/amcc/canyonlands/u-boot-nand.lds
View file

@ -62,7 +62,6 @@ SECTIONS
. = ALIGN(0x80000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/canyonlands/u-boot.lds
View file

@ -69,7 +69,6 @@ SECTIONS
board/amcc/canyonlands/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

22
board/amcc/ebony/ebony.c
View file

@ -210,28 +210,28 @@ void pci_target_init(struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r(PCIX0_PIM0SA, 0); /* disable */
out32r(PCIX0_PIM1SA, 0); /* disable */
out32r(PCIX0_PIM2SA, 0); /* disable */
out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
out32r(PCIL0_PIM0SA, 0); /* disable */
out32r(PCIL0_PIM1SA, 0); /* disable */
out32r(PCIL0_PIM2SA, 0); /* disable */
out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
out32r(PCIX0_PIM0LAH, 0);
out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
out32r(PCIL0_PIM0LAH, 0);
out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
out32r(PCIX0_BAR0, 0);
out32r(PCIL0_BAR0, 0);
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */

1
board/amcc/ebony/u-boot.lds
View file

@ -69,7 +69,6 @@ SECTIONS
board/amcc/ebony/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

25
board/amcc/katmai/katmai.c
View file

@ -32,6 +32,7 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/4xx_pcie.h>
#include <asm/errno.h>
DECLARE_GLOBAL_DATA_PTR;
@ -304,27 +305,27 @@ void pci_target_init(struct pci_controller * hose )
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
out32r( PCIL0_PIM0SA, 0 ); /* disable */
out32r( PCIL0_PIM1SA, 0 ); /* disable */
out32r( PCIL0_PIM2SA, 0 ); /* disable */
out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*-------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIL0_PIM0LAH, 0 );
out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIL0_BAR0, 0 );
/*-------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
@ -391,6 +392,8 @@ void pcie_setup_hoses(int busno)
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
if (ret == -ENODEV)
continue;
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");

1
board/amcc/katmai/u-boot.lds
View file

@ -66,7 +66,6 @@ SECTIONS
board/amcc/katmai/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

3
board/amcc/kilauea/kilauea.c
View file

@ -28,6 +28,7 @@
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/errno.h>
#if defined(CONFIG_PCI)
#include <pci.h>
@ -317,6 +318,8 @@ void pcie_setup_hoses(int busno)
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
if (ret == -ENODEV)
continue;
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");

1
board/amcc/kilauea/u-boot-nand.lds
View file

@ -62,7 +62,6 @@ SECTIONS
. = ALIGN(0x10000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/kilauea/u-boot.lds
View file

@ -64,7 +64,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

22
board/amcc/luan/epld.h
View file

@ -8,8 +8,8 @@
#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */
#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */
#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */
#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */
#define EPLD1_PCIL0_CNTL1 0x40 /* S*0 of 9531 */
#define EPLD1_PCIL0_CNTL2 0x20 /* S*1 of 9531 */
#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */
#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */
#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */
@ -29,25 +29,25 @@
#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */
#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */
#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */
#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */
#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */
#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */
#define EPLD4_PCIL0_VTH1 0x80 /* PCI-X 0 VTH1 status */
#define EPLD4_PCIL0_VTH2 0x40 /* PCI-X 0 VTH2 status */
#define EPLD4_PCIL0_VTH3 0x20 /* PCI-X 0 VTH3 status */
#define EPLD4_PCIL0_VTH4 0x10 /* PCI-X 0 VTH4 status */
#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */
#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */
#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */
#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */
#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
#define EPLD5_PCIL0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
#define EPLD5_PCIL0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
#define EPLD5_PCIL0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
#define EPLD5_PCIL0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */
#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */
#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */
#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */
#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_PCIL0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */
#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */
#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */

22
board/amcc/luan/luan.c
View file

@ -173,28 +173,28 @@ void pci_target_init(struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
out32r( PCIL0_PIM0SA, 0 ); /* disable */
out32r( PCIL0_PIM1SA, 0 ); /* disable */
out32r( PCIL0_PIM2SA, 0 ); /* disable */
out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIL0_PIM0LAH, 0 );
out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
out32r( PCIL0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */

1
board/amcc/luan/u-boot.lds
View file

@ -69,7 +69,6 @@ SECTIONS
board/amcc/luan/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

3
board/amcc/makalu/makalu.c
View file

@ -29,6 +29,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <asm/errno.h>
#if defined(CONFIG_PCI)
#include <pci.h>
@ -273,6 +274,8 @@ void pcie_setup_hoses(int busno)
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
if (ret == -ENODEV)
continue;
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");

1
board/amcc/makalu/u-boot.lds
View file

@ -64,7 +64,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

22
board/amcc/ocotea/ocotea.c
View file

@ -321,28 +321,28 @@ void pci_target_init(struct pci_controller * hose )
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
out32r( PCIL0_PIM0SA, 0 ); /* disable */
out32r( PCIL0_PIM1SA, 0 ); /* disable */
out32r( PCIL0_PIM2SA, 0 ); /* disable */
out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIL0_PIM0LAH, 0 );
out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
out32r( PCIL0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */

1
board/amcc/ocotea/u-boot.lds
View file

@ -69,7 +69,6 @@ SECTIONS
board/amcc/ocotea/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/redwood/u-boot.lds
View file

@ -73,7 +73,6 @@ SECTIONS
/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

28
board/amcc/sequoia/sequoia.c
View file

@ -428,26 +428,26 @@ void pci_target_init(struct pci_controller *hose)
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*
* Set up Configuration registers

1
board/amcc/sequoia/u-boot-nand.lds
View file

@ -62,7 +62,6 @@ SECTIONS
. = ALIGN(0x10000);
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/sequoia/u-boot-ram.lds
View file

@ -53,7 +53,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/sequoia/u-boot.lds
View file

@ -68,7 +68,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/taihu/u-boot.lds
View file

@ -63,7 +63,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

100
board/amcc/taishan/showinfo.c
View file

@ -39,13 +39,13 @@ void show_reset_reg(void)
mfcpr(CPR0_PLLD,reg);
printf("cpr_plld = %#010lx\n",reg);
mfcpr(CPR0_PRIMAD,reg);
mfcpr(CPR0_PRIMAD0,reg);
printf("cpr_primad = %#010lx\n",reg);
mfcpr(CPR0_PRIMBD,reg);
mfcpr(CPR0_PRIMBD0,reg);
printf("cpr_primbd = %#010lx\n",reg);
mfcpr(CPR0_OPBD,reg);
mfcpr(CPR0_OPBD0,reg);
printf("cpr_opbd = %#010lx\n",reg);
mfcpr(CPR0_PERD,reg);
@ -106,59 +106,59 @@ void show_xbridge_info(void)
printf("SDR0_XPLLD = %#010lx\n", reg);
printf("PCI-X Bridge Configure registers\n");
printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));
printf("PCIX0_DEVID = %#06x\n", in16r(PCIX0_DEVID));
printf("PCIX0_CMD = %#06x\n", in16r(PCIX0_CMD));
printf("PCIX0_STATUS = %#06x\n", in16r(PCIX0_STATUS));
printf("PCIX0_REVID = %#04x\n", in8(PCIX0_REVID));
printf("PCIX0_CACHELS = %#04x\n", in8(PCIX0_CACHELS));
printf("PCIX0_LATTIM = %#04x\n", in8(PCIX0_LATTIM));
printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE));
printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST));
printf("PCIL0_VENDID = %#06x\n", in16r(PCIL0_VENDID));
printf("PCIL0_DEVID = %#06x\n", in16r(PCIL0_DEVID));
printf("PCIL0_CMD = %#06x\n", in16r(PCIL0_CMD));
printf("PCIL0_STATUS = %#06x\n", in16r(PCIL0_STATUS));
printf("PCIL0_REVID = %#04x\n", in8(PCIL0_REVID));
printf("PCIL0_CACHELS = %#04x\n", in8(PCIL0_CACHELS));
printf("PCIL0_LATTIM = %#04x\n", in8(PCIL0_LATTIM));
printf("PCIL0_HDTYPE = %#04x\n", in8(PCIL0_HDTYPE));
printf("PCIL0_BIST = %#04x\n", in8(PCIL0_BIST));
printf("PCIX0_BAR0 = %#010lx\n", in32r(PCIX0_BAR0));
printf("PCIX0_BAR1 = %#010lx\n", in32r(PCIX0_BAR1));
printf("PCIX0_BAR2 = %#010lx\n", in32r(PCIX0_BAR2));
printf("PCIX0_BAR3 = %#010lx\n", in32r(PCIX0_BAR3));
printf("PCIX0_BAR4 = %#010lx\n", in32r(PCIX0_BAR4));
printf("PCIX0_BAR5 = %#010lx\n", in32r(PCIX0_BAR5));
printf("PCIL0_BAR0 = %#010lx\n", in32r(PCIL0_BAR0));
printf("PCIL0_BAR1 = %#010lx\n", in32r(PCIL0_BAR1));
printf("PCIL0_BAR2 = %#010lx\n", in32r(PCIL0_BAR2));
printf("PCIL0_BAR3 = %#010lx\n", in32r(PCIL0_BAR3));
printf("PCIL0_BAR4 = %#010lx\n", in32r(PCIL0_BAR4));
printf("PCIL0_BAR5 = %#010lx\n", in32r(PCIL0_BAR5));
printf("PCIX0_CISPTR = %#010lx\n", in32r(PCIX0_CISPTR));
printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID));
printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID));
printf("PCIX0_EROMBA = %#010lx\n", in32r(PCIX0_EROMBA));
printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP));
printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN));
printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN));
printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT));
printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY));
printf("PCIL0_CISPTR = %#010lx\n", in32r(PCIL0_CISPTR));
printf("PCIL0_SBSSYSVID = %#010x\n", in16r(PCIL0_SBSYSVID));
printf("PCIL0_SBSSYSID = %#010x\n", in16r(PCIL0_SBSYSID));
printf("PCIL0_EROMBA = %#010lx\n", in32r(PCIL0_EROMBA));
printf("PCIL0_CAP = %#04x\n", in8(PCIL0_CAP));
printf("PCIL0_INTLN = %#04x\n", in8(PCIL0_INTLN));
printf("PCIL0_INTPN = %#04x\n", in8(PCIL0_INTPN));
printf("PCIL0_MINGNT = %#04x\n", in8(PCIL0_MINGNT));
printf("PCIL0_MAXLTNCY = %#04x\n", in8(PCIL0_MAXLTNCY));
printf("PCIX0_BRDGOPT1 = %#010lx\n", in32r(PCIX0_BRDGOPT1));
printf("PCIX0_BRDGOPT2 = %#010lx\n", in32r(PCIX0_BRDGOPT2));
printf("PCIL0_BRDGOPT1 = %#010lx\n", in32r(PCIL0_BRDGOPT1));
printf("PCIL0_BRDGOPT2 = %#010lx\n", in32r(PCIL0_BRDGOPT2));
printf("PCIX0_POM0LAL = %#010lx\n", in32r(PCIX0_POM0LAL));
printf("PCIX0_POM0LAH = %#010lx\n", in32r(PCIX0_POM0LAH));
printf("PCIX0_POM0SA = %#010lx\n", in32r(PCIX0_POM0SA));
printf("PCIX0_POM0PCILAL = %#010lx\n", in32r(PCIX0_POM0PCIAL));
printf("PCIX0_POM0PCILAH = %#010lx\n", in32r(PCIX0_POM0PCIAH));
printf("PCIX0_POM1LAL = %#010lx\n", in32r(PCIX0_POM1LAL));
printf("PCIX0_POM1LAH = %#010lx\n", in32r(PCIX0_POM1LAH));
printf("PCIX0_POM1SA = %#010lx\n", in32r(PCIX0_POM1SA));
printf("PCIX0_POM1PCILAL = %#010lx\n", in32r(PCIX0_POM1PCIAL));
printf("PCIX0_POM1PCILAH = %#010lx\n", in32r(PCIX0_POM1PCIAH));
printf("PCIX0_POM2SA = %#010lx\n", in32r(PCIX0_POM2SA));
printf("PCIL0_POM0LAL = %#010lx\n", in32r(PCIL0_POM0LAL));
printf("PCIL0_POM0LAH = %#010lx\n", in32r(PCIL0_POM0LAH));
printf("PCIL0_POM0SA = %#010lx\n", in32r(PCIL0_POM0SA));
printf("PCIL0_POM0PCILAL = %#010lx\n", in32r(PCIL0_POM0PCIAL));
printf("PCIL0_POM0PCILAH = %#010lx\n", in32r(PCIL0_POM0PCIAH));
printf("PCIL0_POM1LAL = %#010lx\n", in32r(PCIL0_POM1LAL));
printf("PCIL0_POM1LAH = %#010lx\n", in32r(PCIL0_POM1LAH));
printf("PCIL0_POM1SA = %#010lx\n", in32r(PCIL0_POM1SA));
printf("PCIL0_POM1PCILAL = %#010lx\n", in32r(PCIL0_POM1PCIAL));
printf("PCIL0_POM1PCILAH = %#010lx\n", in32r(PCIL0_POM1PCIAH));
printf("PCIL0_POM2SA = %#010lx\n", in32r(PCIL0_POM2SA));
printf("PCIX0_PIM0SA = %#010lx\n", in32r(PCIX0_PIM0SA));
printf("PCIX0_PIM0LAL = %#010lx\n", in32r(PCIX0_PIM0LAL));
printf("PCIX0_PIM0LAH = %#010lx\n", in32r(PCIX0_PIM0LAH));
printf("PCIX0_PIM1SA = %#010lx\n", in32r(PCIX0_PIM1SA));
printf("PCIX0_PIM1LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
printf("PCIX0_PIM1LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
printf("PCIX0_PIM2SA = %#010lx\n", in32r(PCIX0_PIM1SA));
printf("PCIX0_PIM2LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
printf("PCIX0_PIM2LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
printf("PCIL0_PIM0SA = %#010lx\n", in32r(PCIL0_PIM0SA));
printf("PCIL0_PIM0LAL = %#010lx\n", in32r(PCIL0_PIM0LAL));
printf("PCIL0_PIM0LAH = %#010lx\n", in32r(PCIL0_PIM0LAH));
printf("PCIL0_PIM1SA = %#010lx\n", in32r(PCIL0_PIM1SA));
printf("PCIL0_PIM1LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
printf("PCIL0_PIM1LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
printf("PCIL0_PIM2SA = %#010lx\n", in32r(PCIL0_PIM1SA));
printf("PCIL0_PIM2LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
printf("PCIL0_PIM2LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
printf("PCIX0_XSTS = %#010lx\n", in32r(PCIX0_STS));
printf("PCIL0_XSTS = %#010lx\n", in32r(PCIL0_STS));
}
int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])

22
board/amcc/taishan/taishan.c
View file

@ -254,28 +254,28 @@ void pci_target_init(struct pci_controller * hose )
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
out32r( PCIL0_PIM0SA, 0 ); /* disable */
out32r( PCIL0_PIM1SA, 0 ); /* disable */
out32r( PCIL0_PIM2SA, 0 ); /* disable */
out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIL0_PIM0LAH, 0 );
out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
out32r( PCIL0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */

1
board/amcc/taishan/u-boot.lds
View file

@ -69,7 +69,6 @@ SECTIONS
board/amcc/taishan/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/walnut/u-boot.lds
View file

@ -63,7 +63,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/amcc/yosemite/u-boot.lds
View file

@ -69,7 +69,6 @@ SECTIONS
board/amcc/yosemite/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

28
board/amcc/yosemite/yosemite.c
View file

@ -408,22 +408,22 @@ void pci_target_init(struct pci_controller *hose)
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers

1
board/amcc/yucca/u-boot.lds
View file

@ -69,7 +69,6 @@ SECTIONS
board/amcc/yucca/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

25
board/amcc/yucca/yucca.c
View file

@ -32,6 +32,7 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/4xx_pcie.h>
#include <asm/errno.h>
#include "yucca.h"
@ -632,27 +633,27 @@ void pci_target_init(struct pci_controller * hose )
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
out32r( PCIL0_PIM0SA, 0 ); /* disable */
out32r( PCIL0_PIM1SA, 0 ); /* disable */
out32r( PCIL0_PIM2SA, 0 ); /* disable */
out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
/*-------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIL0_PIM0LAH, 0 );
out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIL0_BAR0, 0 );
/*-------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
@ -830,6 +831,8 @@ void pcie_setup_hoses(int busno)
yucca_setup_pcie_fpga_rootpoint(i);
ret = ppc4xx_init_pcie_rootport(i);
}
if (ret == -ENODEV)
continue;
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");

1
board/amirix/ap1000/u-boot.lds
View file

@ -72,7 +72,6 @@ SECTIONS
/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

13
board/armltd/integrator/integrator.c
View file

@ -34,9 +34,7 @@
*/
#include <common.h>
#ifdef CONFIG_PCI
#include <netdev.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -127,9 +125,16 @@ extern void dram_query(void);
return 0;
}
#ifdef CONFIG_PCI
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
#ifdef CONFIG_PCI
rc += pci_eth_init(bis);
#endif
return rc;
}
#endif

12
board/armltd/versatile/versatile.c
View file

@ -34,6 +34,7 @@
*/
#include <common.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@ -89,3 +90,14 @@ int dram_init (void)
{
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

8
board/bf533-ezkit/bf533-ezkit.c
View file

@ -26,6 +26,7 @@
*/
#include <common.h>
#include <netdev.h>
#include "psd4256.h"
#include "flash-defines.h"
@ -57,3 +58,10 @@ int misc_init_r(void)
return 0;
}
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{
return smc91111_initialize(0, CONFIG_SMC91111_BASE);
}
#endif

8
board/bf533-stamp/bf533-stamp.c
View file

@ -26,6 +26,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include "bf533-stamp.h"
@ -283,3 +284,10 @@ void __led_toggle(led_id_t mask)
}
#endif
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{
return smc91111_initialize(0, CONFIG_SMC91111_BASE);
}
#endif

8
board/bf538f-ezkit/bf538f-ezkit.c
View file

@ -7,6 +7,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <config.h>
#include <asm/blackfin.h>
@ -25,3 +26,10 @@ phys_size_t initdram(int board_type)
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{
return smc91111_initialize(0, CONFIG_SMC91111_BASE);
}
#endif

8
board/bf561-ezkit/bf561-ezkit.c
View file

@ -26,6 +26,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -43,3 +44,10 @@ phys_size_t initdram(int board_type)
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{
return smc91111_initialize(0, CONFIG_SMC91111_BASE);
}
#endif

8
board/blackstamp/blackstamp.c
View file

@ -12,6 +12,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -44,3 +45,10 @@ void swap_to(int device_id)
SSYNC();
}
#endif
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{
return smc91111_initialize(0, CONFIG_SMC91111_BASE);
}
#endif

1
board/c2mon/u-boot.lds
View file

@ -66,7 +66,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/c2mon/u-boot.lds.debug
View file

@ -64,7 +64,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

12
board/cerf250/cerf250.c
View file

@ -26,6 +26,7 @@
*/
#include <common.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@ -71,3 +72,14 @@ int dram_init (void)
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

8
board/cm-bf533/cm-bf533.c
View file

@ -7,6 +7,7 @@
*/
#include <common.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@ -23,3 +24,10 @@ phys_size_t initdram(int board_type)
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{
return smc91111_initialize(0, CONFIG_SMC91111_BASE);
}
#endif

8
board/cm-bf561/cm-bf561.c
View file

@ -7,6 +7,7 @@
*/
#include <common.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@ -23,3 +24,10 @@ phys_size_t initdram(int board_type)
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
#ifdef CONFIG_SMC91111
int board_eth_init(bd_t *bis)
{
return smc91111_initialize(0, CONFIG_SMC91111_BASE);
}
#endif

1
board/cm5200/u-boot.lds
View file

@ -52,7 +52,6 @@ SECTIONS
{
cpu/mpc5xxx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.eh_frame)

1
board/cogent/u-boot.lds
View file

@ -54,7 +54,6 @@ SECTIONS
{
*(.text)
common/env_embedded.o(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/cogent/u-boot.lds.debug
View file

@ -64,7 +64,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

12
board/cradle/cradle.c
View file

@ -27,6 +27,7 @@
#include <asm/arch/pxa-regs.h>
#include <common.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@ -223,3 +224,14 @@ dram_init (void)
PHYS_SDRAM_3_SIZE +
PHYS_SDRAM_4_SIZE );
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

1
board/cray/L1/u-boot.lds
View file

@ -78,7 +78,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/cray/L1/u-boot.lds.debug
View file

@ -64,7 +64,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/csb272/u-boot.lds
View file

@ -79,7 +79,6 @@ SECTIONS
/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/csb472/u-boot.lds
View file

@ -79,7 +79,6 @@ SECTIONS
/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/dave/PPChameleonEVB/u-boot.lds
View file

@ -73,7 +73,6 @@ SECTIONS
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

4
board/davinci/dm355evm/dm355evm.c
View file

@ -92,8 +92,8 @@ int board_eth_init(bd_t *bis)
static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
{
struct nand_chip *this = mtd->priv;
u32 wbase = (u32) this->IO_ADDR_W;
u32 rbase = (u32) this->IO_ADDR_R;
unsigned long wbase = (unsigned long) this->IO_ADDR_W;
unsigned long rbase = (unsigned long) this->IO_ADDR_R;
if (chip == 1) {
__set_bit(14, &wbase);

52
board/davinci/dm355leopard/Makefile Normal file
View file

@ -0,0 +1,52 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o
SOBJS :=
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# This is for $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

6
board/davinci/dm355leopard/config.mk Normal file
View file

@ -0,0 +1,6 @@
# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
TEXT_BASE = 0x81080000

98
board/davinci/dm355leopard/dm355leopard.c Normal file
View file

@ -0,0 +1,98 @@
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <nand.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio_defs.h>
#include <asm/arch/nand_defs.h>
#include "../common/misc.h"
#include <net.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
struct davinci_gpio *gpio01_base =
(struct davinci_gpio *)DAVINCI_GPIO_BANK01;
struct davinci_gpio *gpio23_base =
(struct davinci_gpio *)DAVINCI_GPIO_BANK23;
struct davinci_gpio *gpio67_base =
(struct davinci_gpio *)DAVINCI_GPIO_BANK67;
gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
/* GIO 9 & 10 are used for IO */
writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
/* Interrupt set GIO 9 */
writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
/* set GIO 9 input */
writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
/* Both edge trigger GIO 9 */
writel((readl(&gpio01_base->set_rising) | (1 << 9)),
&gpio01_base->set_rising);
writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
/* output low */
writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
&gpio01_base->set_data);
/* set GIO 10 output */
writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
/* output high */
writel((readl(&gpio01_base->set_data) | (1 << 10)),
&gpio01_base->set_data);
/* set GIO 32 output */
writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
/* output High */
writel((readl(&gpio23_base->set_data) | (1 << 0)),
&gpio23_base->set_data);
/* Enable UART1 MUX Lines */
writel((readl(PINMUX0) & ~3), PINMUX0);
writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
writel((readl(&gpio67_base->set_data) | (1 << 6)),
&gpio67_base->set_data);
return 0;
}
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
return dm9000_initialize(bis);
}
#endif
#ifdef CONFIG_NAND_DAVINCI
int board_nand_init(struct nand_chip *nand)
{
davinci_nand_init(nand);
return 0;
}
#endif

5
board/davinci/dm365evm/dm365evm.c
View file

@ -1,4 +1,5 @@
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -79,8 +80,8 @@ int board_eth_init(bd_t *bis)
static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
{
struct nand_chip *this = mtd->priv;
u32 wbase = (u32) this->IO_ADDR_W;
u32 rbase = (u32) this->IO_ADDR_R;
unsigned long wbase = (unsigned long) this->IO_ADDR_W;
unsigned long rbase = (unsigned long) this->IO_ADDR_R;
if (chip == 1) {
__set_bit(14, &wbase);

52
board/davinci/dm6467evm/Makefile Normal file
View file

@ -0,0 +1,52 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o
SOBJS :=
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# This is for $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

2
board/davinci/dm6467evm/config.mk Normal file
View file

@ -0,0 +1,2 @@
#Provide at least 16MB spacing between us and the Linux Kernel image
TEXT_BASE = 0x81080000

31
board/davinci/dm6467evm/dm6467evm.c Normal file
View file

@ -0,0 +1,31 @@
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}

12
board/delta/delta.c
View file

@ -22,6 +22,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <i2c.h>
#include <da9030.h>
#include <malloc.h>
@ -363,3 +364,14 @@ void hw_watchdog_reset(void)
i2c_reg_write(addr, SYS_CONTROL_A, val);
}
#endif
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

30
board/digsy_mtc/cmd_mtc.c
View file

@ -320,36 +320,6 @@ static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
ARRAY_SIZE(cmd_mtc_sub), cmdtp, flag, argc, argv);
}
/* Relocate the command table function pointers when running in RAM */
int mtc_cmd_init_r(void)
{
cmd_tbl_t *cmdtp;
for (cmdtp = &cmd_mtc_sub[0]; cmdtp !=
&cmd_mtc_sub[ARRAY_SIZE(cmd_mtc_sub)]; cmdtp++) {
ulong addr;
addr = (ulong)(cmdtp->cmd) + gd->reloc_off;
cmdtp->cmd =
(int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
addr = (ulong)(cmdtp->name) + gd->reloc_off;
cmdtp->name = (char *)addr;
if (cmdtp->usage) {
addr = (ulong)(cmdtp->usage) + gd->reloc_off;
cmdtp->usage = (char *)addr;
}
#ifdef CONFIG_SYS_LONGHELP
if (cmdtp->help) {
addr = (ulong)(cmdtp->help) + gd->reloc_off;
cmdtp->help = (char *)addr;
}
#endif
}
return 0;
}
int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
cmd_tbl_t *c;

2
board/digsy_mtc/digsy_mtc.c
View file

@ -240,7 +240,6 @@ void board_get_enetaddr (uchar * enet)
int misc_init_r(void)
{
extern int mtc_cmd_init_r (void);
uchar enetaddr[6];
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
@ -248,7 +247,6 @@ int misc_init_r(void)
eth_setenv_enetaddr("ethaddr", enetaddr);
}
mtc_cmd_init_r();
return 0;
}

12
board/dnp1110/dnp1110.c
View file

@ -23,6 +23,7 @@
*/
#include <common.h>
#include <netdev.h>
#include <SA-1100.h>
DECLARE_GLOBAL_DATA_PTR;
@ -53,3 +54,14 @@ int dram_init (void)
return (0);
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
return rc;
}
#endif

1
board/eltec/bab7xx/u-boot.lds
View file

@ -63,7 +63,6 @@ SECTIONS
/* common/env_embedded.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/eltec/elppc/u-boot.lds
View file

@ -63,7 +63,6 @@ SECTIONS
/* common/env_embedded.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/eltec/mhpc/u-boot.lds
View file

@ -56,7 +56,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/eltec/mhpc/u-boot.lds.debug
View file

@ -64,7 +64,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/emk/top860/u-boot.lds
View file

@ -55,7 +55,6 @@ SECTIONS
cpu/mpc8xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/emk/top860/u-boot.lds.debug
View file

@ -65,7 +65,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/ep88x/u-boot.lds
View file

@ -54,7 +54,6 @@ SECTIONS
{
cpu/mpc8xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

1
board/eric/u-boot.lds
View file

@ -78,7 +78,6 @@ SECTIONS
common/env_embedded.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/esd/adciop/u-boot.lds
View file

@ -60,7 +60,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

1
board/esd/apc405/u-boot.lds
View file

@ -60,7 +60,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;

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